Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26602

1

T1

19

T2

176

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23106

1

T1

19

T2

176

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3496

1

T11

11

T12

2

T13

73

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20603

1

T2

176

T4

185

T6

14

auto[1]

5999

1

T1

19

T3

3

T5

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22211

1

T1

19

T2

176

T3

3

auto[1]

4391

1

T11

23

T13

85

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	321	1			T13	1		T77	13		T145	18
values[0]	43	1			T13	24		T160	1		T185	1
values[1]	719	1			T5	12		T11	11		T14	5
values[2]	774	1			T12	1		T141	15		T148	3
values[3]	771	1			T11	13		T12	1		T149	5
values[4]	849	1			T13	10		T158	10		T43	6
values[5]	835	1			T9	1		T13	49		T14	1
values[6]	761	1			T13	18		T30	19		T159	9
values[7]	763	1			T13	15		T30	9		T33	17
values[8]	620	1			T144	13		T134	48		T161	18
values[9]	3043	1			T1	19		T3	3		T5	13
minimum	17103	1			T2	176		T4	185		T6	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	730	1			T11	11		T12	1		T13	24
values[1]	741	1			T148	3		T138	11		T236	42
values[2]	771	1			T11	13		T12	1		T149	5
values[3]	894	1			T13	25		T32	31		T158	10
values[4]	795	1			T9	1		T13	34		T14	1
values[5]	869	1			T13	33		T30	28		T149	9
values[6]	2795	1			T1	19		T3	3		T8	2
values[7]	625	1			T14	8		T144	21		T161	18
values[8]	912	1			T13	6		T44	2		T77	13
values[9]	120	1			T5	13		T137	17		T217	11
minimum	17350	1			T2	176		T4	185		T5	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

4163

1

T1

18

T5

23

T13

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	10		T76	1		T216	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	1		T12	1		T14	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T236	9		T34	6		T229	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T148	1		T138	1		T236	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T11	1		T149	5		T216	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	1		T136	11		T155	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T13	12		T43	6		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T32	17		T158	1		T159	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T9	1		T141	1		T43	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	12		T14	1		T145	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T30	3		T149	9		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T13	13		T30	10		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1460	1			T1	19		T3	3		T8	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T33	10		T134	25		T169	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T14	4		T144	8		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T144	13		T253	1		T34	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T44	1		T77	1		T145	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	2		T144	8		T149	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T5	13		T137	1		T217	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T140	5		T289	1		T290	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17047	1			T2	176		T4	185		T5	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T160	1		T38	3		T16	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	14		T76	7		T216	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	10		T141	14		T44	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T236	12		T34	8		T229	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T148	2		T138	10		T236	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	12		T216	10		T225	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T136	15		T155	4		T18	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T13	13		T147	7		T136	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T32	14		T158	9		T159	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T148	6		T260	10		T242	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T13	22		T145	5		T175	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T30	6		T159	8		T37	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T13	20		T30	9		T161	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T158	16		T197	13		T179	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T33	7		T134	23		T169	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T14	4		T161	17		T175	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T34	10		T229	1		T106	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T44	1		T77	12		T145	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	4		T145	11		T216	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T137	16		T266	12		T291	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T140	4		T290	15		T265	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	1		T13	12		T33	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T38	2		T16	4		T178	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T77	1		T145	11		T147	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T13	1		T175	8		T153	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T13	10		T292	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T160	1		T185	1		T286	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	12		T76	1		T216	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	1		T14	5		T43	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T155	1		T236	9		T34	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	1		T141	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T11	1		T149	5		T216	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	1		T136	11		T156	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T13	3		T43	6		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T158	1		T159	13		T155	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T9	1		T13	9		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T13	12		T14	1		T32	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T159	1		T176	9		T148	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T13	12		T30	10		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T30	3		T158	1		T45	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T13	1		T33	10		T169	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T161	1		T175	6		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T144	13		T134	25		T34	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1569	1			T1	19		T3	3		T5	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T13	1		T144	8		T149	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16969	1			T2	176		T4	185		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T77	12		T145	7		T147	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T175	2		T153	13		T198	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T13	14		T292	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T76	7		T216	4		T17	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	10		T44	12		T38	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T236	12		T34	8		T229	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T141	14		T148	2		T138	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T11	12		T216	10		T225	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T136	15		T166	16		T293	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T13	7		T147	7		T136	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T158	9		T159	13		T155	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	6		T222	1		T251	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T13	22		T32	14		T145	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T159	8		T148	6		T221	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T13	6		T30	9		T161	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T30	6		T158	16		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	14		T33	7		T169	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T161	17		T175	4		T137	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T134	23		T34	10		T106	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1056	1			T14	4		T44	1		T197	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	4		T145	11		T216	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T13	12		T33	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T13	15		T76	8		T216	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	11		T12	1		T14	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T236	13		T34	9		T229	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T148	3		T138	11		T236	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T11	13		T149	1		T216	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	1		T136	16		T155	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T13	17		T43	1		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T32	15		T158	10		T159	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T9	1		T141	1		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T13	24		T14	1		T145	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T30	7		T149	1		T159	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T13	24		T30	10		T161	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T1	1		T3	3		T8	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T33	8		T134	25		T169	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T14	7		T144	1		T161	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T144	1		T253	1		T34	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T44	2		T77	13		T145	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T13	6		T144	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T5	1		T137	17		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T140	5		T289	1		T290	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17156	1			T2	176		T4	185		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T160	1		T38	5		T16	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	9		T139	2		T140	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T14	2		T43	8		T44	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T236	8		T34	5		T229	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T236	9		T156	16		T186	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T149	4		T225	10		T42	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T136	10		T155	7		T156	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	8		T43	5		T136	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T32	16		T159	12		T243	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T43	13		T148	7		T232	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T13	10		T145	2		T175	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T30	2		T149	8		T37	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	9		T30	9		T217	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1132	1			T1	18		T45	11		T228	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T33	9		T134	23		T169	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T14	1		T144	7		T175	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T144	12		T34	11		T106	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T145	10		T176	12		T39	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T144	7		T149	13		T145	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T5	12		T217	10		T266	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T140	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T5	11		T146	10		T270	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T16	2		T178	6		T221	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T77	13		T145	8		T147	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T13	1		T175	3		T153	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T13	15		T292	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T160	1		T185	1		T286	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	1		T76	8		T216	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T11	11		T14	3		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T155	1		T236	13		T34	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	1		T141	15		T148	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T11	13		T149	1		T216	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	1		T136	16		T156	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T13	10		T43	1		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T158	10		T159	14		T155	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T9	1		T13	7		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T13	24		T14	1		T32	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T159	9		T176	1		T148	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T13	9		T30	10		T161	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T30	7		T158	17		T45	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	15		T33	8		T169	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T161	18		T175	5		T137	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T144	1		T134	25		T34	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1407	1			T1	1		T3	3		T5	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T13	5		T144	1		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17103	1			T2	176		T4	185		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T145	10		T176	12		T39	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T175	7		T274	10		T294	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T13	9		T292	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T182	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	11		T146	10		T139	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	2		T43	8		T44	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T236	8		T34	5		T229	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T236	9		T156	16		T171	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T149	4		T225	10		T42	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T136	10		T156	20		T229	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T43	5		T136	15		T213	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T159	12		T155	7		T243	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	8		T43	13		T251	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	10		T32	16		T145	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T176	8		T148	7		T221	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	9		T30	9		T175	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T30	2		T45	11		T149	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T33	9		T169	4		T227	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T175	5		T170	9		T192	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T144	12		T134	23		T34	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T1	18		T5	12		T14	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T144	7		T149	13		T145	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

auto[0]

4163

1

T1

18

T5

23

T13

36