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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.79 99.07 96.67 100.00 100.00 98.83 98.33 91.66


Total test records in report: 918
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T798 /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.890351183 Jul 12 05:07:42 PM PDT 24 Jul 12 05:15:13 PM PDT 24 209083298108 ps
T799 /workspace/coverage/default/37.adc_ctrl_filters_polled.4178970225 Jul 12 05:07:19 PM PDT 24 Jul 12 05:10:30 PM PDT 24 162280251223 ps
T800 /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.317052562 Jul 12 05:07:28 PM PDT 24 Jul 12 05:11:02 PM PDT 24 162968033739 ps
T801 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3845188001 Jul 12 05:03:50 PM PDT 24 Jul 12 05:03:53 PM PDT 24 297531043 ps
T53 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3597588049 Jul 12 05:03:50 PM PDT 24 Jul 12 05:03:53 PM PDT 24 363442130 ps
T802 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3479373330 Jul 12 05:03:51 PM PDT 24 Jul 12 05:03:54 PM PDT 24 343963029 ps
T50 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2459148150 Jul 12 05:03:34 PM PDT 24 Jul 12 05:03:41 PM PDT 24 2391239068 ps
T129 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.707054315 Jul 12 05:03:54 PM PDT 24 Jul 12 05:03:56 PM PDT 24 385314171 ps
T803 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.720014434 Jul 12 05:03:47 PM PDT 24 Jul 12 05:03:50 PM PDT 24 446581177 ps
T804 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.805080139 Jul 12 05:03:52 PM PDT 24 Jul 12 05:03:55 PM PDT 24 313808469 ps
T805 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2486678667 Jul 12 05:03:51 PM PDT 24 Jul 12 05:03:53 PM PDT 24 325313840 ps
T51 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2839468789 Jul 12 05:03:52 PM PDT 24 Jul 12 05:04:00 PM PDT 24 2290946975 ps
T59 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1864466416 Jul 12 05:03:41 PM PDT 24 Jul 12 05:03:44 PM PDT 24 449626898 ps
T52 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1854425321 Jul 12 05:03:37 PM PDT 24 Jul 12 05:03:43 PM PDT 24 2262992609 ps
T806 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.4068738472 Jul 12 05:03:52 PM PDT 24 Jul 12 05:03:54 PM PDT 24 529935315 ps
T807 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2146890216 Jul 12 05:03:35 PM PDT 24 Jul 12 05:03:37 PM PDT 24 303553713 ps
T112 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.833849009 Jul 12 05:03:52 PM PDT 24 Jul 12 05:03:55 PM PDT 24 411462958 ps
T54 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2645968218 Jul 12 05:03:43 PM PDT 24 Jul 12 05:03:55 PM PDT 24 4694220830 ps
T65 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.300625634 Jul 12 05:03:43 PM PDT 24 Jul 12 05:03:48 PM PDT 24 480656817 ps
T808 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1372805954 Jul 12 05:03:53 PM PDT 24 Jul 12 05:03:56 PM PDT 24 329576247 ps
T133 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2098752140 Jul 12 05:03:37 PM PDT 24 Jul 12 05:05:30 PM PDT 24 51776885592 ps
T113 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1791525020 Jul 12 05:03:57 PM PDT 24 Jul 12 05:03:59 PM PDT 24 368590669 ps
T809 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.540897483 Jul 12 05:03:59 PM PDT 24 Jul 12 05:04:02 PM PDT 24 331091350 ps
T810 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2213058350 Jul 12 05:03:59 PM PDT 24 Jul 12 05:04:02 PM PDT 24 531215205 ps
T114 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.4011717602 Jul 12 05:03:39 PM PDT 24 Jul 12 05:03:42 PM PDT 24 1244885413 ps
T115 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.588069351 Jul 12 05:03:43 PM PDT 24 Jul 12 05:03:47 PM PDT 24 360501686 ps
T55 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.223642565 Jul 12 05:03:36 PM PDT 24 Jul 12 05:03:49 PM PDT 24 4520641812 ps
T130 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3231293221 Jul 12 05:03:39 PM PDT 24 Jul 12 05:03:42 PM PDT 24 359844431 ps
T811 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1870992355 Jul 12 05:03:58 PM PDT 24 Jul 12 05:04:03 PM PDT 24 289585338 ps
T812 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3993813952 Jul 12 05:03:57 PM PDT 24 Jul 12 05:03:58 PM PDT 24 479830181 ps
T813 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2767190182 Jul 12 05:03:58 PM PDT 24 Jul 12 05:04:02 PM PDT 24 540762109 ps
T70 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3053620183 Jul 12 05:03:52 PM PDT 24 Jul 12 05:03:56 PM PDT 24 574530688 ps
T66 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3261507215 Jul 12 05:03:35 PM PDT 24 Jul 12 05:03:37 PM PDT 24 534582460 ps
T64 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.419868946 Jul 12 05:03:57 PM PDT 24 Jul 12 05:04:01 PM PDT 24 2574967190 ps
T814 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.577860888 Jul 12 05:03:39 PM PDT 24 Jul 12 05:03:42 PM PDT 24 694547602 ps
T56 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2443337843 Jul 12 05:03:44 PM PDT 24 Jul 12 05:03:58 PM PDT 24 3950937888 ps
T815 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1510842057 Jul 12 05:03:50 PM PDT 24 Jul 12 05:03:52 PM PDT 24 454127470 ps
T92 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3546685495 Jul 12 05:03:41 PM PDT 24 Jul 12 05:03:44 PM PDT 24 372896369 ps
T131 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3144555384 Jul 12 05:03:42 PM PDT 24 Jul 12 05:03:45 PM PDT 24 509677814 ps
T816 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.4243085599 Jul 12 05:03:52 PM PDT 24 Jul 12 05:03:55 PM PDT 24 398075827 ps
T132 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3816029267 Jul 12 05:03:44 PM PDT 24 Jul 12 05:03:51 PM PDT 24 2623702793 ps
T69 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.74772009 Jul 12 05:03:51 PM PDT 24 Jul 12 05:03:56 PM PDT 24 459600369 ps
T83 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2692092640 Jul 12 05:03:34 PM PDT 24 Jul 12 05:03:40 PM PDT 24 4670312300 ps
T60 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1437115222 Jul 12 05:03:48 PM PDT 24 Jul 12 05:03:54 PM PDT 24 4500499799 ps
T817 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.547240583 Jul 12 05:03:48 PM PDT 24 Jul 12 05:03:51 PM PDT 24 335310366 ps
T67 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2190539242 Jul 12 05:03:33 PM PDT 24 Jul 12 05:03:36 PM PDT 24 559122376 ps
T71 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3609877732 Jul 12 05:03:43 PM PDT 24 Jul 12 05:03:49 PM PDT 24 428348718 ps
T111 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.151161500 Jul 12 05:03:38 PM PDT 24 Jul 12 05:03:41 PM PDT 24 841917671 ps
T116 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2616434985 Jul 12 05:03:28 PM PDT 24 Jul 12 05:05:02 PM PDT 24 26053554507 ps
T117 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1422879946 Jul 12 05:03:37 PM PDT 24 Jul 12 05:03:41 PM PDT 24 791846596 ps
T818 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2055334122 Jul 12 05:03:53 PM PDT 24 Jul 12 05:03:56 PM PDT 24 326043527 ps
T819 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3528369634 Jul 12 05:03:42 PM PDT 24 Jul 12 05:03:45 PM PDT 24 488035838 ps
T820 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3272041958 Jul 12 05:03:45 PM PDT 24 Jul 12 05:03:48 PM PDT 24 614662961 ps
T821 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3519484077 Jul 12 05:03:44 PM PDT 24 Jul 12 05:03:48 PM PDT 24 433048020 ps
T822 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3693602905 Jul 12 05:03:53 PM PDT 24 Jul 12 05:03:55 PM PDT 24 476413624 ps
T118 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2015766515 Jul 12 05:03:36 PM PDT 24 Jul 12 05:03:38 PM PDT 24 539190242 ps
T823 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2002180681 Jul 12 05:03:42 PM PDT 24 Jul 12 05:03:45 PM PDT 24 401028621 ps
T325 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.258347193 Jul 12 05:03:35 PM PDT 24 Jul 12 05:03:39 PM PDT 24 4231876644 ps
T824 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2153537207 Jul 12 05:03:59 PM PDT 24 Jul 12 05:04:03 PM PDT 24 298658687 ps
T825 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2544989289 Jul 12 05:03:52 PM PDT 24 Jul 12 05:03:55 PM PDT 24 374643389 ps
T826 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.4142714558 Jul 12 05:03:57 PM PDT 24 Jul 12 05:04:00 PM PDT 24 550861269 ps
T827 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3509360641 Jul 12 05:03:48 PM PDT 24 Jul 12 05:03:51 PM PDT 24 473944912 ps
T828 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2431403736 Jul 12 05:03:57 PM PDT 24 Jul 12 05:03:59 PM PDT 24 575811173 ps
T829 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3280426614 Jul 12 05:03:43 PM PDT 24 Jul 12 05:03:48 PM PDT 24 2849936222 ps
T323 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3199989771 Jul 12 05:03:44 PM PDT 24 Jul 12 05:03:50 PM PDT 24 4165228516 ps
T830 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2671406517 Jul 12 05:03:49 PM PDT 24 Jul 12 05:03:54 PM PDT 24 463784392 ps
T831 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4211912674 Jul 12 05:03:58 PM PDT 24 Jul 12 05:04:01 PM PDT 24 443423053 ps
T832 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1696617739 Jul 12 05:03:41 PM PDT 24 Jul 12 05:03:43 PM PDT 24 514215490 ps
T833 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1063181702 Jul 12 05:03:57 PM PDT 24 Jul 12 05:04:01 PM PDT 24 2566292022 ps
T834 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2507467107 Jul 12 05:03:41 PM PDT 24 Jul 12 05:03:45 PM PDT 24 988922848 ps
T835 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1992846797 Jul 12 05:03:40 PM PDT 24 Jul 12 05:03:43 PM PDT 24 419025830 ps
T836 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1815969744 Jul 12 05:03:57 PM PDT 24 Jul 12 05:04:00 PM PDT 24 548830204 ps
T837 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.109591381 Jul 12 05:14:38 PM PDT 24 Jul 12 05:14:41 PM PDT 24 695036052 ps
T838 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.601709021 Jul 12 05:03:49 PM PDT 24 Jul 12 05:03:52 PM PDT 24 371105528 ps
T839 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1288543784 Jul 12 05:03:43 PM PDT 24 Jul 12 05:03:46 PM PDT 24 349528099 ps
T840 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2156911145 Jul 12 05:03:57 PM PDT 24 Jul 12 05:04:00 PM PDT 24 451319890 ps
T841 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.847032435 Jul 12 05:03:44 PM PDT 24 Jul 12 05:03:48 PM PDT 24 371388998 ps
T119 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.339840113 Jul 12 05:03:49 PM PDT 24 Jul 12 05:03:51 PM PDT 24 325835144 ps
T842 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1002719490 Jul 12 05:03:51 PM PDT 24 Jul 12 05:03:53 PM PDT 24 480745042 ps
T843 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.999158363 Jul 12 05:03:53 PM PDT 24 Jul 12 05:04:07 PM PDT 24 8490702524 ps
T844 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.854813260 Jul 12 05:03:52 PM PDT 24 Jul 12 05:03:57 PM PDT 24 464931383 ps
T845 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.308901005 Jul 12 05:03:48 PM PDT 24 Jul 12 05:03:52 PM PDT 24 542672473 ps
T846 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1952713160 Jul 12 05:03:59 PM PDT 24 Jul 12 05:04:03 PM PDT 24 411124495 ps
T847 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4170961172 Jul 12 05:03:38 PM PDT 24 Jul 12 05:03:41 PM PDT 24 786977581 ps
T848 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2216221552 Jul 12 05:03:51 PM PDT 24 Jul 12 05:03:53 PM PDT 24 469814543 ps
T849 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.365362462 Jul 12 05:03:43 PM PDT 24 Jul 12 05:03:47 PM PDT 24 547578443 ps
T120 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1666908386 Jul 12 05:03:26 PM PDT 24 Jul 12 05:03:27 PM PDT 24 554326175 ps
T121 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2601633598 Jul 12 05:03:37 PM PDT 24 Jul 12 05:03:40 PM PDT 24 540897390 ps
T850 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.293060938 Jul 12 05:03:47 PM PDT 24 Jul 12 05:03:57 PM PDT 24 4065358597 ps
T851 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.463248621 Jul 12 05:03:40 PM PDT 24 Jul 12 05:03:43 PM PDT 24 407469777 ps
T852 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2704984956 Jul 12 05:03:44 PM PDT 24 Jul 12 05:03:49 PM PDT 24 493986092 ps
T853 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2923962483 Jul 12 05:03:33 PM PDT 24 Jul 12 05:03:35 PM PDT 24 617567919 ps
T854 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1212296812 Jul 12 05:03:47 PM PDT 24 Jul 12 05:03:51 PM PDT 24 4669080096 ps
T72 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2262843572 Jul 12 05:03:36 PM PDT 24 Jul 12 05:03:48 PM PDT 24 4294544026 ps
T855 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2986991995 Jul 12 05:03:38 PM PDT 24 Jul 12 05:03:42 PM PDT 24 404396584 ps
T856 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2926771942 Jul 12 05:03:36 PM PDT 24 Jul 12 05:03:40 PM PDT 24 4865179984 ps
T857 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3130722107 Jul 12 05:03:55 PM PDT 24 Jul 12 05:03:57 PM PDT 24 493073918 ps
T122 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1641816416 Jul 12 05:03:39 PM PDT 24 Jul 12 05:04:10 PM PDT 24 53361971073 ps
T858 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1329520002 Jul 12 05:03:49 PM PDT 24 Jul 12 05:03:51 PM PDT 24 507487660 ps
T859 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.283389650 Jul 12 05:03:35 PM PDT 24 Jul 12 05:03:37 PM PDT 24 538865176 ps
T860 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.706800659 Jul 12 05:03:48 PM PDT 24 Jul 12 05:03:50 PM PDT 24 570492128 ps
T861 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3295770393 Jul 12 05:03:35 PM PDT 24 Jul 12 05:03:37 PM PDT 24 296097053 ps
T123 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.559361488 Jul 12 05:03:44 PM PDT 24 Jul 12 05:03:48 PM PDT 24 797375503 ps
T862 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1469400233 Jul 12 05:06:57 PM PDT 24 Jul 12 05:07:02 PM PDT 24 2046068733 ps
T863 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2375140489 Jul 12 05:03:38 PM PDT 24 Jul 12 05:03:41 PM PDT 24 499583257 ps
T864 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1437738692 Jul 12 05:03:38 PM PDT 24 Jul 12 05:03:41 PM PDT 24 571770268 ps
T865 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.867373665 Jul 12 05:03:58 PM PDT 24 Jul 12 05:04:01 PM PDT 24 532257243 ps
T866 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1441007084 Jul 12 05:03:38 PM PDT 24 Jul 12 05:03:40 PM PDT 24 503901655 ps
T73 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1151683873 Jul 12 05:03:53 PM PDT 24 Jul 12 05:04:03 PM PDT 24 8124465934 ps
T867 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.107775209 Jul 12 05:03:48 PM PDT 24 Jul 12 05:03:50 PM PDT 24 426738823 ps
T868 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1235090832 Jul 12 05:03:48 PM PDT 24 Jul 12 05:03:53 PM PDT 24 402767995 ps
T869 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1989820046 Jul 12 05:03:46 PM PDT 24 Jul 12 05:03:48 PM PDT 24 350645248 ps
T870 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1107169950 Jul 12 05:03:49 PM PDT 24 Jul 12 05:03:52 PM PDT 24 478770283 ps
T871 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.196979512 Jul 12 05:03:59 PM PDT 24 Jul 12 05:04:03 PM PDT 24 344161168 ps
T872 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1982469771 Jul 12 05:03:40 PM PDT 24 Jul 12 05:03:43 PM PDT 24 484204396 ps
T873 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.658287226 Jul 12 05:03:34 PM PDT 24 Jul 12 05:03:37 PM PDT 24 529225243 ps
T874 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.300922369 Jul 12 05:03:36 PM PDT 24 Jul 12 05:03:38 PM PDT 24 493135612 ps
T875 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.4052824163 Jul 12 05:03:52 PM PDT 24 Jul 12 05:03:55 PM PDT 24 374640474 ps
T876 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.73510589 Jul 12 05:03:28 PM PDT 24 Jul 12 05:03:31 PM PDT 24 565022802 ps
T877 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.927262570 Jul 12 05:03:59 PM PDT 24 Jul 12 05:04:03 PM PDT 24 664549268 ps
T878 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3201657997 Jul 12 05:03:54 PM PDT 24 Jul 12 05:03:57 PM PDT 24 501571278 ps
T879 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2766634034 Jul 12 05:03:25 PM PDT 24 Jul 12 05:03:33 PM PDT 24 2406813949 ps
T880 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3020586748 Jul 12 05:03:42 PM PDT 24 Jul 12 05:03:50 PM PDT 24 4596127761 ps
T881 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3387989468 Jul 12 05:04:09 PM PDT 24 Jul 12 05:04:12 PM PDT 24 472985605 ps
T882 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2810517137 Jul 12 05:03:29 PM PDT 24 Jul 12 05:03:31 PM PDT 24 444016392 ps
T883 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.4275445202 Jul 12 05:03:36 PM PDT 24 Jul 12 05:03:39 PM PDT 24 543142213 ps
T884 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1353982617 Jul 12 05:03:48 PM PDT 24 Jul 12 05:03:51 PM PDT 24 436858086 ps
T885 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.52428573 Jul 12 05:03:40 PM PDT 24 Jul 12 05:03:44 PM PDT 24 1181932956 ps
T886 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.995885080 Jul 12 05:03:44 PM PDT 24 Jul 12 05:03:48 PM PDT 24 509936625 ps
T887 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3583211753 Jul 12 05:03:57 PM PDT 24 Jul 12 05:03:59 PM PDT 24 435775668 ps
T888 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2770326057 Jul 12 05:03:35 PM PDT 24 Jul 12 05:03:47 PM PDT 24 2913710881 ps
T889 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3614922456 Jul 12 05:03:43 PM PDT 24 Jul 12 05:03:49 PM PDT 24 550746455 ps
T890 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1272078416 Jul 12 05:03:28 PM PDT 24 Jul 12 05:03:31 PM PDT 24 399650059 ps
T891 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3974326817 Jul 12 05:03:59 PM PDT 24 Jul 12 05:04:04 PM PDT 24 690207964 ps
T892 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1062072340 Jul 12 05:03:44 PM PDT 24 Jul 12 05:03:47 PM PDT 24 447066147 ps
T893 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1904956593 Jul 12 05:03:51 PM PDT 24 Jul 12 05:04:03 PM PDT 24 4748717984 ps
T894 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.566977453 Jul 12 05:03:47 PM PDT 24 Jul 12 05:03:49 PM PDT 24 838967473 ps
T895 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2847636799 Jul 12 05:03:43 PM PDT 24 Jul 12 05:03:52 PM PDT 24 4587077247 ps
T896 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.727547189 Jul 12 05:03:53 PM PDT 24 Jul 12 05:04:01 PM PDT 24 2721013319 ps
T324 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2283209662 Jul 12 05:03:40 PM PDT 24 Jul 12 05:03:46 PM PDT 24 4702233724 ps
T897 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3484794638 Jul 12 05:03:50 PM PDT 24 Jul 12 05:03:56 PM PDT 24 4005506622 ps
T124 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1265909391 Jul 12 05:03:57 PM PDT 24 Jul 12 05:03:59 PM PDT 24 547127325 ps
T898 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3501824004 Jul 12 05:03:37 PM PDT 24 Jul 12 05:03:44 PM PDT 24 2418692273 ps
T899 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3346459236 Jul 12 05:03:44 PM PDT 24 Jul 12 05:03:48 PM PDT 24 396093448 ps
T326 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.842715597 Jul 12 05:03:44 PM PDT 24 Jul 12 05:03:58 PM PDT 24 7951423016 ps
T900 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.625714826 Jul 12 05:04:00 PM PDT 24 Jul 12 05:04:05 PM PDT 24 350279249 ps
T901 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1768579428 Jul 12 05:03:44 PM PDT 24 Jul 12 05:03:48 PM PDT 24 514196817 ps
T902 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.531603307 Jul 12 05:03:36 PM PDT 24 Jul 12 05:04:45 PM PDT 24 53207827334 ps
T903 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.965064367 Jul 12 05:03:35 PM PDT 24 Jul 12 05:03:37 PM PDT 24 642051419 ps
T125 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1350626577 Jul 12 05:03:36 PM PDT 24 Jul 12 05:04:17 PM PDT 24 36904964002 ps
T904 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.753171667 Jul 12 05:03:47 PM PDT 24 Jul 12 05:04:09 PM PDT 24 7916071552 ps
T905 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.134086896 Jul 12 05:03:57 PM PDT 24 Jul 12 05:03:59 PM PDT 24 462171110 ps
T906 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.4218649609 Jul 12 05:03:54 PM PDT 24 Jul 12 05:04:02 PM PDT 24 3942577316 ps
T907 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1043608624 Jul 12 05:03:27 PM PDT 24 Jul 12 05:03:32 PM PDT 24 10052057140 ps
T126 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1317249355 Jul 12 05:03:27 PM PDT 24 Jul 12 05:03:29 PM PDT 24 710382311 ps
T908 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1551141704 Jul 12 05:03:50 PM PDT 24 Jul 12 05:03:56 PM PDT 24 10241332348 ps
T127 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1055353589 Jul 12 05:03:34 PM PDT 24 Jul 12 05:03:38 PM PDT 24 1113683212 ps
T909 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2628333305 Jul 12 05:03:52 PM PDT 24 Jul 12 05:03:55 PM PDT 24 604262396 ps
T910 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.4274707013 Jul 12 05:03:34 PM PDT 24 Jul 12 05:03:37 PM PDT 24 4882488029 ps
T911 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.495390234 Jul 12 05:03:44 PM PDT 24 Jul 12 05:03:47 PM PDT 24 434668021 ps
T128 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2765727431 Jul 12 05:03:36 PM PDT 24 Jul 12 05:03:40 PM PDT 24 1018399115 ps
T912 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3249862358 Jul 12 05:03:25 PM PDT 24 Jul 12 05:03:27 PM PDT 24 923294575 ps
T913 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1007026329 Jul 12 05:03:41 PM PDT 24 Jul 12 05:03:45 PM PDT 24 2342755735 ps
T914 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3338297731 Jul 12 05:03:42 PM PDT 24 Jul 12 05:03:54 PM PDT 24 4147378883 ps
T915 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.103003345 Jul 12 05:03:41 PM PDT 24 Jul 12 05:03:44 PM PDT 24 2640177472 ps
T916 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.4028146937 Jul 12 05:03:33 PM PDT 24 Jul 12 05:03:45 PM PDT 24 5122658580 ps
T917 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.26664064 Jul 12 05:03:48 PM PDT 24 Jul 12 05:03:52 PM PDT 24 5415625719 ps
T918 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1310164422 Jul 12 05:03:37 PM PDT 24 Jul 12 05:03:39 PM PDT 24 530769199 ps

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3564884788
Short name T9
Test name
Test status
Simulation time 351498715400 ps
CPU time 621.19 seconds
Started Jul 12 05:04:12 PM PDT 24
Finished Jul 12 05:14:34 PM PDT 24
Peak memory 201984 kb
Host smart-61034bc3-9a43-4c71-b7bb-678671b23478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564884788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3564884788
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1541263672
Short name T13
Test name
Test status
Simulation time 2067964069188 ps
CPU time 605.08 seconds
Started Jul 12 05:05:11 PM PDT 24
Finished Jul 12 05:15:17 PM PDT 24
Peak memory 210528 kb
Host smart-fa55c246-8990-4db1-aa39-a92445b0c426
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541263672 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1541263672
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1000543396
Short name T14
Test name
Test status
Simulation time 546370700488 ps
CPU time 253.66 seconds
Started Jul 12 05:04:08 PM PDT 24
Finished Jul 12 05:08:22 PM PDT 24
Peak memory 210524 kb
Host smart-c8bdf113-f664-48c6-97c0-76beb1627462
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000543396 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1000543396
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1005674377
Short name T30
Test name
Test status
Simulation time 376461257863 ps
CPU time 181.17 seconds
Started Jul 12 05:05:24 PM PDT 24
Finished Jul 12 05:08:26 PM PDT 24
Peak memory 201756 kb
Host smart-c3f87683-899f-4e6f-acb8-844608510e7d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005674377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1005674377
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3125792912
Short name T11
Test name
Test status
Simulation time 466974070419 ps
CPU time 874.49 seconds
Started Jul 12 05:04:53 PM PDT 24
Finished Jul 12 05:19:29 PM PDT 24
Peak memory 210392 kb
Host smart-44db806f-657e-4e93-8c70-a9584e9707ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125792912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3125792912
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2926087247
Short name T229
Test name
Test status
Simulation time 588994574823 ps
CPU time 239.53 seconds
Started Jul 12 05:04:51 PM PDT 24
Finished Jul 12 05:08:53 PM PDT 24
Peak memory 201956 kb
Host smart-85a3f2c8-7767-4600-b03f-8b72213e9695
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926087247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2926087247
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2381686413
Short name T140
Test name
Test status
Simulation time 502744227640 ps
CPU time 492.62 seconds
Started Jul 12 05:05:38 PM PDT 24
Finished Jul 12 05:13:51 PM PDT 24
Peak memory 201864 kb
Host smart-7b552e0a-ad07-44ea-ae57-a84b49ca7a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381686413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2381686413
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.254493784
Short name T145
Test name
Test status
Simulation time 547973576938 ps
CPU time 256.5 seconds
Started Jul 12 05:04:42 PM PDT 24
Finished Jul 12 05:09:00 PM PDT 24
Peak memory 201884 kb
Host smart-47cf5a9e-a203-4092-8192-2adae4432c75
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254493784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gati
ng.254493784
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.419868946
Short name T64
Test name
Test status
Simulation time 2574967190 ps
CPU time 3.14 seconds
Started Jul 12 05:03:57 PM PDT 24
Finished Jul 12 05:04:01 PM PDT 24
Peak memory 211056 kb
Host smart-412e9d7e-6dff-4d6d-be40-587802813b76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419868946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.419868946
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.3515847470
Short name T230
Test name
Test status
Simulation time 544459825786 ps
CPU time 1272.5 seconds
Started Jul 12 05:08:35 PM PDT 24
Finished Jul 12 05:29:48 PM PDT 24
Peak memory 201800 kb
Host smart-2cd80e5d-ad1f-4835-9004-87c46677e651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515847470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3515847470
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.390573364
Short name T175
Test name
Test status
Simulation time 511283630127 ps
CPU time 591.27 seconds
Started Jul 12 05:06:30 PM PDT 24
Finished Jul 12 05:16:22 PM PDT 24
Peak memory 201780 kb
Host smart-55b00669-68b2-4274-9a9f-1c6d0b3ad3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390573364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.390573364
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1761594471
Short name T61
Test name
Test status
Simulation time 4312437511 ps
CPU time 10.91 seconds
Started Jul 12 05:04:12 PM PDT 24
Finished Jul 12 05:04:24 PM PDT 24
Peak memory 215936 kb
Host smart-cac984f7-d5aa-4578-8148-01a5f68b9860
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761594471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1761594471
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1555362288
Short name T134
Test name
Test status
Simulation time 344127399617 ps
CPU time 787.84 seconds
Started Jul 12 05:04:40 PM PDT 24
Finished Jul 12 05:17:50 PM PDT 24
Peak memory 201636 kb
Host smart-9dfc81f1-cf92-4025-be20-d2c641473eaf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555362288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1555362288
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.628961411
Short name T154
Test name
Test status
Simulation time 333645217613 ps
CPU time 96.85 seconds
Started Jul 12 05:05:01 PM PDT 24
Finished Jul 12 05:06:38 PM PDT 24
Peak memory 201932 kb
Host smart-e69b10f6-1c8e-4c50-95f5-4857a3165389
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628961411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.628961411
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3001631916
Short name T139
Test name
Test status
Simulation time 502892368277 ps
CPU time 1071.42 seconds
Started Jul 12 05:06:01 PM PDT 24
Finished Jul 12 05:23:53 PM PDT 24
Peak memory 201900 kb
Host smart-c09af25e-74da-4bfd-bf01-f694c45d4d1d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001631916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3001631916
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3597588049
Short name T53
Test name
Test status
Simulation time 363442130 ps
CPU time 1.69 seconds
Started Jul 12 05:03:50 PM PDT 24
Finished Jul 12 05:03:53 PM PDT 24
Peak memory 201424 kb
Host smart-50e1d27c-227b-4982-9cc6-1f96a374abd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597588049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3597588049
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1226779224
Short name T157
Test name
Test status
Simulation time 530254923362 ps
CPU time 487.04 seconds
Started Jul 12 05:04:06 PM PDT 24
Finished Jul 12 05:12:15 PM PDT 24
Peak memory 201756 kb
Host smart-1c84f530-6f58-440e-8d30-2756a92eed4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226779224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1226779224
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.2561637946
Short name T166
Test name
Test status
Simulation time 490967484646 ps
CPU time 316.32 seconds
Started Jul 12 05:04:07 PM PDT 24
Finished Jul 12 05:09:25 PM PDT 24
Peak memory 201784 kb
Host smart-4cbd359d-ff64-4da0-8a27-21b007d38909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561637946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.2561637946
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.730936425
Short name T103
Test name
Test status
Simulation time 626556496863 ps
CPU time 1327.64 seconds
Started Jul 12 05:08:32 PM PDT 24
Finished Jul 12 05:30:40 PM PDT 24
Peak memory 201812 kb
Host smart-90d39617-3178-4d88-8a18-95fea1e452dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730936425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.730936425
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.2101779750
Short name T1
Test name
Test status
Simulation time 194811965455 ps
CPU time 447.78 seconds
Started Jul 12 05:04:29 PM PDT 24
Finished Jul 12 05:11:58 PM PDT 24
Peak memory 201668 kb
Host smart-78903dad-2f22-49aa-8d4d-c543500e57bb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101779750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.2101779750
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1747709370
Short name T183
Test name
Test status
Simulation time 1244150583605 ps
CPU time 336.29 seconds
Started Jul 12 05:04:26 PM PDT 24
Finished Jul 12 05:10:04 PM PDT 24
Peak memory 210468 kb
Host smart-9aa18dd6-8d30-4406-be86-1dab590aacbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747709370 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1747709370
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1034842694
Short name T156
Test name
Test status
Simulation time 641165597262 ps
CPU time 355.58 seconds
Started Jul 12 05:07:32 PM PDT 24
Finished Jul 12 05:13:28 PM PDT 24
Peak memory 201900 kb
Host smart-1a143ac2-fa9b-4f22-9189-86da35f9584e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034842694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1034842694
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.2310811222
Short name T288
Test name
Test status
Simulation time 462487968308 ps
CPU time 853.27 seconds
Started Jul 12 05:09:23 PM PDT 24
Finished Jul 12 05:23:37 PM PDT 24
Peak memory 210212 kb
Host smart-16d381ba-927a-4313-a844-c86901b4d2f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310811222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.2310811222
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3359609394
Short name T217
Test name
Test status
Simulation time 514133038476 ps
CPU time 1203.46 seconds
Started Jul 12 05:04:06 PM PDT 24
Finished Jul 12 05:24:11 PM PDT 24
Peak memory 201952 kb
Host smart-fa8cab2f-ac74-457c-9aaf-f10e5d0d5be8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359609394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3359609394
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3716544452
Short name T16
Test name
Test status
Simulation time 82130692760 ps
CPU time 173.92 seconds
Started Jul 12 05:04:51 PM PDT 24
Finished Jul 12 05:07:46 PM PDT 24
Peak memory 210284 kb
Host smart-9699eae5-eea7-41bf-80d3-524b30f0a35b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716544452 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3716544452
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.982330459
Short name T273
Test name
Test status
Simulation time 350753856938 ps
CPU time 90.65 seconds
Started Jul 12 05:07:38 PM PDT 24
Finished Jul 12 05:09:10 PM PDT 24
Peak memory 201892 kb
Host smart-14d41ed2-ecea-4ba0-8405-d6dc8fa375fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982330459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
982330459
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.223642565
Short name T55
Test name
Test status
Simulation time 4520641812 ps
CPU time 11.56 seconds
Started Jul 12 05:03:36 PM PDT 24
Finished Jul 12 05:03:49 PM PDT 24
Peak memory 201688 kb
Host smart-6851a050-6a34-4eae-b469-fbdff59897ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223642565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.223642565
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.4221735996
Short name T214
Test name
Test status
Simulation time 349082604189 ps
CPU time 823.14 seconds
Started Jul 12 05:05:21 PM PDT 24
Finished Jul 12 05:19:04 PM PDT 24
Peak memory 201864 kb
Host smart-93be267c-606d-4eb1-80d1-8d448bf54ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221735996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.4221735996
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1300949373
Short name T387
Test name
Test status
Simulation time 326582544 ps
CPU time 0.8 seconds
Started Jul 12 05:04:44 PM PDT 24
Finished Jul 12 05:04:46 PM PDT 24
Peak memory 201508 kb
Host smart-41296f08-9eff-4474-b119-c6c9cf70d51d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300949373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1300949373
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1614479573
Short name T238
Test name
Test status
Simulation time 1206548274698 ps
CPU time 2700.42 seconds
Started Jul 12 05:05:59 PM PDT 24
Finished Jul 12 05:51:00 PM PDT 24
Peak memory 210664 kb
Host smart-550b689a-c006-45b4-a870-72960376b887
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614479573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1614479573
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.4055054305
Short name T180
Test name
Test status
Simulation time 327042497394 ps
CPU time 718.53 seconds
Started Jul 12 05:06:14 PM PDT 24
Finished Jul 12 05:18:13 PM PDT 24
Peak memory 201896 kb
Host smart-89289dee-54d1-4fb7-a6aa-a5f64efa2be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055054305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.4055054305
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.2976433222
Short name T251
Test name
Test status
Simulation time 331906243127 ps
CPU time 821 seconds
Started Jul 12 05:05:20 PM PDT 24
Finished Jul 12 05:19:01 PM PDT 24
Peak memory 201900 kb
Host smart-8cabe054-663d-4123-ae70-1ffa81852a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976433222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2976433222
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2961220046
Short name T165
Test name
Test status
Simulation time 499143429895 ps
CPU time 158.9 seconds
Started Jul 12 05:04:39 PM PDT 24
Finished Jul 12 05:07:20 PM PDT 24
Peak memory 201932 kb
Host smart-01c2d193-5b85-42cf-8eab-69c690dcc69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961220046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2961220046
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2656222917
Short name T367
Test name
Test status
Simulation time 339033855747 ps
CPU time 92.39 seconds
Started Jul 12 05:04:12 PM PDT 24
Finished Jul 12 05:05:46 PM PDT 24
Peak memory 201632 kb
Host smart-5cfc0a6b-b630-47d7-a485-86003e3baa6a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656222917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2656222917
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.3518725116
Short name T187
Test name
Test status
Simulation time 537898429460 ps
CPU time 326 seconds
Started Jul 12 05:04:00 PM PDT 24
Finished Jul 12 05:09:29 PM PDT 24
Peak memory 201768 kb
Host smart-46bf1aa2-b660-4fba-9647-5626d017aba5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518725116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.3518725116
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.4189098878
Short name T191
Test name
Test status
Simulation time 334739719681 ps
CPU time 181.71 seconds
Started Jul 12 05:04:52 PM PDT 24
Finished Jul 12 05:07:55 PM PDT 24
Peak memory 201912 kb
Host smart-3bffaaac-f6ee-4bd3-bea4-71de1c7a01a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189098878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.4189098878
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3199124767
Short name T185
Test name
Test status
Simulation time 322240397964 ps
CPU time 192 seconds
Started Jul 12 05:07:54 PM PDT 24
Finished Jul 12 05:11:07 PM PDT 24
Peak memory 201984 kb
Host smart-611df93e-31d9-4553-81f7-1ad5e95f759d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199124767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3199124767
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2616434985
Short name T116
Test name
Test status
Simulation time 26053554507 ps
CPU time 92.83 seconds
Started Jul 12 05:03:28 PM PDT 24
Finished Jul 12 05:05:02 PM PDT 24
Peak memory 201816 kb
Host smart-71fffbc3-fbd6-4a46-86e9-61662f560926
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616434985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2616434985
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.1200671191
Short name T301
Test name
Test status
Simulation time 170835726630 ps
CPU time 399.59 seconds
Started Jul 12 05:05:10 PM PDT 24
Finished Jul 12 05:11:51 PM PDT 24
Peak memory 201768 kb
Host smart-03a760fa-a6eb-4916-a59c-bdff90b5ecaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200671191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1200671191
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3362618356
Short name T57
Test name
Test status
Simulation time 226357315902 ps
CPU time 235.53 seconds
Started Jul 12 05:04:12 PM PDT 24
Finished Jul 12 05:08:09 PM PDT 24
Peak memory 217840 kb
Host smart-f1df3f42-945d-41bc-a5d8-93d754f3f239
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362618356 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3362618356
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1711441174
Short name T267
Test name
Test status
Simulation time 499621888243 ps
CPU time 1166.08 seconds
Started Jul 12 05:09:17 PM PDT 24
Finished Jul 12 05:28:44 PM PDT 24
Peak memory 201828 kb
Host smart-24d50baf-b15a-4c62-8bdf-1b134259a939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711441174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1711441174
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.82482223
Short name T296
Test name
Test status
Simulation time 523960158152 ps
CPU time 1234.7 seconds
Started Jul 12 05:04:34 PM PDT 24
Finished Jul 12 05:25:10 PM PDT 24
Peak memory 201880 kb
Host smart-ac6f1cd7-c518-48ed-9258-46b6f1075a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82482223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.82482223
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1459789061
Short name T300
Test name
Test status
Simulation time 27151903582 ps
CPU time 45.38 seconds
Started Jul 12 05:04:37 PM PDT 24
Finished Jul 12 05:05:24 PM PDT 24
Peak memory 210136 kb
Host smart-116828a3-1a3d-4659-a46b-d3326d3fb65b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459789061 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.1459789061
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.691155142
Short name T241
Test name
Test status
Simulation time 174795945309 ps
CPU time 390.12 seconds
Started Jul 12 05:05:07 PM PDT 24
Finished Jul 12 05:11:38 PM PDT 24
Peak memory 201900 kb
Host smart-5c2a8b70-ca26-4a85-bbbd-2114ba912739
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691155142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
691155142
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1552920378
Short name T162
Test name
Test status
Simulation time 496757304268 ps
CPU time 101.93 seconds
Started Jul 12 05:04:08 PM PDT 24
Finished Jul 12 05:05:51 PM PDT 24
Peak memory 201768 kb
Host smart-ccbd476a-c77b-4808-92e2-537a191fb049
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552920378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1552920378
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3329637666
Short name T292
Test name
Test status
Simulation time 176080771729 ps
CPU time 90.3 seconds
Started Jul 12 05:08:58 PM PDT 24
Finished Jul 12 05:10:29 PM PDT 24
Peak memory 210236 kb
Host smart-09009a7e-ebaf-4598-aaf5-7eacf58a0554
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329637666 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3329637666
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.385277617
Short name T188
Test name
Test status
Simulation time 353371084646 ps
CPU time 174.41 seconds
Started Jul 12 05:04:36 PM PDT 24
Finished Jul 12 05:07:32 PM PDT 24
Peak memory 201964 kb
Host smart-b8082e6b-84bd-470e-a9e6-f000de2f7af0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385277617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
wakeup.385277617
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3340959901
Short name T234
Test name
Test status
Simulation time 493936163661 ps
CPU time 311.02 seconds
Started Jul 12 05:05:17 PM PDT 24
Finished Jul 12 05:10:29 PM PDT 24
Peak memory 201844 kb
Host smart-c3a01f7e-2684-4078-824e-d0f1f6735139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340959901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3340959901
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.49155495
Short name T259
Test name
Test status
Simulation time 182222693707 ps
CPU time 99.3 seconds
Started Jul 12 05:06:12 PM PDT 24
Finished Jul 12 05:07:52 PM PDT 24
Peak memory 201852 kb
Host smart-fce1a420-3c03-4c58-bbb2-eba0912a5b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49155495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.49155495
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.4294107265
Short name T136
Test name
Test status
Simulation time 372755198670 ps
CPU time 222.08 seconds
Started Jul 12 05:08:48 PM PDT 24
Finished Jul 12 05:12:30 PM PDT 24
Peak memory 201912 kb
Host smart-083a9ddc-6f31-48bd-9f96-9b5d67b89be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294107265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.4294107265
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1017431408
Short name T33
Test name
Test status
Simulation time 173363335959 ps
CPU time 146.87 seconds
Started Jul 12 05:08:57 PM PDT 24
Finished Jul 12 05:11:25 PM PDT 24
Peak memory 201956 kb
Host smart-5a39cf54-8622-4da7-bcb7-777679f60a0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017431408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1017431408
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3433755970
Short name T199
Test name
Test status
Simulation time 593121521026 ps
CPU time 493.41 seconds
Started Jul 12 05:04:02 PM PDT 24
Finished Jul 12 05:12:19 PM PDT 24
Peak memory 210528 kb
Host smart-1aa2c7ef-198f-4d3d-bce8-ef9ee6914dd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433755970 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3433755970
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1588902713
Short name T211
Test name
Test status
Simulation time 112348256406 ps
CPU time 416.41 seconds
Started Jul 12 05:04:32 PM PDT 24
Finished Jul 12 05:11:30 PM PDT 24
Peak memory 202132 kb
Host smart-b7efface-ce82-4cd1-8413-be210b16c405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588902713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1588902713
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.3508911805
Short name T224
Test name
Test status
Simulation time 328580417651 ps
CPU time 262.99 seconds
Started Jul 12 05:06:33 PM PDT 24
Finished Jul 12 05:10:57 PM PDT 24
Peak memory 201828 kb
Host smart-6201e3eb-5f73-48b0-abb4-c6576706207d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508911805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3508911805
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2594192092
Short name T216
Test name
Test status
Simulation time 482949466999 ps
CPU time 288.92 seconds
Started Jul 12 05:07:03 PM PDT 24
Finished Jul 12 05:11:52 PM PDT 24
Peak memory 201912 kb
Host smart-4a03a836-dac0-4112-a364-8513403c50d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594192092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2594192092
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.255932515
Short name T43
Test name
Test status
Simulation time 534919547885 ps
CPU time 335.97 seconds
Started Jul 12 05:08:34 PM PDT 24
Finished Jul 12 05:14:10 PM PDT 24
Peak memory 201836 kb
Host smart-851f5c38-d82c-41ce-bc55-3785b895ae7f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255932515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_
wakeup.255932515
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3980183829
Short name T219
Test name
Test status
Simulation time 166586097928 ps
CPU time 371.35 seconds
Started Jul 12 05:04:29 PM PDT 24
Finished Jul 12 05:10:42 PM PDT 24
Peak memory 201792 kb
Host smart-f8e2affb-c552-4c07-bedc-6ddf72cc08a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980183829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3980183829
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1492998924
Short name T161
Test name
Test status
Simulation time 319114180479 ps
CPU time 328.59 seconds
Started Jul 12 05:04:34 PM PDT 24
Finished Jul 12 05:10:04 PM PDT 24
Peak memory 201840 kb
Host smart-8c7d88eb-c351-4872-9c42-bb64027b2b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492998924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1492998924
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.26664064
Short name T917
Test name
Test status
Simulation time 5415625719 ps
CPU time 2.83 seconds
Started Jul 12 05:03:48 PM PDT 24
Finished Jul 12 05:03:52 PM PDT 24
Peak memory 201848 kb
Host smart-b67e9f9a-4d9c-43f4-b165-c39beda01425
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26664064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_int
g_err.26664064
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3199989771
Short name T323
Test name
Test status
Simulation time 4165228516 ps
CPU time 3.43 seconds
Started Jul 12 05:03:44 PM PDT 24
Finished Jul 12 05:03:50 PM PDT 24
Peak memory 201824 kb
Host smart-8803a383-0048-4894-9e13-a1ed70667520
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199989771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3199989771
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.4077747059
Short name T254
Test name
Test status
Simulation time 499845547261 ps
CPU time 1063.18 seconds
Started Jul 12 05:04:44 PM PDT 24
Finished Jul 12 05:22:28 PM PDT 24
Peak memory 201896 kb
Host smart-7647c575-9544-41f5-b978-27f98a178b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077747059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.4077747059
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1484823683
Short name T76
Test name
Test status
Simulation time 166831096775 ps
CPU time 92.27 seconds
Started Jul 12 05:04:48 PM PDT 24
Finished Jul 12 05:06:22 PM PDT 24
Peak memory 201792 kb
Host smart-d3cac2d0-6041-48ba-a522-18dfde3c751e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484823683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1484823683
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.38839564
Short name T42
Test name
Test status
Simulation time 53479187325 ps
CPU time 150.45 seconds
Started Jul 12 05:05:17 PM PDT 24
Finished Jul 12 05:07:48 PM PDT 24
Peak memory 210540 kb
Host smart-4fae18ea-a86a-400c-aed6-c62a7db87942
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38839564 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.38839564
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.4084478292
Short name T47
Test name
Test status
Simulation time 119282196836 ps
CPU time 430.01 seconds
Started Jul 12 05:08:35 PM PDT 24
Finished Jul 12 05:15:46 PM PDT 24
Peak memory 202232 kb
Host smart-28df18f1-a566-4d15-a164-03c595d50a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084478292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.4084478292
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.402763733
Short name T277
Test name
Test status
Simulation time 489884918885 ps
CPU time 257.1 seconds
Started Jul 12 05:09:22 PM PDT 24
Finished Jul 12 05:13:40 PM PDT 24
Peak memory 201832 kb
Host smart-d586477b-ec42-4e0c-b0c4-1e6095141fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402763733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.402763733
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.109591381
Short name T837
Test name
Test status
Simulation time 695036052 ps
CPU time 2.49 seconds
Started Jul 12 05:14:38 PM PDT 24
Finished Jul 12 05:14:41 PM PDT 24
Peak memory 209968 kb
Host smart-6ad768c2-1068-4b37-ac2c-c0d30cd9b9e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109591381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.109591381
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1362501412
Short name T189
Test name
Test status
Simulation time 354217003080 ps
CPU time 57.32 seconds
Started Jul 12 05:03:57 PM PDT 24
Finished Jul 12 05:04:56 PM PDT 24
Peak memory 201784 kb
Host smart-416c6e6d-ef8b-4e86-8569-337961680b78
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362501412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1362501412
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.3027443254
Short name T335
Test name
Test status
Simulation time 65007481859 ps
CPU time 398.55 seconds
Started Jul 12 05:04:25 PM PDT 24
Finished Jul 12 05:11:06 PM PDT 24
Peak memory 202244 kb
Host smart-ce134bc4-7c2e-46bb-9830-4408be161d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027443254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3027443254
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1822008540
Short name T201
Test name
Test status
Simulation time 113145076861 ps
CPU time 570.22 seconds
Started Jul 12 05:04:44 PM PDT 24
Finished Jul 12 05:14:15 PM PDT 24
Peak memory 202208 kb
Host smart-7f0049a5-924d-4319-9eb3-204fb2872d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822008540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1822008540
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.570996699
Short name T167
Test name
Test status
Simulation time 548854473620 ps
CPU time 339.56 seconds
Started Jul 12 05:04:39 PM PDT 24
Finished Jul 12 05:10:20 PM PDT 24
Peak memory 201832 kb
Host smart-8f1ec9af-83d2-4d80-b228-dc25b2f9a70b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570996699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
570996699
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1704738188
Short name T263
Test name
Test status
Simulation time 337654810467 ps
CPU time 209.06 seconds
Started Jul 12 05:04:48 PM PDT 24
Finished Jul 12 05:08:18 PM PDT 24
Peak memory 201844 kb
Host smart-99099547-da4d-4430-ac9b-d63c1dafa589
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704738188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1704738188
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3429901583
Short name T182
Test name
Test status
Simulation time 545961207214 ps
CPU time 213.61 seconds
Started Jul 12 05:05:26 PM PDT 24
Finished Jul 12 05:09:00 PM PDT 24
Peak memory 201912 kb
Host smart-bbdef522-796c-451d-a943-dd1837390115
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429901583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3429901583
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3556148924
Short name T204
Test name
Test status
Simulation time 118399873089 ps
CPU time 442.12 seconds
Started Jul 12 05:05:54 PM PDT 24
Finished Jul 12 05:13:16 PM PDT 24
Peak memory 202084 kb
Host smart-44e56219-dd62-4c46-a753-9d27c2e667fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556148924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3556148924
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3292329004
Short name T310
Test name
Test status
Simulation time 463551759083 ps
CPU time 934.16 seconds
Started Jul 12 05:05:52 PM PDT 24
Finished Jul 12 05:21:26 PM PDT 24
Peak memory 201764 kb
Host smart-ee010a85-3646-4b81-b235-d8c608096349
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292329004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3292329004
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3347073352
Short name T208
Test name
Test status
Simulation time 123949649465 ps
CPU time 520.28 seconds
Started Jul 12 05:06:07 PM PDT 24
Finished Jul 12 05:14:48 PM PDT 24
Peak memory 202136 kb
Host smart-150cd75b-37ab-41bc-a03d-8ec06ebdd03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347073352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3347073352
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1484520349
Short name T638
Test name
Test status
Simulation time 186952906153 ps
CPU time 267.25 seconds
Started Jul 12 05:06:27 PM PDT 24
Finished Jul 12 05:10:55 PM PDT 24
Peak memory 201816 kb
Host smart-361c8063-8b6d-4f5a-9d69-0efb5099db84
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484520349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1484520349
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2513715977
Short name T333
Test name
Test status
Simulation time 99099911961 ps
CPU time 557 seconds
Started Jul 12 05:07:33 PM PDT 24
Finished Jul 12 05:16:50 PM PDT 24
Peak memory 202284 kb
Host smart-1d6097c4-e3e7-4133-b1e1-8bcb6a041e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513715977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2513715977
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1190737636
Short name T305
Test name
Test status
Simulation time 520694721370 ps
CPU time 320.67 seconds
Started Jul 12 05:08:00 PM PDT 24
Finished Jul 12 05:13:21 PM PDT 24
Peak memory 201904 kb
Host smart-a1c43b55-354e-4544-9b39-993415868bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190737636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1190737636
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.184181276
Short name T206
Test name
Test status
Simulation time 119532808666 ps
CPU time 598.35 seconds
Started Jul 12 05:08:36 PM PDT 24
Finished Jul 12 05:18:34 PM PDT 24
Peak memory 202084 kb
Host smart-e1d4a53d-0a14-4744-9aa8-3f1ad2b5bf9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184181276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
184181276
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.535265781
Short name T265
Test name
Test status
Simulation time 491747364785 ps
CPU time 1065.93 seconds
Started Jul 12 05:04:21 PM PDT 24
Finished Jul 12 05:22:08 PM PDT 24
Peak memory 201892 kb
Host smart-1348f1dd-0e92-4741-8052-cb1319756cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535265781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.535265781
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3326228617
Short name T308
Test name
Test status
Simulation time 565280275583 ps
CPU time 304.98 seconds
Started Jul 12 05:04:27 PM PDT 24
Finished Jul 12 05:09:34 PM PDT 24
Peak memory 201972 kb
Host smart-35289519-7629-4f8e-88ac-ed0290b31f55
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326228617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.3326228617
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1317249355
Short name T126
Test name
Test status
Simulation time 710382311 ps
CPU time 1.96 seconds
Started Jul 12 05:03:27 PM PDT 24
Finished Jul 12 05:03:29 PM PDT 24
Peak memory 201640 kb
Host smart-9e1134d7-0b64-4ec3-b834-08f038c524ab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317249355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1317249355
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3249862358
Short name T912
Test name
Test status
Simulation time 923294575 ps
CPU time 1.76 seconds
Started Jul 12 05:03:25 PM PDT 24
Finished Jul 12 05:03:27 PM PDT 24
Peak memory 201488 kb
Host smart-2921b957-8d99-4af2-aa03-4b38fe1b620c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249862358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3249862358
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.73510589
Short name T876
Test name
Test status
Simulation time 565022802 ps
CPU time 1.6 seconds
Started Jul 12 05:03:28 PM PDT 24
Finished Jul 12 05:03:31 PM PDT 24
Peak memory 201564 kb
Host smart-39f13032-6700-4ad5-987c-49c93fb115a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73510589 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.73510589
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1666908386
Short name T120
Test name
Test status
Simulation time 554326175 ps
CPU time 0.88 seconds
Started Jul 12 05:03:26 PM PDT 24
Finished Jul 12 05:03:27 PM PDT 24
Peak memory 201488 kb
Host smart-01fc545a-b5f7-4408-9cc2-f883ede562a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666908386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1666908386
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2810517137
Short name T882
Test name
Test status
Simulation time 444016392 ps
CPU time 1.82 seconds
Started Jul 12 05:03:29 PM PDT 24
Finished Jul 12 05:03:31 PM PDT 24
Peak memory 201404 kb
Host smart-399ae53d-0ba7-42a6-970e-6443356e171d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810517137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2810517137
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2766634034
Short name T879
Test name
Test status
Simulation time 2406813949 ps
CPU time 7.55 seconds
Started Jul 12 05:03:25 PM PDT 24
Finished Jul 12 05:03:33 PM PDT 24
Peak memory 201612 kb
Host smart-7f4cb555-d792-4ae1-8c02-c987f2f31b1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766634034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2766634034
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1272078416
Short name T890
Test name
Test status
Simulation time 399650059 ps
CPU time 2.65 seconds
Started Jul 12 05:03:28 PM PDT 24
Finished Jul 12 05:03:31 PM PDT 24
Peak memory 201688 kb
Host smart-e0ecd9b4-930b-460a-9eee-6a95d5db6e3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272078416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1272078416
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1043608624
Short name T907
Test name
Test status
Simulation time 10052057140 ps
CPU time 4.23 seconds
Started Jul 12 05:03:27 PM PDT 24
Finished Jul 12 05:03:32 PM PDT 24
Peak memory 201748 kb
Host smart-847c580a-ae79-4d80-95bd-c29fb41b0a09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043608624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1043608624
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4170961172
Short name T847
Test name
Test status
Simulation time 786977581 ps
CPU time 2.04 seconds
Started Jul 12 05:03:38 PM PDT 24
Finished Jul 12 05:03:41 PM PDT 24
Peak memory 201648 kb
Host smart-d2735783-1b3c-4ddd-b0a7-534b1f278c9b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170961172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.4170961172
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1350626577
Short name T125
Test name
Test status
Simulation time 36904964002 ps
CPU time 40.24 seconds
Started Jul 12 05:03:36 PM PDT 24
Finished Jul 12 05:04:17 PM PDT 24
Peak memory 201796 kb
Host smart-8bb183bf-0c3e-4bca-babb-8417a596657b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350626577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.1350626577
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.577860888
Short name T814
Test name
Test status
Simulation time 694547602 ps
CPU time 1.07 seconds
Started Jul 12 05:03:39 PM PDT 24
Finished Jul 12 05:03:42 PM PDT 24
Peak memory 201472 kb
Host smart-dee6f49d-1e4d-4438-85f2-7798a363fc9e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577860888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.577860888
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.365362462
Short name T849
Test name
Test status
Simulation time 547578443 ps
CPU time 1.99 seconds
Started Jul 12 05:03:43 PM PDT 24
Finished Jul 12 05:03:47 PM PDT 24
Peak memory 201460 kb
Host smart-746adfd8-d0aa-48e9-a216-73fd026bc6fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365362462 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.365362462
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2601633598
Short name T121
Test name
Test status
Simulation time 540897390 ps
CPU time 1.36 seconds
Started Jul 12 05:03:37 PM PDT 24
Finished Jul 12 05:03:40 PM PDT 24
Peak memory 201412 kb
Host smart-5fff49e5-a9a3-470d-9fa4-8dde7fa67127
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601633598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2601633598
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.720014434
Short name T803
Test name
Test status
Simulation time 446581177 ps
CPU time 1.76 seconds
Started Jul 12 05:03:47 PM PDT 24
Finished Jul 12 05:03:50 PM PDT 24
Peak memory 201408 kb
Host smart-e696811d-e66d-477d-8477-7625ad66cbfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720014434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.720014434
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2459148150
Short name T50
Test name
Test status
Simulation time 2391239068 ps
CPU time 6.51 seconds
Started Jul 12 05:03:34 PM PDT 24
Finished Jul 12 05:03:41 PM PDT 24
Peak memory 201840 kb
Host smart-ea487de6-9ef0-46be-a66e-a7572d491512
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459148150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2459148150
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.842715597
Short name T326
Test name
Test status
Simulation time 7951423016 ps
CPU time 12.01 seconds
Started Jul 12 05:03:44 PM PDT 24
Finished Jul 12 05:03:58 PM PDT 24
Peak memory 201684 kb
Host smart-9076472f-6487-4a1d-b4ff-c5cebdecda7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842715597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int
g_err.842715597
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3546685495
Short name T92
Test name
Test status
Simulation time 372896369 ps
CPU time 1.32 seconds
Started Jul 12 05:03:41 PM PDT 24
Finished Jul 12 05:03:44 PM PDT 24
Peak memory 201492 kb
Host smart-47a5a0f8-5309-47e0-9e95-34c82ca68272
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546685495 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3546685495
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3231293221
Short name T130
Test name
Test status
Simulation time 359844431 ps
CPU time 1.09 seconds
Started Jul 12 05:03:39 PM PDT 24
Finished Jul 12 05:03:42 PM PDT 24
Peak memory 201324 kb
Host smart-5c0121b8-0340-4daa-a89b-3bf307a44279
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231293221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3231293221
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1288543784
Short name T839
Test name
Test status
Simulation time 349528099 ps
CPU time 1.46 seconds
Started Jul 12 05:03:43 PM PDT 24
Finished Jul 12 05:03:46 PM PDT 24
Peak memory 201400 kb
Host smart-b5c74756-9019-4503-bf28-84f091d6cc82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288543784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1288543784
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.293060938
Short name T850
Test name
Test status
Simulation time 4065358597 ps
CPU time 8.43 seconds
Started Jul 12 05:03:47 PM PDT 24
Finished Jul 12 05:03:57 PM PDT 24
Peak memory 201724 kb
Host smart-a1cb6485-d8a8-4365-8c4c-fd2f901ac7c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293060938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.293060938
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.74772009
Short name T69
Test name
Test status
Simulation time 459600369 ps
CPU time 3.36 seconds
Started Jul 12 05:03:51 PM PDT 24
Finished Jul 12 05:03:56 PM PDT 24
Peak memory 201612 kb
Host smart-e90abb3f-de5f-4635-bed6-9380d1861ead
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74772009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.74772009
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2847636799
Short name T895
Test name
Test status
Simulation time 4587077247 ps
CPU time 7.03 seconds
Started Jul 12 05:03:43 PM PDT 24
Finished Jul 12 05:03:52 PM PDT 24
Peak memory 201736 kb
Host smart-4bee7c2f-2087-44a5-970f-632de9072c6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847636799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.2847636799
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1696617739
Short name T832
Test name
Test status
Simulation time 514215490 ps
CPU time 1.39 seconds
Started Jul 12 05:03:41 PM PDT 24
Finished Jul 12 05:03:43 PM PDT 24
Peak memory 201556 kb
Host smart-d3f8d3c8-4156-45e9-95d5-c85e00044a42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696617739 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1696617739
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3144555384
Short name T131
Test name
Test status
Simulation time 509677814 ps
CPU time 1.14 seconds
Started Jul 12 05:03:42 PM PDT 24
Finished Jul 12 05:03:45 PM PDT 24
Peak memory 201476 kb
Host smart-2cd85860-68a4-4a79-9515-3a8c7ee82548
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144555384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3144555384
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.706800659
Short name T860
Test name
Test status
Simulation time 570492128 ps
CPU time 0.74 seconds
Started Jul 12 05:03:48 PM PDT 24
Finished Jul 12 05:03:50 PM PDT 24
Peak memory 200476 kb
Host smart-31de030d-8f66-4483-b81c-31198cfae52c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706800659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.706800659
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3816029267
Short name T132
Test name
Test status
Simulation time 2623702793 ps
CPU time 5.12 seconds
Started Jul 12 05:03:44 PM PDT 24
Finished Jul 12 05:03:51 PM PDT 24
Peak memory 201808 kb
Host smart-fa233d25-14d0-4825-8d6e-7d7b25994fee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816029267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.3816029267
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.854813260
Short name T844
Test name
Test status
Simulation time 464931383 ps
CPU time 3.01 seconds
Started Jul 12 05:03:52 PM PDT 24
Finished Jul 12 05:03:57 PM PDT 24
Peak memory 201672 kb
Host smart-2882a026-2c09-42d3-9c8c-92b3b4aa6142
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854813260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.854813260
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2645968218
Short name T54
Test name
Test status
Simulation time 4694220830 ps
CPU time 10.72 seconds
Started Jul 12 05:03:43 PM PDT 24
Finished Jul 12 05:03:55 PM PDT 24
Peak memory 201796 kb
Host smart-650df685-4a1d-48a8-b9d1-ad7a16244373
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645968218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2645968218
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2704984956
Short name T852
Test name
Test status
Simulation time 493986092 ps
CPU time 2.12 seconds
Started Jul 12 05:03:44 PM PDT 24
Finished Jul 12 05:03:49 PM PDT 24
Peak memory 201524 kb
Host smart-7f1f6ebd-a83b-42fc-9ff4-be5e962abdc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704984956 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2704984956
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1791525020
Short name T113
Test name
Test status
Simulation time 368590669 ps
CPU time 0.97 seconds
Started Jul 12 05:03:57 PM PDT 24
Finished Jul 12 05:03:59 PM PDT 24
Peak memory 201412 kb
Host smart-6aa695aa-f00e-45f3-9fd9-3553571ece7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791525020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1791525020
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1353982617
Short name T884
Test name
Test status
Simulation time 436858086 ps
CPU time 0.91 seconds
Started Jul 12 05:03:48 PM PDT 24
Finished Jul 12 05:03:51 PM PDT 24
Peak memory 200576 kb
Host smart-c1aaadb2-2735-420d-a400-a4686754d16a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353982617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1353982617
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1469400233
Short name T862
Test name
Test status
Simulation time 2046068733 ps
CPU time 4.33 seconds
Started Jul 12 05:06:57 PM PDT 24
Finished Jul 12 05:07:02 PM PDT 24
Peak memory 201368 kb
Host smart-3ad5bc9d-af50-40ea-9b87-5b85c301d938
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469400233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.1469400233
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3272041958
Short name T820
Test name
Test status
Simulation time 614662961 ps
CPU time 1.73 seconds
Started Jul 12 05:03:45 PM PDT 24
Finished Jul 12 05:03:48 PM PDT 24
Peak memory 201640 kb
Host smart-bf164d77-1da0-43d0-8ec4-b06e75dbe260
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272041958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3272041958
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.753171667
Short name T904
Test name
Test status
Simulation time 7916071552 ps
CPU time 20.71 seconds
Started Jul 12 05:03:47 PM PDT 24
Finished Jul 12 05:04:09 PM PDT 24
Peak memory 201796 kb
Host smart-7d4b3ed4-b98a-46c4-b27a-af94fe2b3845
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753171667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.753171667
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1864466416
Short name T59
Test name
Test status
Simulation time 449626898 ps
CPU time 1.1 seconds
Started Jul 12 05:03:41 PM PDT 24
Finished Jul 12 05:03:44 PM PDT 24
Peak memory 201468 kb
Host smart-62bbc178-bef2-45d6-a232-6448d82a2e3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864466416 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1864466416
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.588069351
Short name T115
Test name
Test status
Simulation time 360501686 ps
CPU time 1.22 seconds
Started Jul 12 05:03:43 PM PDT 24
Finished Jul 12 05:03:47 PM PDT 24
Peak memory 201400 kb
Host smart-8525be38-0e3e-498e-a521-d078da1b0090
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588069351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.588069351
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1989820046
Short name T869
Test name
Test status
Simulation time 350645248 ps
CPU time 1.08 seconds
Started Jul 12 05:03:46 PM PDT 24
Finished Jul 12 05:03:48 PM PDT 24
Peak memory 201300 kb
Host smart-94b5f7af-c6bd-4ab7-b2b4-2ea3c22852bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989820046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1989820046
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1007026329
Short name T913
Test name
Test status
Simulation time 2342755735 ps
CPU time 2.32 seconds
Started Jul 12 05:03:41 PM PDT 24
Finished Jul 12 05:03:45 PM PDT 24
Peak memory 201548 kb
Host smart-70836cab-8dee-44a4-880b-6d548b9dcc6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007026329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1007026329
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.495390234
Short name T911
Test name
Test status
Simulation time 434668021 ps
CPU time 1.06 seconds
Started Jul 12 05:03:44 PM PDT 24
Finished Jul 12 05:03:47 PM PDT 24
Peak memory 201484 kb
Host smart-92f664fe-dea5-4a7e-a1d3-40bcd5c35ff6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495390234 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.495390234
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2628333305
Short name T909
Test name
Test status
Simulation time 604262396 ps
CPU time 0.83 seconds
Started Jul 12 05:03:52 PM PDT 24
Finished Jul 12 05:03:55 PM PDT 24
Peak memory 201336 kb
Host smart-a649f242-c769-45b1-a09b-69f2b19d4730
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628333305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2628333305
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2002180681
Short name T823
Test name
Test status
Simulation time 401028621 ps
CPU time 1.64 seconds
Started Jul 12 05:03:42 PM PDT 24
Finished Jul 12 05:03:45 PM PDT 24
Peak memory 201348 kb
Host smart-ecc74643-7b0b-4995-9962-66d193577d85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002180681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2002180681
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3280426614
Short name T829
Test name
Test status
Simulation time 2849936222 ps
CPU time 1.86 seconds
Started Jul 12 05:03:43 PM PDT 24
Finished Jul 12 05:03:48 PM PDT 24
Peak memory 201524 kb
Host smart-d7ff48fc-1858-4a07-b065-3dac5ea52c79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280426614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.3280426614
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3614922456
Short name T889
Test name
Test status
Simulation time 550746455 ps
CPU time 3.01 seconds
Started Jul 12 05:03:43 PM PDT 24
Finished Jul 12 05:03:49 PM PDT 24
Peak memory 211048 kb
Host smart-43d9f03d-8229-4f96-b30c-460c6ed9ce6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614922456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3614922456
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1437115222
Short name T60
Test name
Test status
Simulation time 4500499799 ps
CPU time 4.1 seconds
Started Jul 12 05:03:48 PM PDT 24
Finished Jul 12 05:03:54 PM PDT 24
Peak memory 201736 kb
Host smart-56497b87-fdaf-47ec-97a8-9acd7bcc1553
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437115222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1437115222
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3528369634
Short name T819
Test name
Test status
Simulation time 488035838 ps
CPU time 2.11 seconds
Started Jul 12 05:03:42 PM PDT 24
Finished Jul 12 05:03:45 PM PDT 24
Peak memory 201560 kb
Host smart-3ffeb84e-3a09-4162-9946-35eb05f36c12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528369634 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3528369634
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1265909391
Short name T124
Test name
Test status
Simulation time 547127325 ps
CPU time 1.5 seconds
Started Jul 12 05:03:57 PM PDT 24
Finished Jul 12 05:03:59 PM PDT 24
Peak memory 201416 kb
Host smart-6484d1c5-2bea-4a73-9584-1c41a12036a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265909391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1265909391
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1992846797
Short name T835
Test name
Test status
Simulation time 419025830 ps
CPU time 1.45 seconds
Started Jul 12 05:03:40 PM PDT 24
Finished Jul 12 05:03:43 PM PDT 24
Peak memory 201284 kb
Host smart-832247cc-4739-417f-a03a-a5d5985bbae1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992846797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1992846797
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1063181702
Short name T833
Test name
Test status
Simulation time 2566292022 ps
CPU time 3.38 seconds
Started Jul 12 05:03:57 PM PDT 24
Finished Jul 12 05:04:01 PM PDT 24
Peak memory 201536 kb
Host smart-38892e66-e724-4fbd-8ada-cda567e4de14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063181702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1063181702
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.134086896
Short name T905
Test name
Test status
Simulation time 462171110 ps
CPU time 2.27 seconds
Started Jul 12 05:03:57 PM PDT 24
Finished Jul 12 05:03:59 PM PDT 24
Peak memory 201692 kb
Host smart-9b1d7303-cee1-4e07-bbc4-9e897681f311
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134086896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.134086896
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1212296812
Short name T854
Test name
Test status
Simulation time 4669080096 ps
CPU time 2.31 seconds
Started Jul 12 05:03:47 PM PDT 24
Finished Jul 12 05:03:51 PM PDT 24
Peak memory 201756 kb
Host smart-2960ad49-5b3f-49c3-826a-4a454c8ac622
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212296812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.1212296812
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3693602905
Short name T822
Test name
Test status
Simulation time 476413624 ps
CPU time 1.22 seconds
Started Jul 12 05:03:53 PM PDT 24
Finished Jul 12 05:03:55 PM PDT 24
Peak memory 201492 kb
Host smart-4a232768-4fb3-4dc7-8cd6-d7cecee731d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693602905 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3693602905
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.339840113
Short name T119
Test name
Test status
Simulation time 325835144 ps
CPU time 1.05 seconds
Started Jul 12 05:03:49 PM PDT 24
Finished Jul 12 05:03:51 PM PDT 24
Peak memory 201424 kb
Host smart-1a239234-23e0-495f-8da8-58d51be5d920
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339840113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.339840113
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3993813952
Short name T812
Test name
Test status
Simulation time 479830181 ps
CPU time 0.77 seconds
Started Jul 12 05:03:57 PM PDT 24
Finished Jul 12 05:03:58 PM PDT 24
Peak memory 201336 kb
Host smart-3574dd55-bac8-4313-90f4-a4bb953eaff7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993813952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3993813952
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3484794638
Short name T897
Test name
Test status
Simulation time 4005506622 ps
CPU time 5.32 seconds
Started Jul 12 05:03:50 PM PDT 24
Finished Jul 12 05:03:56 PM PDT 24
Peak memory 201860 kb
Host smart-ae5ab3e1-667b-44c8-bc09-ee363d07dadb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484794638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.3484794638
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.566977453
Short name T894
Test name
Test status
Simulation time 838967473 ps
CPU time 1.56 seconds
Started Jul 12 05:03:47 PM PDT 24
Finished Jul 12 05:03:49 PM PDT 24
Peak memory 201728 kb
Host smart-2aa47553-1520-427e-b246-bc681adf4d85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566977453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.566977453
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2443337843
Short name T56
Test name
Test status
Simulation time 3950937888 ps
CPU time 11.67 seconds
Started Jul 12 05:03:44 PM PDT 24
Finished Jul 12 05:03:58 PM PDT 24
Peak memory 201840 kb
Host smart-83ba0714-af4e-4973-a61d-b1fd2802407a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443337843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2443337843
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.308901005
Short name T845
Test name
Test status
Simulation time 542672473 ps
CPU time 2.2 seconds
Started Jul 12 05:03:48 PM PDT 24
Finished Jul 12 05:03:52 PM PDT 24
Peak memory 201536 kb
Host smart-0d55f140-2a68-411d-87a9-c753bb5795ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308901005 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.308901005
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.707054315
Short name T129
Test name
Test status
Simulation time 385314171 ps
CPU time 0.77 seconds
Started Jul 12 05:03:54 PM PDT 24
Finished Jul 12 05:03:56 PM PDT 24
Peak memory 201432 kb
Host smart-62bb0a70-4238-46ab-9bfa-d4e40096d65a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707054315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.707054315
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4211912674
Short name T831
Test name
Test status
Simulation time 443423053 ps
CPU time 0.83 seconds
Started Jul 12 05:03:58 PM PDT 24
Finished Jul 12 05:04:01 PM PDT 24
Peak memory 201404 kb
Host smart-03d219eb-4ee0-4a87-8c90-710933e73f30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211912674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.4211912674
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1904956593
Short name T893
Test name
Test status
Simulation time 4748717984 ps
CPU time 9.83 seconds
Started Jul 12 05:03:51 PM PDT 24
Finished Jul 12 05:04:03 PM PDT 24
Peak memory 201816 kb
Host smart-9bee112f-27ae-469e-ab1d-3288df3e2b7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904956593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1904956593
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3974326817
Short name T891
Test name
Test status
Simulation time 690207964 ps
CPU time 2.17 seconds
Started Jul 12 05:03:59 PM PDT 24
Finished Jul 12 05:04:04 PM PDT 24
Peak memory 201728 kb
Host smart-383681eb-869b-481d-9ef8-80def079785d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974326817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3974326817
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1551141704
Short name T908
Test name
Test status
Simulation time 10241332348 ps
CPU time 4.65 seconds
Started Jul 12 05:03:50 PM PDT 24
Finished Jul 12 05:03:56 PM PDT 24
Peak memory 201836 kb
Host smart-2775a4e9-8f32-48ce-ba21-928db520525d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551141704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1551141704
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.601709021
Short name T838
Test name
Test status
Simulation time 371105528 ps
CPU time 1.65 seconds
Started Jul 12 05:03:49 PM PDT 24
Finished Jul 12 05:03:52 PM PDT 24
Peak memory 201428 kb
Host smart-3344a2df-a9ad-4e52-82ef-f87fe538297a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601709021 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.601709021
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1329520002
Short name T858
Test name
Test status
Simulation time 507487660 ps
CPU time 1 seconds
Started Jul 12 05:03:49 PM PDT 24
Finished Jul 12 05:03:51 PM PDT 24
Peak memory 201388 kb
Host smart-64959308-bc6b-4bac-8c27-fdb20d53a713
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329520002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1329520002
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3479373330
Short name T802
Test name
Test status
Simulation time 343963029 ps
CPU time 1.11 seconds
Started Jul 12 05:03:51 PM PDT 24
Finished Jul 12 05:03:54 PM PDT 24
Peak memory 201404 kb
Host smart-ac5723df-e370-43ad-858d-162ed21f9b4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479373330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3479373330
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.727547189
Short name T896
Test name
Test status
Simulation time 2721013319 ps
CPU time 6.67 seconds
Started Jul 12 05:03:53 PM PDT 24
Finished Jul 12 05:04:01 PM PDT 24
Peak memory 201796 kb
Host smart-62a85025-ad22-43f7-ab46-0697f272c3d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727547189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_same_csr_outstanding.727547189
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2671406517
Short name T830
Test name
Test status
Simulation time 463784392 ps
CPU time 2.95 seconds
Started Jul 12 05:03:49 PM PDT 24
Finished Jul 12 05:03:54 PM PDT 24
Peak memory 217612 kb
Host smart-9c4d5923-0859-407e-b71f-169a6dd8ef36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671406517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.2671406517
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1151683873
Short name T73
Test name
Test status
Simulation time 8124465934 ps
CPU time 9.15 seconds
Started Jul 12 05:03:53 PM PDT 24
Finished Jul 12 05:04:03 PM PDT 24
Peak memory 201776 kb
Host smart-325bb59e-4e4a-46cd-894c-fb4a928dd23d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151683873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1151683873
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3053620183
Short name T70
Test name
Test status
Simulation time 574530688 ps
CPU time 2.1 seconds
Started Jul 12 05:03:52 PM PDT 24
Finished Jul 12 05:03:56 PM PDT 24
Peak memory 201536 kb
Host smart-a8baad56-7fb1-4690-8a0d-6e28c3cb7225
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053620183 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3053620183
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2486678667
Short name T805
Test name
Test status
Simulation time 325313840 ps
CPU time 1.4 seconds
Started Jul 12 05:03:51 PM PDT 24
Finished Jul 12 05:03:53 PM PDT 24
Peak memory 201344 kb
Host smart-ad1c7801-a919-47bd-97de-d2099ac2b3cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486678667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2486678667
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.4218649609
Short name T906
Test name
Test status
Simulation time 3942577316 ps
CPU time 6.58 seconds
Started Jul 12 05:03:54 PM PDT 24
Finished Jul 12 05:04:02 PM PDT 24
Peak memory 201992 kb
Host smart-778719ef-0ae2-461c-9472-ab63b60ed801
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218649609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.4218649609
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1235090832
Short name T868
Test name
Test status
Simulation time 402767995 ps
CPU time 3.42 seconds
Started Jul 12 05:03:48 PM PDT 24
Finished Jul 12 05:03:53 PM PDT 24
Peak memory 201620 kb
Host smart-d6d561a8-5773-44bf-aeea-4576d8be4808
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235090832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1235090832
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.999158363
Short name T843
Test name
Test status
Simulation time 8490702524 ps
CPU time 12.5 seconds
Started Jul 12 05:03:53 PM PDT 24
Finished Jul 12 05:04:07 PM PDT 24
Peak memory 201824 kb
Host smart-2b0ae788-7f6b-4e77-8f5b-41b2aee35054
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999158363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.999158363
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2765727431
Short name T128
Test name
Test status
Simulation time 1018399115 ps
CPU time 3.04 seconds
Started Jul 12 05:03:36 PM PDT 24
Finished Jul 12 05:03:40 PM PDT 24
Peak memory 201692 kb
Host smart-445cf83c-b1b6-4c82-a56b-482be8694930
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765727431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2765727431
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2098752140
Short name T133
Test name
Test status
Simulation time 51776885592 ps
CPU time 111.5 seconds
Started Jul 12 05:03:37 PM PDT 24
Finished Jul 12 05:05:30 PM PDT 24
Peak memory 201768 kb
Host smart-bf64c798-a4f4-4400-b93d-4511d9a6da57
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098752140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2098752140
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.4011717602
Short name T114
Test name
Test status
Simulation time 1244885413 ps
CPU time 1.53 seconds
Started Jul 12 05:03:39 PM PDT 24
Finished Jul 12 05:03:42 PM PDT 24
Peak memory 201472 kb
Host smart-048372da-5956-4423-94eb-9004fdb6844d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011717602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.4011717602
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2375140489
Short name T863
Test name
Test status
Simulation time 499583257 ps
CPU time 1.92 seconds
Started Jul 12 05:03:38 PM PDT 24
Finished Jul 12 05:03:41 PM PDT 24
Peak memory 201548 kb
Host smart-7b25bcdd-85f2-4969-b904-01c5b68cedae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375140489 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2375140489
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2015766515
Short name T118
Test name
Test status
Simulation time 539190242 ps
CPU time 1.07 seconds
Started Jul 12 05:03:36 PM PDT 24
Finished Jul 12 05:03:38 PM PDT 24
Peak memory 201424 kb
Host smart-606f3ce2-08b8-4b12-944a-db5cc90d9797
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015766515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2015766515
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3295770393
Short name T861
Test name
Test status
Simulation time 296097053 ps
CPU time 1.07 seconds
Started Jul 12 05:03:35 PM PDT 24
Finished Jul 12 05:03:37 PM PDT 24
Peak memory 201424 kb
Host smart-fccf27d8-a648-46d4-bd35-b342de6d8434
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295770393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3295770393
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1854425321
Short name T52
Test name
Test status
Simulation time 2262992609 ps
CPU time 4.3 seconds
Started Jul 12 05:03:37 PM PDT 24
Finished Jul 12 05:03:43 PM PDT 24
Peak memory 201548 kb
Host smart-8892b2ce-30d5-4657-b702-e71a0cff2e4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854425321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1854425321
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3609877732
Short name T71
Test name
Test status
Simulation time 428348718 ps
CPU time 3.26 seconds
Started Jul 12 05:03:43 PM PDT 24
Finished Jul 12 05:03:49 PM PDT 24
Peak memory 209880 kb
Host smart-c8229fdf-e26c-48e4-9a04-21fa532759db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609877732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3609877732
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2692092640
Short name T83
Test name
Test status
Simulation time 4670312300 ps
CPU time 4.54 seconds
Started Jul 12 05:03:34 PM PDT 24
Finished Jul 12 05:03:40 PM PDT 24
Peak memory 201784 kb
Host smart-3e9acbd9-be9a-4fc6-bb83-ab4ab53527fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692092640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2692092640
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.4243085599
Short name T816
Test name
Test status
Simulation time 398075827 ps
CPU time 0.76 seconds
Started Jul 12 05:03:52 PM PDT 24
Finished Jul 12 05:03:55 PM PDT 24
Peak memory 201396 kb
Host smart-2a85a26e-668d-4cdf-a6a0-1ce33115c0b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243085599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.4243085599
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1510842057
Short name T815
Test name
Test status
Simulation time 454127470 ps
CPU time 0.75 seconds
Started Jul 12 05:03:50 PM PDT 24
Finished Jul 12 05:03:52 PM PDT 24
Peak memory 201408 kb
Host smart-95186f88-b0f5-4d8a-a48c-d77435840d29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510842057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1510842057
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.4068738472
Short name T806
Test name
Test status
Simulation time 529935315 ps
CPU time 0.79 seconds
Started Jul 12 05:03:52 PM PDT 24
Finished Jul 12 05:03:54 PM PDT 24
Peak memory 201520 kb
Host smart-347d45af-d01e-459b-a0d4-fa1ce4575f44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068738472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.4068738472
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.540897483
Short name T809
Test name
Test status
Simulation time 331091350 ps
CPU time 0.8 seconds
Started Jul 12 05:03:59 PM PDT 24
Finished Jul 12 05:04:02 PM PDT 24
Peak memory 201404 kb
Host smart-1b0d9cfa-b6cd-4117-bbdc-abdfeb0a8131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540897483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.540897483
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.4052824163
Short name T875
Test name
Test status
Simulation time 374640474 ps
CPU time 1.13 seconds
Started Jul 12 05:03:52 PM PDT 24
Finished Jul 12 05:03:55 PM PDT 24
Peak memory 201396 kb
Host smart-75d07ca5-aa10-417f-bdb4-4119bbfdfdf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052824163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.4052824163
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3583211753
Short name T887
Test name
Test status
Simulation time 435775668 ps
CPU time 0.83 seconds
Started Jul 12 05:03:57 PM PDT 24
Finished Jul 12 05:03:59 PM PDT 24
Peak memory 201336 kb
Host smart-eec34c5a-0cf6-40bd-a5da-d7b1cee4cb07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583211753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3583211753
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.805080139
Short name T804
Test name
Test status
Simulation time 313808469 ps
CPU time 1.31 seconds
Started Jul 12 05:03:52 PM PDT 24
Finished Jul 12 05:03:55 PM PDT 24
Peak memory 201332 kb
Host smart-811dc729-35cb-4319-9ade-820a1e4d5531
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805080139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.805080139
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.107775209
Short name T867
Test name
Test status
Simulation time 426738823 ps
CPU time 0.69 seconds
Started Jul 12 05:03:48 PM PDT 24
Finished Jul 12 05:03:50 PM PDT 24
Peak memory 201388 kb
Host smart-a4894edd-49fc-45b6-b5df-4b096a1e2576
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107775209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.107775209
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3130722107
Short name T857
Test name
Test status
Simulation time 493073918 ps
CPU time 1.78 seconds
Started Jul 12 05:03:55 PM PDT 24
Finished Jul 12 05:03:57 PM PDT 24
Peak memory 201408 kb
Host smart-ec5535c1-2930-4ed5-8486-b1cad6ef2dba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130722107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3130722107
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1107169950
Short name T870
Test name
Test status
Simulation time 478770283 ps
CPU time 1.18 seconds
Started Jul 12 05:03:49 PM PDT 24
Finished Jul 12 05:03:52 PM PDT 24
Peak memory 201400 kb
Host smart-68476c7c-8ddd-4424-a9ff-5d8c99de3c42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107169950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1107169950
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1422879946
Short name T117
Test name
Test status
Simulation time 791846596 ps
CPU time 2.3 seconds
Started Jul 12 05:03:37 PM PDT 24
Finished Jul 12 05:03:41 PM PDT 24
Peak memory 201620 kb
Host smart-5e506aa9-b6d2-4719-8ebc-e5cc8d1b1142
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422879946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.1422879946
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.531603307
Short name T902
Test name
Test status
Simulation time 53207827334 ps
CPU time 68.34 seconds
Started Jul 12 05:03:36 PM PDT 24
Finished Jul 12 05:04:45 PM PDT 24
Peak memory 201808 kb
Host smart-c9d663cf-cf29-472c-bf82-36892682ca98
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531603307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_b
ash.531603307
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.559361488
Short name T123
Test name
Test status
Simulation time 797375503 ps
CPU time 1.74 seconds
Started Jul 12 05:03:44 PM PDT 24
Finished Jul 12 05:03:48 PM PDT 24
Peak memory 201688 kb
Host smart-a90d832c-bada-42c4-9c9f-820f74a6697e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559361488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.559361488
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.151161500
Short name T111
Test name
Test status
Simulation time 841917671 ps
CPU time 1.17 seconds
Started Jul 12 05:03:38 PM PDT 24
Finished Jul 12 05:03:41 PM PDT 24
Peak memory 201472 kb
Host smart-2b52b20c-e3ff-4558-83af-19290074e538
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151161500 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.151161500
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1768579428
Short name T901
Test name
Test status
Simulation time 514196817 ps
CPU time 2.09 seconds
Started Jul 12 05:03:44 PM PDT 24
Finished Jul 12 05:03:48 PM PDT 24
Peak memory 201400 kb
Host smart-7d6e2f28-9f8a-4680-bcab-702fad3f6eb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768579428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1768579428
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2146890216
Short name T807
Test name
Test status
Simulation time 303553713 ps
CPU time 1.3 seconds
Started Jul 12 05:03:35 PM PDT 24
Finished Jul 12 05:03:37 PM PDT 24
Peak memory 201360 kb
Host smart-36202015-c844-4c1d-869a-7747ad832dfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146890216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2146890216
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3501824004
Short name T898
Test name
Test status
Simulation time 2418692273 ps
CPU time 5.52 seconds
Started Jul 12 05:03:37 PM PDT 24
Finished Jul 12 05:03:44 PM PDT 24
Peak memory 201584 kb
Host smart-3fe22e54-4494-4044-846b-672652011eec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501824004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3501824004
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.4275445202
Short name T883
Test name
Test status
Simulation time 543142213 ps
CPU time 3.06 seconds
Started Jul 12 05:03:36 PM PDT 24
Finished Jul 12 05:03:39 PM PDT 24
Peak memory 218160 kb
Host smart-bc4efe74-127a-4175-8018-a6c83f84900c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275445202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.4275445202
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2055334122
Short name T818
Test name
Test status
Simulation time 326043527 ps
CPU time 1.44 seconds
Started Jul 12 05:03:53 PM PDT 24
Finished Jul 12 05:03:56 PM PDT 24
Peak memory 201308 kb
Host smart-d64242da-30c9-46ff-87f8-f8abc4a55687
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055334122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2055334122
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3845188001
Short name T801
Test name
Test status
Simulation time 297531043 ps
CPU time 1.44 seconds
Started Jul 12 05:03:50 PM PDT 24
Finished Jul 12 05:03:53 PM PDT 24
Peak memory 201392 kb
Host smart-1805536e-cde0-4cda-9bda-4bfb4be5438d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845188001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3845188001
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1815969744
Short name T836
Test name
Test status
Simulation time 548830204 ps
CPU time 0.72 seconds
Started Jul 12 05:03:57 PM PDT 24
Finished Jul 12 05:04:00 PM PDT 24
Peak memory 201400 kb
Host smart-c43106f7-b9ce-4609-9ab7-67cd255e81b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815969744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1815969744
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2156911145
Short name T840
Test name
Test status
Simulation time 451319890 ps
CPU time 0.88 seconds
Started Jul 12 05:03:57 PM PDT 24
Finished Jul 12 05:04:00 PM PDT 24
Peak memory 201404 kb
Host smart-bf8de095-857e-4fee-9c53-76a14975a021
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156911145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2156911145
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2213058350
Short name T810
Test name
Test status
Simulation time 531215205 ps
CPU time 0.85 seconds
Started Jul 12 05:03:59 PM PDT 24
Finished Jul 12 05:04:02 PM PDT 24
Peak memory 201404 kb
Host smart-f31ad36c-4d09-4411-ae21-ea6633b41b33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213058350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2213058350
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.867373665
Short name T865
Test name
Test status
Simulation time 532257243 ps
CPU time 1.95 seconds
Started Jul 12 05:03:58 PM PDT 24
Finished Jul 12 05:04:01 PM PDT 24
Peak memory 201404 kb
Host smart-cf153404-5950-4067-94da-6f88d328427e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867373665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.867373665
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.927262570
Short name T877
Test name
Test status
Simulation time 664549268 ps
CPU time 0.75 seconds
Started Jul 12 05:03:59 PM PDT 24
Finished Jul 12 05:04:03 PM PDT 24
Peak memory 201404 kb
Host smart-f2846180-f08c-4f1f-9b80-f5fcae455a66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927262570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.927262570
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2767190182
Short name T813
Test name
Test status
Simulation time 540762109 ps
CPU time 0.85 seconds
Started Jul 12 05:03:58 PM PDT 24
Finished Jul 12 05:04:02 PM PDT 24
Peak memory 201400 kb
Host smart-5e3eaa33-bb94-40f7-b3c5-5bab4d128a8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767190182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2767190182
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3201657997
Short name T878
Test name
Test status
Simulation time 501571278 ps
CPU time 1.76 seconds
Started Jul 12 05:03:54 PM PDT 24
Finished Jul 12 05:03:57 PM PDT 24
Peak memory 201320 kb
Host smart-09ccb772-f557-4f5b-8d86-4b1df2d57a1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201657997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3201657997
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1870992355
Short name T811
Test name
Test status
Simulation time 289585338 ps
CPU time 1.41 seconds
Started Jul 12 05:03:58 PM PDT 24
Finished Jul 12 05:04:03 PM PDT 24
Peak memory 201400 kb
Host smart-5dd06f9b-3dc8-4820-9e7c-914e6d53085f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870992355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1870992355
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1055353589
Short name T127
Test name
Test status
Simulation time 1113683212 ps
CPU time 3.57 seconds
Started Jul 12 05:03:34 PM PDT 24
Finished Jul 12 05:03:38 PM PDT 24
Peak memory 201552 kb
Host smart-31940185-c7ae-4abe-b39e-5cdfe9c45a86
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055353589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1055353589
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1641816416
Short name T122
Test name
Test status
Simulation time 53361971073 ps
CPU time 29.94 seconds
Started Jul 12 05:03:39 PM PDT 24
Finished Jul 12 05:04:10 PM PDT 24
Peak memory 201772 kb
Host smart-c495db66-514e-48b0-893f-8d2ed0e04e3b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641816416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1641816416
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.52428573
Short name T885
Test name
Test status
Simulation time 1181932956 ps
CPU time 3.29 seconds
Started Jul 12 05:03:40 PM PDT 24
Finished Jul 12 05:03:44 PM PDT 24
Peak memory 201588 kb
Host smart-2b7c3dea-bef6-4a26-a77a-ac1ca7bad55c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52428573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_res
et.52428573
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3519484077
Short name T821
Test name
Test status
Simulation time 433048020 ps
CPU time 1.83 seconds
Started Jul 12 05:03:44 PM PDT 24
Finished Jul 12 05:03:48 PM PDT 24
Peak memory 201460 kb
Host smart-9ee01a37-0072-4943-98cc-828732de7909
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519484077 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3519484077
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.283389650
Short name T859
Test name
Test status
Simulation time 538865176 ps
CPU time 2.02 seconds
Started Jul 12 05:03:35 PM PDT 24
Finished Jul 12 05:03:37 PM PDT 24
Peak memory 201424 kb
Host smart-9e8d2cc9-1b37-4601-9524-d3a7e692a2d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283389650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.283389650
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1441007084
Short name T866
Test name
Test status
Simulation time 503901655 ps
CPU time 1.03 seconds
Started Jul 12 05:03:38 PM PDT 24
Finished Jul 12 05:03:40 PM PDT 24
Peak memory 201356 kb
Host smart-9c45650f-be6a-48b1-893a-3831d225d6b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441007084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1441007084
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.4028146937
Short name T916
Test name
Test status
Simulation time 5122658580 ps
CPU time 12.09 seconds
Started Jul 12 05:03:33 PM PDT 24
Finished Jul 12 05:03:45 PM PDT 24
Peak memory 201816 kb
Host smart-3999c256-1e18-4cae-945b-74072f2cba43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028146937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.4028146937
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2986991995
Short name T855
Test name
Test status
Simulation time 404396584 ps
CPU time 2.6 seconds
Started Jul 12 05:03:38 PM PDT 24
Finished Jul 12 05:03:42 PM PDT 24
Peak memory 209960 kb
Host smart-0d48c01a-2fd7-4f6c-9eed-ec76e942067d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986991995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2986991995
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2283209662
Short name T324
Test name
Test status
Simulation time 4702233724 ps
CPU time 4.44 seconds
Started Jul 12 05:03:40 PM PDT 24
Finished Jul 12 05:03:46 PM PDT 24
Peak memory 201892 kb
Host smart-1edc0e70-0244-4cd7-a267-f171ca432cec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283209662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2283209662
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2216221552
Short name T848
Test name
Test status
Simulation time 469814543 ps
CPU time 0.72 seconds
Started Jul 12 05:03:51 PM PDT 24
Finished Jul 12 05:03:53 PM PDT 24
Peak memory 201348 kb
Host smart-5b6162a5-43b9-402b-8123-3da554bcea3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216221552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2216221552
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2544989289
Short name T825
Test name
Test status
Simulation time 374643389 ps
CPU time 1.49 seconds
Started Jul 12 05:03:52 PM PDT 24
Finished Jul 12 05:03:55 PM PDT 24
Peak memory 201304 kb
Host smart-54747c58-ba8e-403d-b138-da579739acd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544989289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2544989289
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1002719490
Short name T842
Test name
Test status
Simulation time 480745042 ps
CPU time 0.91 seconds
Started Jul 12 05:03:51 PM PDT 24
Finished Jul 12 05:03:53 PM PDT 24
Peak memory 201400 kb
Host smart-75786cd8-5f27-4d2c-b97b-778576b63b6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002719490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1002719490
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2153537207
Short name T824
Test name
Test status
Simulation time 298658687 ps
CPU time 1.39 seconds
Started Jul 12 05:03:59 PM PDT 24
Finished Jul 12 05:04:03 PM PDT 24
Peak memory 201404 kb
Host smart-3710cf65-4df9-46e3-b0c5-47fb7e0fb5fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153537207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2153537207
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1372805954
Short name T808
Test name
Test status
Simulation time 329576247 ps
CPU time 1.35 seconds
Started Jul 12 05:03:53 PM PDT 24
Finished Jul 12 05:03:56 PM PDT 24
Peak memory 201400 kb
Host smart-0fa80c5a-6c74-4fa9-b365-b1568e38c2c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372805954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1372805954
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.625714826
Short name T900
Test name
Test status
Simulation time 350279249 ps
CPU time 1.46 seconds
Started Jul 12 05:04:00 PM PDT 24
Finished Jul 12 05:04:05 PM PDT 24
Peak memory 201376 kb
Host smart-d3b1379e-dad3-444b-b234-87475156095b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625714826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.625714826
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.196979512
Short name T871
Test name
Test status
Simulation time 344161168 ps
CPU time 1.46 seconds
Started Jul 12 05:03:59 PM PDT 24
Finished Jul 12 05:04:03 PM PDT 24
Peak memory 201276 kb
Host smart-23ed38bf-cc7e-4113-84e0-cb691bba7870
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196979512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.196979512
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1952713160
Short name T846
Test name
Test status
Simulation time 411124495 ps
CPU time 1.59 seconds
Started Jul 12 05:03:59 PM PDT 24
Finished Jul 12 05:04:03 PM PDT 24
Peak memory 201424 kb
Host smart-ac24f8af-a3ad-4b3d-b37f-0e4fd34bbc4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952713160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1952713160
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2431403736
Short name T828
Test name
Test status
Simulation time 575811173 ps
CPU time 0.87 seconds
Started Jul 12 05:03:57 PM PDT 24
Finished Jul 12 05:03:59 PM PDT 24
Peak memory 201320 kb
Host smart-e7752ded-1d0f-47b7-a44c-bf78321901d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431403736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2431403736
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3387989468
Short name T881
Test name
Test status
Simulation time 472985605 ps
CPU time 1.72 seconds
Started Jul 12 05:04:09 PM PDT 24
Finished Jul 12 05:04:12 PM PDT 24
Peak memory 201408 kb
Host smart-570516bb-68c4-4c70-a2a6-31e10d20a695
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387989468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3387989468
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1437738692
Short name T864
Test name
Test status
Simulation time 571770268 ps
CPU time 2.24 seconds
Started Jul 12 05:03:38 PM PDT 24
Finished Jul 12 05:03:41 PM PDT 24
Peak memory 201564 kb
Host smart-01072049-b37c-4b66-80d6-7ebc0a283dbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437738692 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1437738692
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.965064367
Short name T903
Test name
Test status
Simulation time 642051419 ps
CPU time 0.95 seconds
Started Jul 12 05:03:35 PM PDT 24
Finished Jul 12 05:03:37 PM PDT 24
Peak memory 201476 kb
Host smart-4e643604-ca00-45d7-8848-8566f18c1c66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965064367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.965064367
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.658287226
Short name T873
Test name
Test status
Simulation time 529225243 ps
CPU time 1.79 seconds
Started Jul 12 05:03:34 PM PDT 24
Finished Jul 12 05:03:37 PM PDT 24
Peak memory 201380 kb
Host smart-99b7bdf7-66f3-418d-8752-c7cc6c01ac9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658287226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.658287226
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3020586748
Short name T880
Test name
Test status
Simulation time 4596127761 ps
CPU time 6.87 seconds
Started Jul 12 05:03:42 PM PDT 24
Finished Jul 12 05:03:50 PM PDT 24
Peak memory 201836 kb
Host smart-02fa13f6-11a7-46f6-be43-f0dc14927068
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020586748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3020586748
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.300625634
Short name T65
Test name
Test status
Simulation time 480656817 ps
CPU time 2.54 seconds
Started Jul 12 05:03:43 PM PDT 24
Finished Jul 12 05:03:48 PM PDT 24
Peak memory 201632 kb
Host smart-992cf8ef-8bcf-4d54-8604-d1a9e9e0e978
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300625634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.300625634
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.258347193
Short name T325
Test name
Test status
Simulation time 4231876644 ps
CPU time 3.11 seconds
Started Jul 12 05:03:35 PM PDT 24
Finished Jul 12 05:03:39 PM PDT 24
Peak memory 201804 kb
Host smart-f33cecfc-1aef-445b-a784-9a3f5ebc8cd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258347193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.258347193
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2923962483
Short name T853
Test name
Test status
Simulation time 617567919 ps
CPU time 1.59 seconds
Started Jul 12 05:03:33 PM PDT 24
Finished Jul 12 05:03:35 PM PDT 24
Peak memory 201740 kb
Host smart-73541b4d-b7cb-4c63-ae60-1e281140098f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923962483 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2923962483
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.300922369
Short name T874
Test name
Test status
Simulation time 493135612 ps
CPU time 1.27 seconds
Started Jul 12 05:03:36 PM PDT 24
Finished Jul 12 05:03:38 PM PDT 24
Peak memory 201424 kb
Host smart-63b59ca4-daac-4105-8d12-d927c60b263e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300922369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.300922369
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.463248621
Short name T851
Test name
Test status
Simulation time 407469777 ps
CPU time 1.56 seconds
Started Jul 12 05:03:40 PM PDT 24
Finished Jul 12 05:03:43 PM PDT 24
Peak memory 201396 kb
Host smart-ef398d98-5aa1-4fad-acd1-19ab9edad9fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463248621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.463248621
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2926771942
Short name T856
Test name
Test status
Simulation time 4865179984 ps
CPU time 3.84 seconds
Started Jul 12 05:03:36 PM PDT 24
Finished Jul 12 05:03:40 PM PDT 24
Peak memory 201828 kb
Host smart-f66a75f6-0c2e-4aee-8f3a-0b4e9c8e3d96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926771942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2926771942
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.847032435
Short name T841
Test name
Test status
Simulation time 371388998 ps
CPU time 1.64 seconds
Started Jul 12 05:03:44 PM PDT 24
Finished Jul 12 05:03:48 PM PDT 24
Peak memory 201940 kb
Host smart-c487d4dc-619a-44d2-87ac-81e918fd1bfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847032435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.847032435
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.4274707013
Short name T910
Test name
Test status
Simulation time 4882488029 ps
CPU time 2.96 seconds
Started Jul 12 05:03:34 PM PDT 24
Finished Jul 12 05:03:37 PM PDT 24
Peak memory 201836 kb
Host smart-04072428-5256-482a-aac5-4cb38aafd4f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274707013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.4274707013
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3261507215
Short name T66
Test name
Test status
Simulation time 534582460 ps
CPU time 1.72 seconds
Started Jul 12 05:03:35 PM PDT 24
Finished Jul 12 05:03:37 PM PDT 24
Peak memory 201516 kb
Host smart-8816d479-6713-46f3-8785-0e16b906324c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261507215 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3261507215
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1062072340
Short name T892
Test name
Test status
Simulation time 447066147 ps
CPU time 1.37 seconds
Started Jul 12 05:03:44 PM PDT 24
Finished Jul 12 05:03:47 PM PDT 24
Peak memory 201400 kb
Host smart-ee23fa22-10f6-48e0-8d75-de38e6275594
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062072340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1062072340
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1310164422
Short name T918
Test name
Test status
Simulation time 530769199 ps
CPU time 0.92 seconds
Started Jul 12 05:03:37 PM PDT 24
Finished Jul 12 05:03:39 PM PDT 24
Peak memory 201432 kb
Host smart-7de37bd4-4900-4305-bfa9-fde2d0cbc72f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310164422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1310164422
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2770326057
Short name T888
Test name
Test status
Simulation time 2913710881 ps
CPU time 11.06 seconds
Started Jul 12 05:03:35 PM PDT 24
Finished Jul 12 05:03:47 PM PDT 24
Peak memory 201784 kb
Host smart-4b0bfbe4-495e-478b-9bf6-9768cd207d89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770326057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2770326057
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2190539242
Short name T67
Test name
Test status
Simulation time 559122376 ps
CPU time 3.2 seconds
Started Jul 12 05:03:33 PM PDT 24
Finished Jul 12 05:03:36 PM PDT 24
Peak memory 217868 kb
Host smart-29c6f5ef-e35c-4b9e-b39d-68bb0e6c733c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190539242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2190539242
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2262843572
Short name T72
Test name
Test status
Simulation time 4294544026 ps
CPU time 10.98 seconds
Started Jul 12 05:03:36 PM PDT 24
Finished Jul 12 05:03:48 PM PDT 24
Peak memory 201820 kb
Host smart-174324a0-91f9-4adb-94cb-7eee3b335a94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262843572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2262843572
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3509360641
Short name T827
Test name
Test status
Simulation time 473944912 ps
CPU time 2.05 seconds
Started Jul 12 05:03:48 PM PDT 24
Finished Jul 12 05:03:51 PM PDT 24
Peak memory 201448 kb
Host smart-3c2b800f-f523-42ae-84cb-8e791fc993b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509360641 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3509360641
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1982469771
Short name T872
Test name
Test status
Simulation time 484204396 ps
CPU time 1 seconds
Started Jul 12 05:03:40 PM PDT 24
Finished Jul 12 05:03:43 PM PDT 24
Peak memory 201452 kb
Host smart-294440ec-de04-4c9b-8031-398c13af1483
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982469771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1982469771
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.547240583
Short name T817
Test name
Test status
Simulation time 335310366 ps
CPU time 1.44 seconds
Started Jul 12 05:03:48 PM PDT 24
Finished Jul 12 05:03:51 PM PDT 24
Peak memory 201620 kb
Host smart-133049bb-c655-48ae-8d77-38304874e1d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547240583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.547240583
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2839468789
Short name T51
Test name
Test status
Simulation time 2290946975 ps
CPU time 5.79 seconds
Started Jul 12 05:03:52 PM PDT 24
Finished Jul 12 05:04:00 PM PDT 24
Peak memory 201468 kb
Host smart-883835ee-ba74-4fb0-a8c5-ecb35e730158
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839468789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2839468789
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.4142714558
Short name T826
Test name
Test status
Simulation time 550861269 ps
CPU time 2.32 seconds
Started Jul 12 05:03:57 PM PDT 24
Finished Jul 12 05:04:00 PM PDT 24
Peak memory 217984 kb
Host smart-b0af320a-548b-4937-9874-3e1c190423ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142714558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.4142714558
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.995885080
Short name T886
Test name
Test status
Simulation time 509936625 ps
CPU time 1.24 seconds
Started Jul 12 05:03:44 PM PDT 24
Finished Jul 12 05:03:48 PM PDT 24
Peak memory 201556 kb
Host smart-db642228-0340-49d7-8831-ba8897c165f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995885080 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.995885080
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.833849009
Short name T112
Test name
Test status
Simulation time 411462958 ps
CPU time 1.86 seconds
Started Jul 12 05:03:52 PM PDT 24
Finished Jul 12 05:03:55 PM PDT 24
Peak memory 201388 kb
Host smart-8f96ee0a-28cc-466e-b1c8-adb2742b6afb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833849009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.833849009
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3346459236
Short name T899
Test name
Test status
Simulation time 396093448 ps
CPU time 1.11 seconds
Started Jul 12 05:03:44 PM PDT 24
Finished Jul 12 05:03:48 PM PDT 24
Peak memory 201352 kb
Host smart-ced68745-2903-4b1b-a6c1-a2cf8af08faa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346459236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3346459236
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.103003345
Short name T915
Test name
Test status
Simulation time 2640177472 ps
CPU time 2.4 seconds
Started Jul 12 05:03:41 PM PDT 24
Finished Jul 12 05:03:44 PM PDT 24
Peak memory 201612 kb
Host smart-9a7363fa-4289-402a-8d8c-294f91e0fb22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103003345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.103003345
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2507467107
Short name T834
Test name
Test status
Simulation time 988922848 ps
CPU time 2.29 seconds
Started Jul 12 05:03:41 PM PDT 24
Finished Jul 12 05:03:45 PM PDT 24
Peak memory 201632 kb
Host smart-dac3ce7c-f9de-4978-81b5-87065e234506
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507467107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2507467107
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3338297731
Short name T914
Test name
Test status
Simulation time 4147378883 ps
CPU time 10.12 seconds
Started Jul 12 05:03:42 PM PDT 24
Finished Jul 12 05:03:54 PM PDT 24
Peak memory 201888 kb
Host smart-650e4eda-46f0-419e-a6fb-78f8535e0947
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338297731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3338297731
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.169392044
Short name T528
Test name
Test status
Simulation time 407739835 ps
CPU time 0.82 seconds
Started Jul 12 05:04:01 PM PDT 24
Finished Jul 12 05:04:05 PM PDT 24
Peak memory 201604 kb
Host smart-49d1c77d-e9a8-40e0-acb0-0d54c57c3dd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169392044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.169392044
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2422708740
Short name T607
Test name
Test status
Simulation time 335294314046 ps
CPU time 212.68 seconds
Started Jul 12 05:04:00 PM PDT 24
Finished Jul 12 05:07:36 PM PDT 24
Peak memory 201908 kb
Host smart-958749d5-c4de-46f3-aca8-f66849b8b9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422708740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2422708740
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1413262582
Short name T303
Test name
Test status
Simulation time 334684081338 ps
CPU time 196.92 seconds
Started Jul 12 05:04:01 PM PDT 24
Finished Jul 12 05:07:21 PM PDT 24
Peak memory 202080 kb
Host smart-b8e8d083-a602-4c78-ace9-653b2f64b3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413262582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1413262582
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.555145818
Short name T467
Test name
Test status
Simulation time 175569839814 ps
CPU time 401.38 seconds
Started Jul 12 05:03:58 PM PDT 24
Finished Jul 12 05:10:42 PM PDT 24
Peak memory 201780 kb
Host smart-9cc76c53-9235-4bc8-a68d-79f8d7290f27
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=555145818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.555145818
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.306676962
Short name T163
Test name
Test status
Simulation time 172228218031 ps
CPU time 386.19 seconds
Started Jul 12 05:04:01 PM PDT 24
Finished Jul 12 05:10:30 PM PDT 24
Peak memory 201844 kb
Host smart-24cde215-e8a2-4970-ab3a-2d5ea3bbba3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306676962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.306676962
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1818084113
Short name T3
Test name
Test status
Simulation time 490350437630 ps
CPU time 1004.96 seconds
Started Jul 12 05:04:01 PM PDT 24
Finished Jul 12 05:20:49 PM PDT 24
Peak memory 201884 kb
Host smart-cdec744b-5c1a-4243-9a42-c0c20b9a859e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818084113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1818084113
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.4094015609
Short name T499
Test name
Test status
Simulation time 611810721532 ps
CPU time 367.7 seconds
Started Jul 12 05:04:01 PM PDT 24
Finished Jul 12 05:10:12 PM PDT 24
Peak memory 201796 kb
Host smart-7084294d-8be4-4faf-9d24-1051bb8f2438
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094015609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.4094015609
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3549245306
Short name T554
Test name
Test status
Simulation time 78150064532 ps
CPU time 374.24 seconds
Started Jul 12 05:04:00 PM PDT 24
Finished Jul 12 05:10:17 PM PDT 24
Peak memory 202276 kb
Host smart-933f0d02-8d7f-46bd-806e-a2578eb11462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549245306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3549245306
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.996254181
Short name T388
Test name
Test status
Simulation time 32741033347 ps
CPU time 39.09 seconds
Started Jul 12 05:04:02 PM PDT 24
Finished Jul 12 05:04:44 PM PDT 24
Peak memory 201668 kb
Host smart-989a72e3-aac7-400f-bba8-729aa83460aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996254181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.996254181
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3571685598
Short name T482
Test name
Test status
Simulation time 4673268672 ps
CPU time 5.68 seconds
Started Jul 12 05:04:00 PM PDT 24
Finished Jul 12 05:04:09 PM PDT 24
Peak memory 201664 kb
Host smart-cf597fd0-61db-4e2a-b5de-feef63bfb19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571685598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3571685598
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2788927810
Short name T62
Test name
Test status
Simulation time 7916998228 ps
CPU time 18.96 seconds
Started Jul 12 05:03:58 PM PDT 24
Finished Jul 12 05:04:19 PM PDT 24
Peak memory 218276 kb
Host smart-d5da0eec-5d2f-4d55-9c6c-d23e57649c64
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788927810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2788927810
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1357873940
Short name T7
Test name
Test status
Simulation time 5776335711 ps
CPU time 9.47 seconds
Started Jul 12 05:04:03 PM PDT 24
Finished Jul 12 05:04:16 PM PDT 24
Peak memory 201560 kb
Host smart-b3c2e6d7-070b-452d-abac-1773f0dd99d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357873940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1357873940
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3347357350
Short name T91
Test name
Test status
Simulation time 789342132893 ps
CPU time 827.06 seconds
Started Jul 12 05:04:05 PM PDT 24
Finished Jul 12 05:17:54 PM PDT 24
Peak memory 202196 kb
Host smart-ccb4477b-1e8b-41fb-a9ce-7c5833b93a32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347357350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3347357350
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1647476714
Short name T605
Test name
Test status
Simulation time 7825291648 ps
CPU time 21.32 seconds
Started Jul 12 05:04:05 PM PDT 24
Finished Jul 12 05:04:28 PM PDT 24
Peak memory 210520 kb
Host smart-c70ab2e8-19dd-4aea-9c1f-f048246b8fdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647476714 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.1647476714
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1619376132
Short name T417
Test name
Test status
Simulation time 324750242 ps
CPU time 0.83 seconds
Started Jul 12 05:03:58 PM PDT 24
Finished Jul 12 05:04:01 PM PDT 24
Peak memory 201668 kb
Host smart-ade616a9-1a02-458b-bde1-28ebcc0ba5f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619376132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1619376132
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2148170040
Short name T302
Test name
Test status
Simulation time 162710985502 ps
CPU time 138.56 seconds
Started Jul 12 05:04:01 PM PDT 24
Finished Jul 12 05:06:23 PM PDT 24
Peak memory 202060 kb
Host smart-a99b997b-1cf9-4d75-a098-32deef3b641e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148170040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2148170040
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2077656676
Short name T752
Test name
Test status
Simulation time 493159135445 ps
CPU time 1108.03 seconds
Started Jul 12 05:03:59 PM PDT 24
Finished Jul 12 05:22:30 PM PDT 24
Peak memory 201888 kb
Host smart-951d0b03-efce-4fbb-9b94-d1483d38b70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077656676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2077656676
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3300259828
Short name T260
Test name
Test status
Simulation time 161240728723 ps
CPU time 282.22 seconds
Started Jul 12 05:04:00 PM PDT 24
Finished Jul 12 05:08:46 PM PDT 24
Peak memory 201856 kb
Host smart-973f870e-2ce2-4a79-829b-9fcbb0194baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300259828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3300259828
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1362517867
Short name T642
Test name
Test status
Simulation time 329063363493 ps
CPU time 96.9 seconds
Started Jul 12 05:04:04 PM PDT 24
Finished Jul 12 05:05:43 PM PDT 24
Peak memory 201828 kb
Host smart-a40dfd7b-f364-4ea0-9af8-316ad33f0e7f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362517867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1362517867
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.121252603
Short name T174
Test name
Test status
Simulation time 330880496977 ps
CPU time 183.85 seconds
Started Jul 12 05:04:03 PM PDT 24
Finished Jul 12 05:07:10 PM PDT 24
Peak memory 201888 kb
Host smart-e3d9d793-fd15-400b-9f72-18ce47f04e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121252603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.121252603
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.646131011
Short name T541
Test name
Test status
Simulation time 481596238084 ps
CPU time 263.13 seconds
Started Jul 12 05:03:59 PM PDT 24
Finished Jul 12 05:08:25 PM PDT 24
Peak memory 201764 kb
Host smart-6336d03c-94a6-4763-97e2-fd2ac83ba9e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=646131011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed
.646131011
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2199277039
Short name T552
Test name
Test status
Simulation time 204641760466 ps
CPU time 106.49 seconds
Started Jul 12 05:04:01 PM PDT 24
Finished Jul 12 05:05:50 PM PDT 24
Peak memory 201760 kb
Host smart-5728111f-0e45-4fd1-a99e-2d231c9201a2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199277039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2199277039
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1885620516
Short name T203
Test name
Test status
Simulation time 132933775319 ps
CPU time 668 seconds
Started Jul 12 05:04:00 PM PDT 24
Finished Jul 12 05:15:12 PM PDT 24
Peak memory 202208 kb
Host smart-dfe76c5f-7e22-44f9-8b93-b89585f5816a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885620516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1885620516
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2227217101
Short name T380
Test name
Test status
Simulation time 45317572088 ps
CPU time 17.8 seconds
Started Jul 12 05:03:59 PM PDT 24
Finished Jul 12 05:04:19 PM PDT 24
Peak memory 201700 kb
Host smart-fca0fe61-83b3-4eb4-ac19-dd00805dfb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227217101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2227217101
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1292435447
Short name T628
Test name
Test status
Simulation time 4321467760 ps
CPU time 6.12 seconds
Started Jul 12 05:03:59 PM PDT 24
Finished Jul 12 05:04:08 PM PDT 24
Peak memory 201624 kb
Host smart-424e718f-2791-41ae-bea2-9575c345889a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292435447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1292435447
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3430642837
Short name T63
Test name
Test status
Simulation time 7649616999 ps
CPU time 5.36 seconds
Started Jul 12 05:04:04 PM PDT 24
Finished Jul 12 05:04:12 PM PDT 24
Peak memory 218372 kb
Host smart-fe6c8817-03bd-419e-93eb-0ece4eee4ebf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430642837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3430642837
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2144561423
Short name T545
Test name
Test status
Simulation time 5925662117 ps
CPU time 13.38 seconds
Started Jul 12 05:04:01 PM PDT 24
Finished Jul 12 05:04:18 PM PDT 24
Peak memory 201892 kb
Host smart-d323df38-c10b-429d-b662-3cb6d562870d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144561423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2144561423
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3361807761
Short name T770
Test name
Test status
Simulation time 437577613192 ps
CPU time 1154.42 seconds
Started Jul 12 05:04:09 PM PDT 24
Finished Jul 12 05:23:24 PM PDT 24
Peak memory 210416 kb
Host smart-5abed1f8-49ae-4739-95c4-7643d9786e07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361807761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3361807761
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2981768332
Short name T415
Test name
Test status
Simulation time 494874322 ps
CPU time 1.15 seconds
Started Jul 12 05:04:34 PM PDT 24
Finished Jul 12 05:04:36 PM PDT 24
Peak memory 201528 kb
Host smart-a239da02-c42a-4386-8455-fd4a0ff31096
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981768332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2981768332
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2158726384
Short name T676
Test name
Test status
Simulation time 328303100093 ps
CPU time 687.89 seconds
Started Jul 12 05:04:26 PM PDT 24
Finished Jul 12 05:15:56 PM PDT 24
Peak memory 201808 kb
Host smart-7755d987-3547-484f-a8aa-4af7aa6129dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158726384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2158726384
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3767336544
Short name T788
Test name
Test status
Simulation time 163678268853 ps
CPU time 93.37 seconds
Started Jul 12 05:04:27 PM PDT 24
Finished Jul 12 05:06:02 PM PDT 24
Peak memory 201912 kb
Host smart-e8369bde-dfac-4740-97f0-675297238374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767336544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3767336544
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2932811500
Short name T147
Test name
Test status
Simulation time 497511253311 ps
CPU time 100.99 seconds
Started Jul 12 05:04:33 PM PDT 24
Finished Jul 12 05:06:15 PM PDT 24
Peak memory 201904 kb
Host smart-f0fbf3b3-4aa9-4800-a0ba-fc3552b31591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932811500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2932811500
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.122647880
Short name T475
Test name
Test status
Simulation time 327455309309 ps
CPU time 769.05 seconds
Started Jul 12 05:04:29 PM PDT 24
Finished Jul 12 05:17:20 PM PDT 24
Peak memory 201872 kb
Host smart-4b7ec63f-2cab-46d1-948d-6d8648449fe4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=122647880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrup
t_fixed.122647880
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2376283077
Short name T434
Test name
Test status
Simulation time 334094211749 ps
CPU time 181.12 seconds
Started Jul 12 05:04:23 PM PDT 24
Finished Jul 12 05:07:25 PM PDT 24
Peak memory 201960 kb
Host smart-da81d191-27c5-4681-91e5-a460237e27dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376283077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2376283077
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.2089676631
Short name T393
Test name
Test status
Simulation time 161746932104 ps
CPU time 311.57 seconds
Started Jul 12 05:04:24 PM PDT 24
Finished Jul 12 05:09:37 PM PDT 24
Peak memory 201816 kb
Host smart-951f6f41-4f86-4ecc-98bb-a4088b7a64a1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089676631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.2089676631
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.990256690
Short name T769
Test name
Test status
Simulation time 573729075982 ps
CPU time 333.83 seconds
Started Jul 12 05:04:28 PM PDT 24
Finished Jul 12 05:10:04 PM PDT 24
Peak memory 201976 kb
Host smart-90145a70-74f5-48df-98ac-466cb54f7207
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990256690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.990256690
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2174342234
Short name T228
Test name
Test status
Simulation time 605562210991 ps
CPU time 288.15 seconds
Started Jul 12 05:04:27 PM PDT 24
Finished Jul 12 05:09:17 PM PDT 24
Peak memory 201880 kb
Host smart-c881be08-3a55-4c7e-8fe8-17259c968b88
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174342234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2174342234
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3890538921
Short name T86
Test name
Test status
Simulation time 32868583262 ps
CPU time 36.53 seconds
Started Jul 12 05:04:31 PM PDT 24
Finished Jul 12 05:05:10 PM PDT 24
Peak memory 201772 kb
Host smart-7bcde6bc-aa1c-40d2-89df-1faaa0ec2802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890538921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3890538921
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2083597419
Short name T568
Test name
Test status
Simulation time 4448473464 ps
CPU time 9.98 seconds
Started Jul 12 05:04:28 PM PDT 24
Finished Jul 12 05:04:40 PM PDT 24
Peak memory 201708 kb
Host smart-4f2cfdb4-ac3b-49ce-9d55-763c23ce7576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083597419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2083597419
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3018467442
Short name T767
Test name
Test status
Simulation time 5899084513 ps
CPU time 14.67 seconds
Started Jul 12 05:04:33 PM PDT 24
Finished Jul 12 05:04:49 PM PDT 24
Peak memory 201700 kb
Host smart-506c4292-9ca5-47a0-9fc7-4910669ab150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018467442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3018467442
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1199928820
Short name T551
Test name
Test status
Simulation time 195035816852 ps
CPU time 414.69 seconds
Started Jul 12 05:04:35 PM PDT 24
Finished Jul 12 05:11:31 PM PDT 24
Peak memory 201848 kb
Host smart-66e95b9f-9453-4cbf-8114-bd29168c127f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199928820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1199928820
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2414092324
Short name T544
Test name
Test status
Simulation time 35863501305 ps
CPU time 70.77 seconds
Started Jul 12 05:04:35 PM PDT 24
Finished Jul 12 05:05:47 PM PDT 24
Peak memory 210216 kb
Host smart-3761c9e1-4f7f-48f1-a00a-3369ba9c37b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414092324 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2414092324
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.4204963702
Short name T600
Test name
Test status
Simulation time 529604084 ps
CPU time 0.98 seconds
Started Jul 12 05:04:34 PM PDT 24
Finished Jul 12 05:04:36 PM PDT 24
Peak memory 201568 kb
Host smart-24c447f9-9e68-4d3c-b7ff-3f1e7ba38b1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204963702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.4204963702
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2167696993
Short name T620
Test name
Test status
Simulation time 171807848111 ps
CPU time 204.73 seconds
Started Jul 12 05:04:36 PM PDT 24
Finished Jul 12 05:08:02 PM PDT 24
Peak memory 201808 kb
Host smart-ee29fa5e-28ec-4136-89e6-3cc75eab1209
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167696993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2167696993
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.961691270
Short name T491
Test name
Test status
Simulation time 160893158040 ps
CPU time 136.26 seconds
Started Jul 12 05:04:33 PM PDT 24
Finished Jul 12 05:06:50 PM PDT 24
Peak memory 201908 kb
Host smart-6cca78dc-7cee-4cdf-9829-d90d01d5a2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961691270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.961691270
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.1776009064
Short name T316
Test name
Test status
Simulation time 162542311590 ps
CPU time 385.26 seconds
Started Jul 12 05:04:35 PM PDT 24
Finished Jul 12 05:11:02 PM PDT 24
Peak memory 201808 kb
Host smart-b9db33bb-1199-433b-b739-2319bd41d85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776009064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1776009064
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2790637668
Short name T570
Test name
Test status
Simulation time 487336980216 ps
CPU time 1192.43 seconds
Started Jul 12 05:04:41 PM PDT 24
Finished Jul 12 05:24:35 PM PDT 24
Peak memory 202056 kb
Host smart-1bc32db9-eaa6-4eb8-9d76-f7901a942327
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790637668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2790637668
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.85596277
Short name T684
Test name
Test status
Simulation time 159139616718 ps
CPU time 335.05 seconds
Started Jul 12 05:04:38 PM PDT 24
Finished Jul 12 05:10:14 PM PDT 24
Peak memory 201908 kb
Host smart-9cba3d87-b9fa-4774-8d5f-9ca7a1cbfa88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85596277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.85596277
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.815589567
Short name T438
Test name
Test status
Simulation time 164875888641 ps
CPU time 361.06 seconds
Started Jul 12 05:04:36 PM PDT 24
Finished Jul 12 05:10:38 PM PDT 24
Peak memory 201896 kb
Host smart-d0811296-331c-4f51-b06c-5bacfcf8c702
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=815589567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixe
d.815589567
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.67295042
Short name T45
Test name
Test status
Simulation time 194310528776 ps
CPU time 201.41 seconds
Started Jul 12 05:04:42 PM PDT 24
Finished Jul 12 05:08:05 PM PDT 24
Peak memory 201896 kb
Host smart-83db4537-2c2d-4b07-bb49-a30a72be523d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67295042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_w
akeup.67295042
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1351246082
Short name T578
Test name
Test status
Simulation time 201557534857 ps
CPU time 444.28 seconds
Started Jul 12 05:04:32 PM PDT 24
Finished Jul 12 05:11:58 PM PDT 24
Peak memory 201840 kb
Host smart-42beee0b-205e-4166-87b9-b25155d473b4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351246082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1351246082
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3751879225
Short name T210
Test name
Test status
Simulation time 74656596486 ps
CPU time 317.74 seconds
Started Jul 12 05:04:38 PM PDT 24
Finished Jul 12 05:09:57 PM PDT 24
Peak memory 202092 kb
Host smart-7cbf26da-bc18-4d42-9eac-d961f632b389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751879225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3751879225
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3340509099
Short name T347
Test name
Test status
Simulation time 29793852498 ps
CPU time 68.45 seconds
Started Jul 12 05:04:40 PM PDT 24
Finished Jul 12 05:05:50 PM PDT 24
Peak memory 201692 kb
Host smart-c26c4c43-6b13-4cac-87a8-75c91275a997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340509099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3340509099
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1603012922
Short name T366
Test name
Test status
Simulation time 3719927412 ps
CPU time 2.79 seconds
Started Jul 12 05:04:38 PM PDT 24
Finished Jul 12 05:04:42 PM PDT 24
Peak memory 201572 kb
Host smart-9676bf70-a47f-4757-87c7-6211809e46ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603012922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1603012922
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3619362902
Short name T10
Test name
Test status
Simulation time 5736400760 ps
CPU time 7.39 seconds
Started Jul 12 05:04:34 PM PDT 24
Finished Jul 12 05:04:43 PM PDT 24
Peak memory 201636 kb
Host smart-21690598-8370-423f-aa63-3c72a65ecb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619362902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3619362902
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3635657508
Short name T712
Test name
Test status
Simulation time 388496605638 ps
CPU time 791.5 seconds
Started Jul 12 05:04:32 PM PDT 24
Finished Jul 12 05:17:45 PM PDT 24
Peak memory 201808 kb
Host smart-2feeeb78-ccd4-4397-9913-36bb1f2cda58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635657508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3635657508
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.843994733
Short name T21
Test name
Test status
Simulation time 23767402941 ps
CPU time 55.84 seconds
Started Jul 12 05:04:34 PM PDT 24
Finished Jul 12 05:05:31 PM PDT 24
Peak memory 210460 kb
Host smart-65ff3f6e-0832-4c58-b263-c8bb062f4eef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843994733 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.843994733
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2780886346
Short name T110
Test name
Test status
Simulation time 305166681 ps
CPU time 1.04 seconds
Started Jul 12 05:04:41 PM PDT 24
Finished Jul 12 05:04:44 PM PDT 24
Peak memory 201616 kb
Host smart-470af667-7a68-43ba-96b3-706f648ba513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780886346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2780886346
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2694778456
Short name T220
Test name
Test status
Simulation time 325163084400 ps
CPU time 762.22 seconds
Started Jul 12 05:04:40 PM PDT 24
Finished Jul 12 05:17:24 PM PDT 24
Peak memory 201684 kb
Host smart-7abac0d7-edf8-45d5-a70e-5d3bb37a42dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694778456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2694778456
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.917103131
Short name T459
Test name
Test status
Simulation time 504073328018 ps
CPU time 1170.43 seconds
Started Jul 12 05:04:41 PM PDT 24
Finished Jul 12 05:24:13 PM PDT 24
Peak memory 202072 kb
Host smart-c32c113a-7426-4d79-bf2e-619e9c35604c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=917103131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrup
t_fixed.917103131
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1471379781
Short name T504
Test name
Test status
Simulation time 159190829883 ps
CPU time 175.26 seconds
Started Jul 12 05:04:33 PM PDT 24
Finished Jul 12 05:07:29 PM PDT 24
Peak memory 201964 kb
Host smart-16d8ccd7-8e16-411a-9ffc-9c7300c41196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471379781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1471379781
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2286584154
Short name T680
Test name
Test status
Simulation time 163872102042 ps
CPU time 378.01 seconds
Started Jul 12 05:04:36 PM PDT 24
Finished Jul 12 05:10:55 PM PDT 24
Peak memory 201888 kb
Host smart-b5a0dbff-faf2-43d0-94c0-cb98b1e55127
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286584154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2286584154
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.85639988
Short name T428
Test name
Test status
Simulation time 610365894235 ps
CPU time 633.82 seconds
Started Jul 12 05:04:36 PM PDT 24
Finished Jul 12 05:15:12 PM PDT 24
Peak memory 201800 kb
Host smart-12566723-6f3e-45b6-b466-cf25cd1fbafb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85639988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.a
dc_ctrl_filters_wakeup_fixed.85639988
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.1881842852
Short name T356
Test name
Test status
Simulation time 45195826342 ps
CPU time 27.06 seconds
Started Jul 12 05:04:34 PM PDT 24
Finished Jul 12 05:05:02 PM PDT 24
Peak memory 201584 kb
Host smart-ae32dd99-8a68-4b64-9368-f6743989a5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881842852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.1881842852
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2539253022
Short name T771
Test name
Test status
Simulation time 4078204032 ps
CPU time 3.29 seconds
Started Jul 12 05:04:33 PM PDT 24
Finished Jul 12 05:04:38 PM PDT 24
Peak memory 201700 kb
Host smart-a0a7259e-588d-4c46-81a1-2346873164c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539253022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2539253022
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3875598277
Short name T343
Test name
Test status
Simulation time 5812826989 ps
CPU time 3.39 seconds
Started Jul 12 05:04:40 PM PDT 24
Finished Jul 12 05:04:45 PM PDT 24
Peak memory 201860 kb
Host smart-c472de65-1f77-4eb9-a74d-e6f6089cd296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875598277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3875598277
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1844472504
Short name T783
Test name
Test status
Simulation time 326865304008 ps
CPU time 431.86 seconds
Started Jul 12 05:04:34 PM PDT 24
Finished Jul 12 05:11:47 PM PDT 24
Peak memory 201808 kb
Host smart-e77f7351-e755-4592-af00-81a82b159d5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844472504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1844472504
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3639531441
Short name T731
Test name
Test status
Simulation time 29025585099 ps
CPU time 57.46 seconds
Started Jul 12 05:04:33 PM PDT 24
Finished Jul 12 05:05:32 PM PDT 24
Peak memory 210532 kb
Host smart-7967455a-bf0a-4276-a064-2917fd69179f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639531441 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3639531441
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.911723128
Short name T529
Test name
Test status
Simulation time 446165026 ps
CPU time 1.67 seconds
Started Jul 12 05:04:39 PM PDT 24
Finished Jul 12 05:04:43 PM PDT 24
Peak memory 201640 kb
Host smart-40a9ee47-af7e-4dee-851c-8c1d1932a0f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911723128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.911723128
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3977010432
Short name T588
Test name
Test status
Simulation time 347786695896 ps
CPU time 615.43 seconds
Started Jul 12 05:04:34 PM PDT 24
Finished Jul 12 05:14:51 PM PDT 24
Peak memory 201884 kb
Host smart-8c75655b-bba0-4dd0-b0fc-0a0ab3c3497a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977010432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3977010432
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3634565332
Short name T543
Test name
Test status
Simulation time 163538098457 ps
CPU time 72.11 seconds
Started Jul 12 05:04:38 PM PDT 24
Finished Jul 12 05:05:52 PM PDT 24
Peak memory 201780 kb
Host smart-1886a44c-36ed-42c7-995a-474a6cb51afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634565332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3634565332
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2033809561
Short name T172
Test name
Test status
Simulation time 165258676740 ps
CPU time 357.29 seconds
Started Jul 12 05:04:36 PM PDT 24
Finished Jul 12 05:10:34 PM PDT 24
Peak memory 201812 kb
Host smart-fd23504c-5352-407a-a1bc-e1856c9a1fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033809561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2033809561
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3050624465
Short name T522
Test name
Test status
Simulation time 498653089858 ps
CPU time 287.92 seconds
Started Jul 12 05:04:38 PM PDT 24
Finished Jul 12 05:09:27 PM PDT 24
Peak memory 201824 kb
Host smart-86b5b779-9e50-4a92-a280-7d629fa67345
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050624465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3050624465
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.478998738
Short name T789
Test name
Test status
Simulation time 338144829089 ps
CPU time 188.45 seconds
Started Jul 12 05:04:36 PM PDT 24
Finished Jul 12 05:07:46 PM PDT 24
Peak memory 201916 kb
Host smart-2051f3ba-1dbd-4faa-801a-e6a647e3d988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478998738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.478998738
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1767331685
Short name T754
Test name
Test status
Simulation time 486920176246 ps
CPU time 597.4 seconds
Started Jul 12 05:04:33 PM PDT 24
Finished Jul 12 05:14:32 PM PDT 24
Peak memory 201752 kb
Host smart-a6290461-29c4-430b-85c0-c350fb7ae6d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767331685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1767331685
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.1251965376
Short name T591
Test name
Test status
Simulation time 178793928296 ps
CPU time 368.35 seconds
Started Jul 12 05:04:36 PM PDT 24
Finished Jul 12 05:10:45 PM PDT 24
Peak memory 201888 kb
Host smart-ecc3f84a-ecf5-40be-8e81-82e6aec11d08
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251965376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.1251965376
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3936889496
Short name T358
Test name
Test status
Simulation time 579979635352 ps
CPU time 1275.93 seconds
Started Jul 12 05:04:36 PM PDT 24
Finished Jul 12 05:25:53 PM PDT 24
Peak memory 201792 kb
Host smart-e46a45ce-2825-40cb-b4b4-c68876a58ca8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936889496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3936889496
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2102048557
Short name T209
Test name
Test status
Simulation time 99765295209 ps
CPU time 482.91 seconds
Started Jul 12 05:04:38 PM PDT 24
Finished Jul 12 05:12:42 PM PDT 24
Peak memory 202092 kb
Host smart-730df417-757d-4c4c-9f61-36253deaf023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102048557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2102048557
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.505065241
Short name T479
Test name
Test status
Simulation time 44422984602 ps
CPU time 25.26 seconds
Started Jul 12 05:04:35 PM PDT 24
Finished Jul 12 05:05:01 PM PDT 24
Peak memory 201644 kb
Host smart-d92437ca-b174-4968-9d4a-0ca5aa36843f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505065241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.505065241
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2846196094
Short name T785
Test name
Test status
Simulation time 3661797531 ps
CPU time 4.6 seconds
Started Jul 12 05:04:37 PM PDT 24
Finished Jul 12 05:04:43 PM PDT 24
Peak memory 201700 kb
Host smart-8a36ab45-5702-4ef7-bae2-7d8db06efa59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846196094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2846196094
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.960279753
Short name T489
Test name
Test status
Simulation time 5799394122 ps
CPU time 7 seconds
Started Jul 12 05:04:33 PM PDT 24
Finished Jul 12 05:04:41 PM PDT 24
Peak memory 201700 kb
Host smart-72c3b7a0-0780-4b0b-9dbe-a18f357d11ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960279753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.960279753
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3340187565
Short name T233
Test name
Test status
Simulation time 403423804347 ps
CPU time 770.15 seconds
Started Jul 12 05:04:41 PM PDT 24
Finished Jul 12 05:17:33 PM PDT 24
Peak memory 201864 kb
Host smart-844c8a20-cb1b-47cb-8cd0-09361700245f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340187565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3340187565
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1040716848
Short name T461
Test name
Test status
Simulation time 365601837 ps
CPU time 1.04 seconds
Started Jul 12 05:04:38 PM PDT 24
Finished Jul 12 05:04:40 PM PDT 24
Peak memory 201608 kb
Host smart-38559069-f5a7-48d3-b77f-afcb17fb230b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040716848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1040716848
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.2246839998
Short name T32
Test name
Test status
Simulation time 184017704600 ps
CPU time 196.22 seconds
Started Jul 12 05:04:36 PM PDT 24
Finished Jul 12 05:07:54 PM PDT 24
Peak memory 201904 kb
Host smart-5dfde290-d7cc-450f-81d6-f9474b347ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246839998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.2246839998
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.510634062
Short name T269
Test name
Test status
Simulation time 325685438106 ps
CPU time 398.29 seconds
Started Jul 12 05:04:36 PM PDT 24
Finished Jul 12 05:11:16 PM PDT 24
Peak memory 201808 kb
Host smart-bc271754-b96f-4549-b72f-0831577abf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510634062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.510634062
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2642062299
Short name T422
Test name
Test status
Simulation time 327475196143 ps
CPU time 788.89 seconds
Started Jul 12 05:04:38 PM PDT 24
Finished Jul 12 05:17:48 PM PDT 24
Peak memory 201744 kb
Host smart-ce3f12f6-6dd9-4e47-901a-0f8463d8b093
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642062299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2642062299
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1082674000
Short name T508
Test name
Test status
Simulation time 168116207554 ps
CPU time 344.72 seconds
Started Jul 12 05:04:34 PM PDT 24
Finished Jul 12 05:10:20 PM PDT 24
Peak memory 201880 kb
Host smart-1917dc06-c848-4b43-a3fb-783d5ab52074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082674000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1082674000
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.3137290920
Short name T447
Test name
Test status
Simulation time 163765544896 ps
CPU time 366.81 seconds
Started Jul 12 05:04:39 PM PDT 24
Finished Jul 12 05:10:48 PM PDT 24
Peak memory 201860 kb
Host smart-6917730f-f74c-4b43-bc2b-78815274df07
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137290920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.3137290920
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.4251395400
Short name T709
Test name
Test status
Simulation time 173730079784 ps
CPU time 106.18 seconds
Started Jul 12 05:04:41 PM PDT 24
Finished Jul 12 05:06:29 PM PDT 24
Peak memory 201268 kb
Host smart-c346802e-ba3e-4c23-b69e-a99d3a379af0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251395400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.4251395400
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2347251463
Short name T597
Test name
Test status
Simulation time 398550493177 ps
CPU time 446.33 seconds
Started Jul 12 05:04:37 PM PDT 24
Finished Jul 12 05:12:04 PM PDT 24
Peak memory 201780 kb
Host smart-8cf81d07-e91e-4fda-9b72-5c9b33976b9c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347251463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2347251463
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.644242341
Short name T531
Test name
Test status
Simulation time 119686379977 ps
CPU time 560.44 seconds
Started Jul 12 05:04:41 PM PDT 24
Finished Jul 12 05:14:03 PM PDT 24
Peak memory 201508 kb
Host smart-f40e1b59-f8f8-4226-b765-db826eed2fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644242341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.644242341
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1839012719
Short name T599
Test name
Test status
Simulation time 44271693341 ps
CPU time 28.08 seconds
Started Jul 12 05:04:40 PM PDT 24
Finished Jul 12 05:05:10 PM PDT 24
Peak memory 201688 kb
Host smart-92807388-2b99-48db-a097-40188a9a3648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839012719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1839012719
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2769455645
Short name T446
Test name
Test status
Simulation time 3950991940 ps
CPU time 2.45 seconds
Started Jul 12 05:04:36 PM PDT 24
Finished Jul 12 05:04:40 PM PDT 24
Peak memory 201612 kb
Host smart-628fedaa-5952-4311-bc87-1bb3bf8de306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769455645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2769455645
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.1678583154
Short name T427
Test name
Test status
Simulation time 5656132192 ps
CPU time 12.47 seconds
Started Jul 12 05:04:34 PM PDT 24
Finished Jul 12 05:04:48 PM PDT 24
Peak memory 201700 kb
Host smart-f9cc76dc-876c-4918-8b00-b9d9e256031e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678583154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1678583154
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3519716176
Short name T782
Test name
Test status
Simulation time 70420318281 ps
CPU time 79.03 seconds
Started Jul 12 05:04:36 PM PDT 24
Finished Jul 12 05:05:57 PM PDT 24
Peak memory 201708 kb
Host smart-1ef962f2-0532-4848-a022-35db8bfe0f3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519716176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3519716176
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2652879369
Short name T713
Test name
Test status
Simulation time 397373451 ps
CPU time 1.03 seconds
Started Jul 12 05:04:42 PM PDT 24
Finished Jul 12 05:04:44 PM PDT 24
Peak memory 201556 kb
Host smart-e24b0698-b9fa-4cfd-ac4d-410eab895e69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652879369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2652879369
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.766034795
Short name T669
Test name
Test status
Simulation time 338341459757 ps
CPU time 190.31 seconds
Started Jul 12 05:04:39 PM PDT 24
Finished Jul 12 05:07:50 PM PDT 24
Peak memory 201972 kb
Host smart-0b9c0923-5ff9-4923-ad0d-c8ea430059d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766034795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gati
ng.766034795
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.4243289049
Short name T474
Test name
Test status
Simulation time 159780860429 ps
CPU time 101.2 seconds
Started Jul 12 05:04:51 PM PDT 24
Finished Jul 12 05:06:34 PM PDT 24
Peak memory 201476 kb
Host smart-268a0ac0-02a5-43cb-ad82-db93cb655ec2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243289049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.4243289049
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1837063256
Short name T537
Test name
Test status
Simulation time 331348769089 ps
CPU time 200.93 seconds
Started Jul 12 05:04:49 PM PDT 24
Finished Jul 12 05:08:11 PM PDT 24
Peak memory 201760 kb
Host smart-a6a410a5-390c-4a2d-8e8b-d046f6893285
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837063256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1837063256
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.2843363050
Short name T765
Test name
Test status
Simulation time 545959092295 ps
CPU time 316.78 seconds
Started Jul 12 05:04:45 PM PDT 24
Finished Jul 12 05:10:02 PM PDT 24
Peak memory 201820 kb
Host smart-a4c58c26-bfe0-4f36-a2d8-55fdb645871d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843363050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.2843363050
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2047118547
Short name T466
Test name
Test status
Simulation time 394548128267 ps
CPU time 933.83 seconds
Started Jul 12 05:04:52 PM PDT 24
Finished Jul 12 05:20:28 PM PDT 24
Peak memory 201760 kb
Host smart-2a06a0d6-7f7b-47f0-8973-f0660b997d6d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047118547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2047118547
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2613958015
Short name T465
Test name
Test status
Simulation time 45045937724 ps
CPU time 25.24 seconds
Started Jul 12 05:04:52 PM PDT 24
Finished Jul 12 05:05:19 PM PDT 24
Peak memory 201616 kb
Host smart-d13dfee7-371a-4508-9abc-2daf3a184af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613958015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2613958015
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1989903578
Short name T649
Test name
Test status
Simulation time 3482171461 ps
CPU time 8.98 seconds
Started Jul 12 05:04:41 PM PDT 24
Finished Jul 12 05:04:52 PM PDT 24
Peak memory 201680 kb
Host smart-ed6210da-6ba6-42b1-b488-cf7b9860ccba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989903578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1989903578
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1394781230
Short name T671
Test name
Test status
Simulation time 5773212255 ps
CPU time 12.94 seconds
Started Jul 12 05:04:39 PM PDT 24
Finished Jul 12 05:04:54 PM PDT 24
Peak memory 201556 kb
Host smart-66156609-7694-4176-af48-1fe59d8a1f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394781230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1394781230
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2414883073
Short name T473
Test name
Test status
Simulation time 13034692507 ps
CPU time 7.78 seconds
Started Jul 12 05:04:41 PM PDT 24
Finished Jul 12 05:04:50 PM PDT 24
Peak memory 201880 kb
Host smart-06d7f18e-4244-4158-804c-49245df14623
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414883073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2414883073
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3396301009
Short name T106
Test name
Test status
Simulation time 182513294296 ps
CPU time 45.45 seconds
Started Jul 12 05:04:38 PM PDT 24
Finished Jul 12 05:05:25 PM PDT 24
Peak memory 210224 kb
Host smart-e5dd0554-872d-486b-99e3-05d409b87196
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396301009 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3396301009
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2410430467
Short name T222
Test name
Test status
Simulation time 511921778687 ps
CPU time 108.49 seconds
Started Jul 12 05:04:49 PM PDT 24
Finished Jul 12 05:06:39 PM PDT 24
Peak memory 201776 kb
Host smart-a816e270-cd04-40f2-a503-51f50ef29146
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410430467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2410430467
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.695964442
Short name T184
Test name
Test status
Simulation time 187154078201 ps
CPU time 118.48 seconds
Started Jul 12 05:04:45 PM PDT 24
Finished Jul 12 05:06:45 PM PDT 24
Peak memory 201972 kb
Host smart-d8dea5a9-3c94-482a-ba26-cc53c64861e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695964442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.695964442
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2141436171
Short name T721
Test name
Test status
Simulation time 165657473442 ps
CPU time 374.81 seconds
Started Jul 12 05:04:43 PM PDT 24
Finished Jul 12 05:10:59 PM PDT 24
Peak memory 201860 kb
Host smart-d0322122-820d-4709-9872-13a0ca37f03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141436171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2141436171
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2992974803
Short name T445
Test name
Test status
Simulation time 331075930443 ps
CPU time 178.4 seconds
Started Jul 12 05:04:43 PM PDT 24
Finished Jul 12 05:07:42 PM PDT 24
Peak memory 201828 kb
Host smart-c07b3bde-a3ea-4a4f-836e-4abef86cf2b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992974803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2992974803
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3214117998
Short name T295
Test name
Test status
Simulation time 168437841753 ps
CPU time 383.99 seconds
Started Jul 12 05:04:44 PM PDT 24
Finished Jul 12 05:11:09 PM PDT 24
Peak memory 201832 kb
Host smart-4ac895d8-e304-40ef-b541-a061c7431c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214117998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3214117998
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3266738109
Short name T606
Test name
Test status
Simulation time 488763577184 ps
CPU time 278.22 seconds
Started Jul 12 05:04:42 PM PDT 24
Finished Jul 12 05:09:22 PM PDT 24
Peak memory 201876 kb
Host smart-17ea76df-b84b-4a51-b5d7-ab3405a1dd61
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266738109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3266738109
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2864333938
Short name T90
Test name
Test status
Simulation time 541078540847 ps
CPU time 322.72 seconds
Started Jul 12 05:04:39 PM PDT 24
Finished Jul 12 05:10:04 PM PDT 24
Peak memory 201816 kb
Host smart-810303a0-66aa-4972-91cc-bccf8c795b48
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864333938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2864333938
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2176617538
Short name T429
Test name
Test status
Simulation time 395902797135 ps
CPU time 274.14 seconds
Started Jul 12 05:04:44 PM PDT 24
Finished Jul 12 05:09:19 PM PDT 24
Peak memory 201872 kb
Host smart-a3495cd1-aabd-4737-82fa-b252cf7c5c5a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176617538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2176617538
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.886114473
Short name T757
Test name
Test status
Simulation time 126762230657 ps
CPU time 634.88 seconds
Started Jul 12 05:04:40 PM PDT 24
Finished Jul 12 05:15:17 PM PDT 24
Peak memory 202216 kb
Host smart-eb3b4d75-3f5e-4af2-9dd4-b28ea9c66631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886114473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.886114473
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.190857614
Short name T646
Test name
Test status
Simulation time 36141464492 ps
CPU time 62.5 seconds
Started Jul 12 05:04:48 PM PDT 24
Finished Jul 12 05:05:51 PM PDT 24
Peak memory 201592 kb
Host smart-2d1d1a6d-0bcb-4185-9cad-6643c76371af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190857614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.190857614
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.4273298273
Short name T435
Test name
Test status
Simulation time 3653056900 ps
CPU time 2.84 seconds
Started Jul 12 05:04:39 PM PDT 24
Finished Jul 12 05:04:44 PM PDT 24
Peak memory 201704 kb
Host smart-140bc838-e132-4d45-931e-dcc5b9297634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273298273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.4273298273
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3065129273
Short name T344
Test name
Test status
Simulation time 6054072851 ps
CPU time 7.38 seconds
Started Jul 12 05:04:43 PM PDT 24
Finished Jul 12 05:04:52 PM PDT 24
Peak memory 201652 kb
Host smart-0d75849b-a1bb-42b5-b742-4cf6271437d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065129273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3065129273
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.1676364581
Short name T750
Test name
Test status
Simulation time 421705814 ps
CPU time 0.71 seconds
Started Jul 12 05:04:54 PM PDT 24
Finished Jul 12 05:04:55 PM PDT 24
Peak memory 201520 kb
Host smart-a8134709-1e6a-4ff2-a708-317be75aa805
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676364581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1676364581
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1190743393
Short name T97
Test name
Test status
Simulation time 162372328780 ps
CPU time 355.4 seconds
Started Jul 12 05:04:48 PM PDT 24
Finished Jul 12 05:10:45 PM PDT 24
Peak memory 201800 kb
Host smart-cbff19e5-d929-4d67-9f87-c23c0eb3a264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190743393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1190743393
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1253711551
Short name T462
Test name
Test status
Simulation time 165662496463 ps
CPU time 28.5 seconds
Started Jul 12 05:04:51 PM PDT 24
Finished Jul 12 05:05:21 PM PDT 24
Peak memory 201724 kb
Host smart-db436ebc-2915-42f4-92c2-4a2232acbbbf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253711551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1253711551
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3751253227
Short name T190
Test name
Test status
Simulation time 331891791408 ps
CPU time 180.4 seconds
Started Jul 12 05:04:40 PM PDT 24
Finished Jul 12 05:07:42 PM PDT 24
Peak memory 201784 kb
Host smart-443366f6-7d90-4280-afac-1e4b92082543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751253227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3751253227
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1104242816
Short name T442
Test name
Test status
Simulation time 165887365851 ps
CPU time 62.57 seconds
Started Jul 12 05:04:38 PM PDT 24
Finished Jul 12 05:05:42 PM PDT 24
Peak memory 201864 kb
Host smart-bc6f9309-cee5-4508-a2ec-8bdb7e8a692e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104242816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1104242816
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.184864963
Short name T283
Test name
Test status
Simulation time 168850623706 ps
CPU time 181.46 seconds
Started Jul 12 05:04:41 PM PDT 24
Finished Jul 12 05:07:45 PM PDT 24
Peak memory 201796 kb
Host smart-040cbaeb-76e2-48ea-b7f1-4fb65ed41491
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184864963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.184864963
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.4194850041
Short name T635
Test name
Test status
Simulation time 201930813671 ps
CPU time 419.91 seconds
Started Jul 12 05:04:41 PM PDT 24
Finished Jul 12 05:11:42 PM PDT 24
Peak memory 201860 kb
Host smart-966c670d-d57c-43c1-bb82-c8a2a879982f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194850041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.4194850041
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2025410589
Short name T212
Test name
Test status
Simulation time 113813713284 ps
CPU time 371.28 seconds
Started Jul 12 05:04:48 PM PDT 24
Finished Jul 12 05:11:00 PM PDT 24
Peak memory 202112 kb
Host smart-d6364259-36ff-4291-b6d0-716862ef64dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025410589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2025410589
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1664871741
Short name T378
Test name
Test status
Simulation time 35817446416 ps
CPU time 86.34 seconds
Started Jul 12 05:04:40 PM PDT 24
Finished Jul 12 05:06:08 PM PDT 24
Peak memory 201700 kb
Host smart-7262757d-a4d0-40dd-9eb8-2b07732361a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664871741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1664871741
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1547374597
Short name T595
Test name
Test status
Simulation time 4259616190 ps
CPU time 9.78 seconds
Started Jul 12 05:04:46 PM PDT 24
Finished Jul 12 05:04:56 PM PDT 24
Peak memory 201772 kb
Host smart-18ddc4f0-9f27-4fbb-8b61-6e633a559935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547374597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1547374597
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.370312070
Short name T581
Test name
Test status
Simulation time 6229738024 ps
CPU time 15.13 seconds
Started Jul 12 05:04:47 PM PDT 24
Finished Jul 12 05:05:03 PM PDT 24
Peak memory 201592 kb
Host smart-6859dd2f-5800-4f13-aba3-77245a990557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370312070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.370312070
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.4242062315
Short name T471
Test name
Test status
Simulation time 53997965797 ps
CPU time 31.93 seconds
Started Jul 12 05:04:40 PM PDT 24
Finished Jul 12 05:05:14 PM PDT 24
Peak memory 201896 kb
Host smart-3a5bed1e-2906-4921-86c0-833ded58a19f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242062315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.4242062315
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2062379234
Short name T719
Test name
Test status
Simulation time 32499080808 ps
CPU time 35.08 seconds
Started Jul 12 05:04:40 PM PDT 24
Finished Jul 12 05:05:17 PM PDT 24
Peak memory 210560 kb
Host smart-e945c796-c991-43ce-88e7-1ee2c9d8ea91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062379234 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2062379234
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1467816830
Short name T392
Test name
Test status
Simulation time 426928510 ps
CPU time 0.87 seconds
Started Jul 12 05:04:45 PM PDT 24
Finished Jul 12 05:04:47 PM PDT 24
Peak memory 201644 kb
Host smart-6c0d54fe-d004-43c0-aed5-d1d3794338fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467816830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1467816830
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2023768477
Short name T647
Test name
Test status
Simulation time 188873942956 ps
CPU time 433.39 seconds
Started Jul 12 05:04:51 PM PDT 24
Finished Jul 12 05:12:07 PM PDT 24
Peak memory 201764 kb
Host smart-fa551107-eb7b-4f82-a5b2-89b1d22f5340
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023768477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2023768477
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2638335418
Short name T243
Test name
Test status
Simulation time 502436285107 ps
CPU time 1178.93 seconds
Started Jul 12 05:04:47 PM PDT 24
Finished Jul 12 05:24:26 PM PDT 24
Peak memory 201904 kb
Host smart-73ff5973-89cf-44a4-9322-2abc905260ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638335418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2638335418
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.727135188
Short name T240
Test name
Test status
Simulation time 165767082272 ps
CPU time 255.48 seconds
Started Jul 12 05:04:43 PM PDT 24
Finished Jul 12 05:08:59 PM PDT 24
Peak memory 201856 kb
Host smart-da12133b-fc33-42e3-ae4a-048aa4801884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727135188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.727135188
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2744673347
Short name T412
Test name
Test status
Simulation time 495266491504 ps
CPU time 1142.7 seconds
Started Jul 12 05:04:45 PM PDT 24
Finished Jul 12 05:23:48 PM PDT 24
Peak memory 201720 kb
Host smart-4871ea8f-819c-41a4-9641-2c0bd2807dd0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744673347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2744673347
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2719331145
Short name T160
Test name
Test status
Simulation time 328920085668 ps
CPU time 181.86 seconds
Started Jul 12 05:04:42 PM PDT 24
Finished Jul 12 05:07:46 PM PDT 24
Peak memory 201804 kb
Host smart-b6a22fd5-478d-4e0a-9fd6-132b15b67e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719331145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2719331145
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.325372952
Short name T386
Test name
Test status
Simulation time 163906974512 ps
CPU time 86.35 seconds
Started Jul 12 05:04:44 PM PDT 24
Finished Jul 12 05:06:12 PM PDT 24
Peak memory 201744 kb
Host smart-223a3fb8-95b8-4e76-83ac-e3cd7f080f7b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=325372952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.325372952
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3570744669
Short name T318
Test name
Test status
Simulation time 190603426188 ps
CPU time 102.73 seconds
Started Jul 12 05:04:44 PM PDT 24
Finished Jul 12 05:06:28 PM PDT 24
Peak memory 201972 kb
Host smart-842187bf-0527-4b35-944f-70ed66b1e865
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570744669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3570744669
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1351377527
Short name T373
Test name
Test status
Simulation time 403147445386 ps
CPU time 178.1 seconds
Started Jul 12 05:04:45 PM PDT 24
Finished Jul 12 05:07:44 PM PDT 24
Peak memory 201732 kb
Host smart-8b4e13d4-1edd-4665-afcc-acc79b3638c6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351377527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1351377527
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2719570637
Short name T49
Test name
Test status
Simulation time 126923801672 ps
CPU time 639.98 seconds
Started Jul 12 05:04:50 PM PDT 24
Finished Jul 12 05:15:32 PM PDT 24
Peak memory 202252 kb
Host smart-ab3baa5c-7440-40b2-8260-6740142312b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719570637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2719570637
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2823499745
Short name T495
Test name
Test status
Simulation time 26982338466 ps
CPU time 57.74 seconds
Started Jul 12 05:04:45 PM PDT 24
Finished Jul 12 05:05:44 PM PDT 24
Peak memory 201580 kb
Host smart-aa1ad30d-b814-4964-bdd0-672acc0e3d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823499745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2823499745
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.680389283
Short name T511
Test name
Test status
Simulation time 4858047730 ps
CPU time 3.82 seconds
Started Jul 12 05:04:46 PM PDT 24
Finished Jul 12 05:04:50 PM PDT 24
Peak memory 201688 kb
Host smart-1961f435-06a6-46ba-be74-27b65425da83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680389283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.680389283
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3574777283
Short name T518
Test name
Test status
Simulation time 5945072225 ps
CPU time 14.08 seconds
Started Jul 12 05:04:44 PM PDT 24
Finished Jul 12 05:04:59 PM PDT 24
Peak memory 201652 kb
Host smart-038ae7ad-3f60-4094-9261-9087c59b66ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574777283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3574777283
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1685358374
Short name T19
Test name
Test status
Simulation time 83765891050 ps
CPU time 71.54 seconds
Started Jul 12 05:04:49 PM PDT 24
Finished Jul 12 05:06:02 PM PDT 24
Peak memory 210608 kb
Host smart-9e4696f7-9b97-477c-9e60-5640d194373a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685358374 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.1685358374
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2679979503
Short name T485
Test name
Test status
Simulation time 347310654 ps
CPU time 0.8 seconds
Started Jul 12 05:04:50 PM PDT 24
Finished Jul 12 05:04:52 PM PDT 24
Peak memory 201608 kb
Host smart-db4e1bb4-e51e-4015-a7a7-77e13d9440a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679979503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2679979503
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2968889393
Short name T215
Test name
Test status
Simulation time 349617015224 ps
CPU time 454.11 seconds
Started Jul 12 05:04:46 PM PDT 24
Finished Jul 12 05:12:21 PM PDT 24
Peak memory 201744 kb
Host smart-f4b2ec97-f4da-4416-b58c-ab6dc26f7826
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968889393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2968889393
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1684257574
Short name T287
Test name
Test status
Simulation time 163582262526 ps
CPU time 388.26 seconds
Started Jul 12 05:04:47 PM PDT 24
Finished Jul 12 05:11:16 PM PDT 24
Peak memory 201980 kb
Host smart-17ecda8c-9915-4082-9a3d-8bdc3a150218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684257574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1684257574
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2860492483
Short name T456
Test name
Test status
Simulation time 162125031469 ps
CPU time 346.42 seconds
Started Jul 12 05:04:49 PM PDT 24
Finished Jul 12 05:10:36 PM PDT 24
Peak memory 201852 kb
Host smart-5416936b-5761-408d-bfdd-0d01c5e13c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860492483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2860492483
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.4162692210
Short name T787
Test name
Test status
Simulation time 474208405546 ps
CPU time 1058.85 seconds
Started Jul 12 05:04:46 PM PDT 24
Finished Jul 12 05:22:26 PM PDT 24
Peak memory 201972 kb
Host smart-dc5c0e2c-7f12-44b9-a3ff-e0246d65dd9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162692210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.4162692210
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.330206401
Short name T248
Test name
Test status
Simulation time 324977633616 ps
CPU time 211.87 seconds
Started Jul 12 05:04:46 PM PDT 24
Finished Jul 12 05:08:19 PM PDT 24
Peak memory 201872 kb
Host smart-c17184d5-8aeb-4954-80e4-16e69af368f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330206401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.330206401
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3357104327
Short name T142
Test name
Test status
Simulation time 495719220393 ps
CPU time 209.21 seconds
Started Jul 12 05:04:49 PM PDT 24
Finished Jul 12 05:08:20 PM PDT 24
Peak memory 201824 kb
Host smart-6a08cd1b-68e0-4e08-a5f7-678a2e8d53c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357104327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3357104327
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1192544798
Short name T232
Test name
Test status
Simulation time 398367402246 ps
CPU time 923.33 seconds
Started Jul 12 05:04:46 PM PDT 24
Finished Jul 12 05:20:11 PM PDT 24
Peak memory 201784 kb
Host smart-5d8e9b50-c1d2-4317-8ba0-948b8f1cc9b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192544798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1192544798
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3741121224
Short name T402
Test name
Test status
Simulation time 192510049121 ps
CPU time 91.62 seconds
Started Jul 12 05:04:46 PM PDT 24
Finished Jul 12 05:06:18 PM PDT 24
Peak memory 201736 kb
Host smart-f4be395f-34d8-43b9-b60b-2d1aba10a776
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741121224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3741121224
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.523551323
Short name T589
Test name
Test status
Simulation time 76683103603 ps
CPU time 267.71 seconds
Started Jul 12 05:04:52 PM PDT 24
Finished Jul 12 05:09:21 PM PDT 24
Peak memory 202096 kb
Host smart-178ea5a9-0623-46b0-925c-22cde264b238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523551323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.523551323
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1276236907
Short name T583
Test name
Test status
Simulation time 27555429805 ps
CPU time 17.21 seconds
Started Jul 12 05:04:44 PM PDT 24
Finished Jul 12 05:05:02 PM PDT 24
Peak memory 201592 kb
Host smart-e9ae1395-d429-4176-846c-c1392952a4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276236907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1276236907
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3632402482
Short name T582
Test name
Test status
Simulation time 4846124460 ps
CPU time 3.46 seconds
Started Jul 12 05:04:59 PM PDT 24
Finished Jul 12 05:05:03 PM PDT 24
Peak memory 201700 kb
Host smart-9e88220f-c931-4227-aa17-4b3f5d96f6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632402482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3632402482
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1451225949
Short name T567
Test name
Test status
Simulation time 5863559450 ps
CPU time 15.25 seconds
Started Jul 12 05:04:49 PM PDT 24
Finished Jul 12 05:05:06 PM PDT 24
Peak memory 201652 kb
Host smart-c19918d0-ca1a-4c6c-92c4-de32198975ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451225949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1451225949
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.30893177
Short name T753
Test name
Test status
Simulation time 356184696290 ps
CPU time 231.26 seconds
Started Jul 12 05:04:48 PM PDT 24
Finished Jul 12 05:08:40 PM PDT 24
Peak memory 201760 kb
Host smart-3fdc6134-8dc1-4038-85c1-3001d85e5eed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30893177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.30893177
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.346278964
Short name T17
Test name
Test status
Simulation time 121225538455 ps
CPU time 154.57 seconds
Started Jul 12 05:04:46 PM PDT 24
Finished Jul 12 05:07:21 PM PDT 24
Peak memory 210436 kb
Host smart-058210d9-9f9f-46c5-b395-80f8e6e9d1e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346278964 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.346278964
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.2567447975
Short name T584
Test name
Test status
Simulation time 504214124 ps
CPU time 1.26 seconds
Started Jul 12 05:04:11 PM PDT 24
Finished Jul 12 05:04:14 PM PDT 24
Peak memory 201640 kb
Host smart-db2df54a-e1cd-44d4-9027-485f4d932e8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567447975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2567447975
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2503805582
Short name T679
Test name
Test status
Simulation time 512525605625 ps
CPU time 300.69 seconds
Started Jul 12 05:04:11 PM PDT 24
Finished Jul 12 05:09:13 PM PDT 24
Peak memory 201884 kb
Host smart-c0bab320-974e-4c57-9508-0c9ea7fb88fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503805582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2503805582
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2176937193
Short name T678
Test name
Test status
Simulation time 490979959007 ps
CPU time 1048.25 seconds
Started Jul 12 05:04:06 PM PDT 24
Finished Jul 12 05:21:36 PM PDT 24
Peak memory 201856 kb
Host smart-4c8045d9-9e1a-44cd-baac-99d67e17a12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176937193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2176937193
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.248398647
Short name T777
Test name
Test status
Simulation time 324593078344 ps
CPU time 166.38 seconds
Started Jul 12 05:04:05 PM PDT 24
Finished Jul 12 05:06:53 PM PDT 24
Peak memory 202092 kb
Host smart-891a91bd-d5cc-4eac-ab35-d4ecae58cc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248398647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.248398647
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3970381562
Short name T26
Test name
Test status
Simulation time 325940652053 ps
CPU time 170.08 seconds
Started Jul 12 05:04:03 PM PDT 24
Finished Jul 12 05:06:56 PM PDT 24
Peak memory 202136 kb
Host smart-1f04d76b-81a2-4726-9673-a0366a0e598b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970381562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.3970381562
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.208265329
Short name T542
Test name
Test status
Simulation time 178992184857 ps
CPU time 106.2 seconds
Started Jul 12 05:04:09 PM PDT 24
Finished Jul 12 05:05:56 PM PDT 24
Peak memory 201880 kb
Host smart-d2c8c17b-745d-4249-ae0f-fe376da2f860
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208265329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.208265329
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.4009772528
Short name T516
Test name
Test status
Simulation time 589925153201 ps
CPU time 364.89 seconds
Started Jul 12 05:04:09 PM PDT 24
Finished Jul 12 05:10:15 PM PDT 24
Peak memory 201892 kb
Host smart-45ea9eda-e0ad-4756-8fae-f417401e9a69
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009772528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.4009772528
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3128430520
Short name T693
Test name
Test status
Simulation time 85336231385 ps
CPU time 321.27 seconds
Started Jul 12 05:04:06 PM PDT 24
Finished Jul 12 05:09:29 PM PDT 24
Peak memory 202268 kb
Host smart-f025eb3e-86f1-44e4-a397-7d1eca8e8395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128430520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3128430520
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3807291227
Short name T553
Test name
Test status
Simulation time 38850475567 ps
CPU time 25.53 seconds
Started Jul 12 05:04:09 PM PDT 24
Finished Jul 12 05:04:35 PM PDT 24
Peak memory 201700 kb
Host smart-2b70ead7-8f8e-4a86-ba3f-dd71dfcf300f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807291227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3807291227
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.1711670069
Short name T733
Test name
Test status
Simulation time 3639316927 ps
CPU time 5.14 seconds
Started Jul 12 05:04:08 PM PDT 24
Finished Jul 12 05:04:14 PM PDT 24
Peak memory 201716 kb
Host smart-a48cf408-4931-4d8f-bc6c-93a53649688d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711670069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1711670069
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.850013625
Short name T108
Test name
Test status
Simulation time 5695705426 ps
CPU time 7.59 seconds
Started Jul 12 05:04:01 PM PDT 24
Finished Jul 12 05:04:12 PM PDT 24
Peak memory 201692 kb
Host smart-2c11f28f-5a25-4cfd-b7a7-70db602d5575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850013625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.850013625
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.66126480
Short name T745
Test name
Test status
Simulation time 338140239140 ps
CPU time 384.4 seconds
Started Jul 12 05:15:05 PM PDT 24
Finished Jul 12 05:21:30 PM PDT 24
Peak memory 201780 kb
Host smart-300cd2dc-df48-4249-8583-d314edf5f9cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66126480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.66126480
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1566183695
Short name T58
Test name
Test status
Simulation time 89679097837 ps
CPU time 286.27 seconds
Started Jul 12 05:04:09 PM PDT 24
Finished Jul 12 05:08:56 PM PDT 24
Peak memory 211776 kb
Host smart-d4e3602d-5e59-48a8-8a72-e1347fdf267a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566183695 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1566183695
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2753001476
Short name T337
Test name
Test status
Simulation time 516671933 ps
CPU time 0.91 seconds
Started Jul 12 05:04:59 PM PDT 24
Finished Jul 12 05:05:01 PM PDT 24
Peak memory 201608 kb
Host smart-732e8b47-5f1a-407e-bf6f-077dd08eb715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753001476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2753001476
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3414209291
Short name T236
Test name
Test status
Simulation time 367448990463 ps
CPU time 751.49 seconds
Started Jul 12 05:04:52 PM PDT 24
Finished Jul 12 05:17:26 PM PDT 24
Peak memory 201904 kb
Host smart-4a1e7a22-b7f1-45d6-8bfe-fccb2854a83f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414209291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3414209291
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3478348216
Short name T792
Test name
Test status
Simulation time 188181398389 ps
CPU time 234.44 seconds
Started Jul 12 05:04:53 PM PDT 24
Finished Jul 12 05:08:49 PM PDT 24
Peak memory 201904 kb
Host smart-972867d8-590e-4c5a-9b54-6162e01869d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478348216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3478348216
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.90003698
Short name T77
Test name
Test status
Simulation time 167653884064 ps
CPU time 354.47 seconds
Started Jul 12 05:04:59 PM PDT 24
Finished Jul 12 05:10:54 PM PDT 24
Peak memory 201868 kb
Host smart-db20fe29-ca8a-4cfb-8b8c-e8069790887c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90003698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.90003698
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1924648076
Short name T448
Test name
Test status
Simulation time 319513335261 ps
CPU time 217.83 seconds
Started Jul 12 05:04:56 PM PDT 24
Finished Jul 12 05:08:34 PM PDT 24
Peak memory 201868 kb
Host smart-b3cb2597-9adf-4e47-ab79-9abd147fdafd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924648076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.1924648076
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2167830110
Short name T488
Test name
Test status
Simulation time 325176544392 ps
CPU time 699.75 seconds
Started Jul 12 05:04:50 PM PDT 24
Finished Jul 12 05:16:32 PM PDT 24
Peak memory 201856 kb
Host smart-97463bce-e5bb-4e13-9130-a8e3a5d51475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167830110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2167830110
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1735076424
Short name T399
Test name
Test status
Simulation time 168038292843 ps
CPU time 376.05 seconds
Started Jul 12 05:04:46 PM PDT 24
Finished Jul 12 05:11:03 PM PDT 24
Peak memory 201788 kb
Host smart-6c74e55c-837c-4fba-9c59-454296ab4c82
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735076424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1735076424
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2305378228
Short name T143
Test name
Test status
Simulation time 187674884847 ps
CPU time 103.07 seconds
Started Jul 12 05:04:53 PM PDT 24
Finished Jul 12 05:06:38 PM PDT 24
Peak memory 201924 kb
Host smart-a9b41c4d-42aa-4f26-b3e1-2bded77a84db
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305378228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2305378228
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1244675257
Short name T352
Test name
Test status
Simulation time 392685345460 ps
CPU time 432.74 seconds
Started Jul 12 05:04:52 PM PDT 24
Finished Jul 12 05:12:07 PM PDT 24
Peak memory 201800 kb
Host smart-0a0d5c06-fe8a-4bbd-b853-40ba72f61432
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244675257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1244675257
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2730770074
Short name T329
Test name
Test status
Simulation time 73383753618 ps
CPU time 438.34 seconds
Started Jul 12 05:04:55 PM PDT 24
Finished Jul 12 05:12:14 PM PDT 24
Peak memory 202192 kb
Host smart-38177763-c139-4c68-83e8-0dbbffb070b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730770074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2730770074
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2697310470
Short name T694
Test name
Test status
Simulation time 27484720046 ps
CPU time 60.41 seconds
Started Jul 12 05:04:53 PM PDT 24
Finished Jul 12 05:05:55 PM PDT 24
Peak memory 201700 kb
Host smart-6868df2a-1d00-43f7-8b6f-f7e9d98efcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697310470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2697310470
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1700112447
Short name T494
Test name
Test status
Simulation time 4003008842 ps
CPU time 2.86 seconds
Started Jul 12 05:04:52 PM PDT 24
Finished Jul 12 05:04:57 PM PDT 24
Peak memory 201668 kb
Host smart-dc2f44f8-cd7e-4f1d-963d-8c2ca6f32efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700112447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1700112447
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1844443045
Short name T648
Test name
Test status
Simulation time 5749081462 ps
CPU time 4.27 seconds
Started Jul 12 05:04:49 PM PDT 24
Finished Jul 12 05:04:55 PM PDT 24
Peak memory 201860 kb
Host smart-148179f2-8438-425d-ad98-677b0cadba0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844443045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1844443045
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3832319970
Short name T39
Test name
Test status
Simulation time 283153754059 ps
CPU time 54.36 seconds
Started Jul 12 05:05:21 PM PDT 24
Finished Jul 12 05:06:17 PM PDT 24
Peak memory 201976 kb
Host smart-4ab3f939-075d-4e77-89c7-2eb575e40196
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832319970 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.3832319970
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1941489423
Short name T663
Test name
Test status
Simulation time 322688019 ps
CPU time 0.8 seconds
Started Jul 12 05:05:08 PM PDT 24
Finished Jul 12 05:05:09 PM PDT 24
Peak memory 201512 kb
Host smart-df64a9c5-91c4-4dab-a8af-241dcf677012
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941489423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1941489423
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.3142976211
Short name T227
Test name
Test status
Simulation time 334071815573 ps
CPU time 289.68 seconds
Started Jul 12 05:05:00 PM PDT 24
Finished Jul 12 05:09:50 PM PDT 24
Peak memory 201796 kb
Host smart-6794de5f-64db-4fac-9080-0eee0b4d767d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142976211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.3142976211
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2733892886
Short name T186
Test name
Test status
Simulation time 390176172566 ps
CPU time 235.76 seconds
Started Jul 12 05:05:01 PM PDT 24
Finished Jul 12 05:08:57 PM PDT 24
Peak memory 201892 kb
Host smart-5a90b3ac-c6af-46b0-aae0-3626e01b5d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733892886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2733892886
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.248642045
Short name T193
Test name
Test status
Simulation time 485289389528 ps
CPU time 290.93 seconds
Started Jul 12 05:04:55 PM PDT 24
Finished Jul 12 05:09:47 PM PDT 24
Peak memory 202092 kb
Host smart-7067042b-1c4f-4d48-aef1-80529d13a99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248642045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.248642045
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1039495192
Short name T697
Test name
Test status
Simulation time 164323976455 ps
CPU time 386.27 seconds
Started Jul 12 05:05:03 PM PDT 24
Finished Jul 12 05:11:30 PM PDT 24
Peak memory 201752 kb
Host smart-3e0f06aa-ecde-458c-82ae-2de27907ba37
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039495192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1039495192
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1461724474
Short name T660
Test name
Test status
Simulation time 163671526029 ps
CPU time 38.04 seconds
Started Jul 12 05:04:53 PM PDT 24
Finished Jul 12 05:05:33 PM PDT 24
Peak memory 201956 kb
Host smart-f1726b02-0b84-445b-9dc0-11467b7c2e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461724474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1461724474
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2352326935
Short name T457
Test name
Test status
Simulation time 495165944818 ps
CPU time 997.15 seconds
Started Jul 12 05:05:02 PM PDT 24
Finished Jul 12 05:21:40 PM PDT 24
Peak memory 201740 kb
Host smart-652cb457-fbdb-4478-8a3c-04ef87ca9408
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352326935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2352326935
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2395155567
Short name T729
Test name
Test status
Simulation time 171423559942 ps
CPU time 207.73 seconds
Started Jul 12 05:05:02 PM PDT 24
Finished Jul 12 05:08:30 PM PDT 24
Peak memory 201920 kb
Host smart-e5237033-dce8-4ab3-9d90-5637adcabb86
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395155567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2395155567
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3507962103
Short name T774
Test name
Test status
Simulation time 610729437645 ps
CPU time 394.02 seconds
Started Jul 12 05:05:01 PM PDT 24
Finished Jul 12 05:11:36 PM PDT 24
Peak memory 201880 kb
Host smart-dc5f12ce-486a-415b-836f-6c93a06afbf5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507962103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3507962103
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1371973339
Short name T331
Test name
Test status
Simulation time 95086861649 ps
CPU time 355.2 seconds
Started Jul 12 05:05:01 PM PDT 24
Finished Jul 12 05:10:56 PM PDT 24
Peak memory 202436 kb
Host smart-6785229d-2869-4851-ae00-49c645c1daca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371973339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1371973339
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.4132826600
Short name T637
Test name
Test status
Simulation time 36320083761 ps
CPU time 76.08 seconds
Started Jul 12 05:05:02 PM PDT 24
Finished Jul 12 05:06:19 PM PDT 24
Peak memory 201656 kb
Host smart-afea4a80-4504-451e-85cd-a88f0c2b6823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132826600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.4132826600
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1275673092
Short name T627
Test name
Test status
Simulation time 3570375027 ps
CPU time 8.29 seconds
Started Jul 12 05:05:02 PM PDT 24
Finished Jul 12 05:05:11 PM PDT 24
Peak memory 201656 kb
Host smart-0ef1d883-61e4-41d3-a8da-d252c6df7a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275673092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1275673092
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1258782183
Short name T355
Test name
Test status
Simulation time 5828698976 ps
CPU time 6.91 seconds
Started Jul 12 05:04:54 PM PDT 24
Finished Jul 12 05:05:02 PM PDT 24
Peak memory 201472 kb
Host smart-55db1937-c005-4429-9c2e-af064397a103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258782183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1258782183
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3016713734
Short name T82
Test name
Test status
Simulation time 1278696960809 ps
CPU time 1046.63 seconds
Started Jul 12 05:05:02 PM PDT 24
Finished Jul 12 05:22:29 PM PDT 24
Peak memory 210564 kb
Host smart-9fb46114-cd18-4113-93c8-540cedb6a4b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016713734 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3016713734
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.2046062647
Short name T338
Test name
Test status
Simulation time 322352879 ps
CPU time 0.71 seconds
Started Jul 12 05:05:09 PM PDT 24
Finished Jul 12 05:05:10 PM PDT 24
Peak memory 201492 kb
Host smart-84a1bee8-a520-4bdf-84d7-b380b8b270dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046062647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2046062647
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.4223158295
Short name T293
Test name
Test status
Simulation time 188636488340 ps
CPU time 191.05 seconds
Started Jul 12 05:05:03 PM PDT 24
Finished Jul 12 05:08:14 PM PDT 24
Peak memory 201948 kb
Host smart-433159f0-b160-4bd0-b7fd-5c156a96c768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223158295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.4223158295
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2200992062
Short name T716
Test name
Test status
Simulation time 323934146969 ps
CPU time 202.14 seconds
Started Jul 12 05:05:03 PM PDT 24
Finished Jul 12 05:08:26 PM PDT 24
Peak memory 201864 kb
Host smart-85659eb6-c924-4f53-a812-24bacd15d20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200992062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2200992062
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1583519495
Short name T197
Test name
Test status
Simulation time 164280861778 ps
CPU time 93.13 seconds
Started Jul 12 05:05:06 PM PDT 24
Finished Jul 12 05:06:39 PM PDT 24
Peak memory 201824 kb
Host smart-3eb04921-3ffa-43e8-8307-7a97cbc96c44
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583519495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1583519495
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3039141844
Short name T320
Test name
Test status
Simulation time 496270180910 ps
CPU time 550.79 seconds
Started Jul 12 05:05:01 PM PDT 24
Finished Jul 12 05:14:12 PM PDT 24
Peak memory 201908 kb
Host smart-473fda34-72d3-478b-9fdf-c8477c63251e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039141844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3039141844
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1430577187
Short name T548
Test name
Test status
Simulation time 496288824055 ps
CPU time 114.48 seconds
Started Jul 12 05:05:00 PM PDT 24
Finished Jul 12 05:06:55 PM PDT 24
Peak memory 201960 kb
Host smart-5a6d2f6b-3ff1-403d-aba2-201cccda0692
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430577187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1430577187
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2254490731
Short name T610
Test name
Test status
Simulation time 357886417598 ps
CPU time 216.65 seconds
Started Jul 12 05:05:03 PM PDT 24
Finished Jul 12 05:08:40 PM PDT 24
Peak memory 201844 kb
Host smart-c9f2b4f5-2487-419d-8413-e91552fa03b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254490731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2254490731
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2755692988
Short name T674
Test name
Test status
Simulation time 400483428409 ps
CPU time 968.18 seconds
Started Jul 12 05:05:00 PM PDT 24
Finished Jul 12 05:21:08 PM PDT 24
Peak memory 201876 kb
Host smart-77e4409f-a8ff-4a31-9759-6a55dcdc8e74
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755692988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2755692988
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2754448064
Short name T701
Test name
Test status
Simulation time 87837120631 ps
CPU time 308.13 seconds
Started Jul 12 05:05:07 PM PDT 24
Finished Jul 12 05:10:16 PM PDT 24
Peak memory 202120 kb
Host smart-183b21a8-7daf-4aba-895e-40de3d3305db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754448064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2754448064
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1254273359
Short name T168
Test name
Test status
Simulation time 29951517466 ps
CPU time 64.46 seconds
Started Jul 12 05:05:09 PM PDT 24
Finished Jul 12 05:06:15 PM PDT 24
Peak memory 201700 kb
Host smart-b0dbd87e-94f1-42b6-8c07-d3896bbf2ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254273359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1254273359
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.422982418
Short name T437
Test name
Test status
Simulation time 4890877702 ps
CPU time 6.13 seconds
Started Jul 12 05:05:09 PM PDT 24
Finished Jul 12 05:05:16 PM PDT 24
Peak memory 201712 kb
Host smart-7b2a1f85-d1f4-447e-9092-289c7892b252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422982418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.422982418
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1573239589
Short name T342
Test name
Test status
Simulation time 5714677385 ps
CPU time 4.17 seconds
Started Jul 12 05:05:05 PM PDT 24
Finished Jul 12 05:05:10 PM PDT 24
Peak memory 201700 kb
Host smart-dcf0f9c3-03b4-41a3-ba9f-85bf2416d67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573239589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1573239589
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.1843709460
Short name T315
Test name
Test status
Simulation time 168432627948 ps
CPU time 62.85 seconds
Started Jul 12 05:05:11 PM PDT 24
Finished Jul 12 05:06:14 PM PDT 24
Peak memory 201736 kb
Host smart-baf3ac04-93a5-44d7-9106-4aa7d843a316
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843709460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.1843709460
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.157950031
Short name T775
Test name
Test status
Simulation time 392589423 ps
CPU time 1.06 seconds
Started Jul 12 05:05:16 PM PDT 24
Finished Jul 12 05:05:17 PM PDT 24
Peak memory 201604 kb
Host smart-bd0ee509-c27c-4ba3-a484-582ff4d37ad5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157950031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.157950031
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3765522292
Short name T796
Test name
Test status
Simulation time 168662175916 ps
CPU time 128.55 seconds
Started Jul 12 05:05:09 PM PDT 24
Finished Jul 12 05:07:18 PM PDT 24
Peak memory 201720 kb
Host smart-cf1bd0db-b14b-47e1-b1a9-2f84fab68602
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765522292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3765522292
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.4176627043
Short name T688
Test name
Test status
Simulation time 160267801751 ps
CPU time 186.25 seconds
Started Jul 12 05:05:12 PM PDT 24
Finished Jul 12 05:08:19 PM PDT 24
Peak memory 201956 kb
Host smart-37022208-9191-4519-bd36-fddc4f3d10a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176627043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.4176627043
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.60891142
Short name T179
Test name
Test status
Simulation time 334146681829 ps
CPU time 167.65 seconds
Started Jul 12 05:05:11 PM PDT 24
Finished Jul 12 05:07:59 PM PDT 24
Peak memory 201728 kb
Host smart-36e5fecf-2d14-4799-a981-4082384b5a9a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=60891142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt
_fixed.60891142
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3691442924
Short name T490
Test name
Test status
Simulation time 322708451533 ps
CPU time 186.67 seconds
Started Jul 12 05:05:08 PM PDT 24
Finished Jul 12 05:08:15 PM PDT 24
Peak memory 201864 kb
Host smart-b17aa259-8a31-4d10-9758-8fb7afa4c7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691442924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3691442924
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2858085980
Short name T746
Test name
Test status
Simulation time 321337675065 ps
CPU time 227.36 seconds
Started Jul 12 05:05:12 PM PDT 24
Finished Jul 12 05:08:59 PM PDT 24
Peak memory 201728 kb
Host smart-3230efcc-12da-4d3f-9976-6f27b506c292
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858085980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2858085980
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1275744908
Short name T171
Test name
Test status
Simulation time 369181667888 ps
CPU time 209.46 seconds
Started Jul 12 05:05:10 PM PDT 24
Finished Jul 12 05:08:41 PM PDT 24
Peak memory 201772 kb
Host smart-bf77cf7d-6278-475c-aa59-6e955d48e629
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275744908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1275744908
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2428664808
Short name T705
Test name
Test status
Simulation time 208819805615 ps
CPU time 488.98 seconds
Started Jul 12 05:05:09 PM PDT 24
Finished Jul 12 05:13:19 PM PDT 24
Peak memory 201796 kb
Host smart-97345ed7-448c-4b9e-a708-c1b62daddce1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428664808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.2428664808
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.441387785
Short name T336
Test name
Test status
Simulation time 95632992652 ps
CPU time 385.09 seconds
Started Jul 12 05:05:15 PM PDT 24
Finished Jul 12 05:11:40 PM PDT 24
Peak memory 202212 kb
Host smart-648ae480-aece-48ae-b6bd-a2b9dadf12c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441387785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.441387785
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2472668925
Short name T778
Test name
Test status
Simulation time 37636185293 ps
CPU time 19.15 seconds
Started Jul 12 05:05:14 PM PDT 24
Finished Jul 12 05:05:34 PM PDT 24
Peak memory 201584 kb
Host smart-21739a3b-42fc-4299-b274-904d6e02d784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472668925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2472668925
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3723733012
Short name T779
Test name
Test status
Simulation time 5047277144 ps
CPU time 3.48 seconds
Started Jul 12 05:05:12 PM PDT 24
Finished Jul 12 05:05:16 PM PDT 24
Peak memory 201644 kb
Host smart-2f9fdd6a-a3ea-4f86-9f80-0c2dc3f72109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723733012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3723733012
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.367197869
Short name T470
Test name
Test status
Simulation time 5576986013 ps
CPU time 5.85 seconds
Started Jul 12 05:05:10 PM PDT 24
Finished Jul 12 05:05:17 PM PDT 24
Peak memory 201608 kb
Host smart-6d8086af-f894-4efb-a730-292f09a3c342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367197869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.367197869
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2543283234
Short name T195
Test name
Test status
Simulation time 171261070230 ps
CPU time 364.64 seconds
Started Jul 12 05:05:15 PM PDT 24
Finished Jul 12 05:11:20 PM PDT 24
Peak memory 201852 kb
Host smart-052768b5-b331-4981-b120-c9503b54a42a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543283234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2543283234
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1024527196
Short name T744
Test name
Test status
Simulation time 458326292 ps
CPU time 1.59 seconds
Started Jul 12 05:05:20 PM PDT 24
Finished Jul 12 05:05:22 PM PDT 24
Peak memory 201652 kb
Host smart-9bffea2e-c447-4130-beae-ad4cfca3cc5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024527196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1024527196
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.68684122
Short name T732
Test name
Test status
Simulation time 172428889288 ps
CPU time 188.76 seconds
Started Jul 12 05:05:21 PM PDT 24
Finished Jul 12 05:08:30 PM PDT 24
Peak memory 201872 kb
Host smart-c311f9f7-fb98-43a9-ae70-de45d1379076
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68684122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gatin
g.68684122
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2385431430
Short name T704
Test name
Test status
Simulation time 332686209200 ps
CPU time 388.96 seconds
Started Jul 12 05:05:22 PM PDT 24
Finished Jul 12 05:11:51 PM PDT 24
Peak memory 201884 kb
Host smart-73d844c6-81cd-4877-b9e8-e4d866e17eb2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385431430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2385431430
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3238401180
Short name T12
Test name
Test status
Simulation time 326260369722 ps
CPU time 774 seconds
Started Jul 12 05:05:16 PM PDT 24
Finished Jul 12 05:18:11 PM PDT 24
Peak memory 201880 kb
Host smart-eadc67d1-7357-436c-a865-998a0aceca4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238401180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3238401180
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1579794079
Short name T629
Test name
Test status
Simulation time 334324594005 ps
CPU time 794.03 seconds
Started Jul 12 05:05:14 PM PDT 24
Finished Jul 12 05:18:29 PM PDT 24
Peak memory 201860 kb
Host smart-65a5bc48-9d32-4679-b40c-aca5a7c13d03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579794079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1579794079
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1496427708
Short name T773
Test name
Test status
Simulation time 410680087853 ps
CPU time 500.94 seconds
Started Jul 12 05:05:21 PM PDT 24
Finished Jul 12 05:13:43 PM PDT 24
Peak memory 201780 kb
Host smart-e8049d6b-cbab-4a68-b538-b49dc41798b5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496427708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1496427708
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2604849852
Short name T569
Test name
Test status
Simulation time 74005136801 ps
CPU time 238.75 seconds
Started Jul 12 05:05:25 PM PDT 24
Finished Jul 12 05:09:25 PM PDT 24
Peak memory 202280 kb
Host smart-860d04b5-bcb1-473e-b255-fccc7b3b9ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604849852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2604849852
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.876614246
Short name T359
Test name
Test status
Simulation time 44966013990 ps
CPU time 26 seconds
Started Jul 12 05:05:22 PM PDT 24
Finished Jul 12 05:05:48 PM PDT 24
Peak memory 201560 kb
Host smart-ff419856-cab7-40bc-9614-b946cec7dd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876614246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.876614246
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.874399843
Short name T464
Test name
Test status
Simulation time 4902679108 ps
CPU time 3.27 seconds
Started Jul 12 05:05:25 PM PDT 24
Finished Jul 12 05:05:29 PM PDT 24
Peak memory 201696 kb
Host smart-7639cd0f-ba4c-4775-aa2c-4c090a0b9927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874399843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.874399843
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3555971564
Short name T371
Test name
Test status
Simulation time 6006602374 ps
CPU time 1.61 seconds
Started Jul 12 05:05:13 PM PDT 24
Finished Jul 12 05:05:16 PM PDT 24
Peak memory 201712 kb
Host smart-ae331b76-0e66-4b38-8cd9-c4fd9fbe6c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555971564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3555971564
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.4131269069
Short name T681
Test name
Test status
Simulation time 420844097695 ps
CPU time 508.85 seconds
Started Jul 12 05:05:25 PM PDT 24
Finished Jul 12 05:13:54 PM PDT 24
Peak memory 202260 kb
Host smart-c07b2ad1-57a5-4e6a-a30d-4d7b57c3e1d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131269069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.4131269069
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3174757497
Short name T102
Test name
Test status
Simulation time 165937941720 ps
CPU time 228.41 seconds
Started Jul 12 05:05:20 PM PDT 24
Finished Jul 12 05:09:09 PM PDT 24
Peak memory 218468 kb
Host smart-dfa11a9a-3acd-4ef4-bed1-b4c517a87a71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174757497 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3174757497
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1788351491
Short name T561
Test name
Test status
Simulation time 320818722 ps
CPU time 1.32 seconds
Started Jul 12 05:05:28 PM PDT 24
Finished Jul 12 05:05:29 PM PDT 24
Peak memory 201508 kb
Host smart-e33fdc7d-49b8-4463-90ca-f9c700e5290f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788351491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1788351491
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3572423887
Short name T235
Test name
Test status
Simulation time 327151060857 ps
CPU time 177.83 seconds
Started Jul 12 05:05:21 PM PDT 24
Finished Jul 12 05:08:19 PM PDT 24
Peak memory 201900 kb
Host smart-5afcc81c-240a-4056-8c33-1e4d14db1595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572423887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3572423887
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.204735671
Short name T101
Test name
Test status
Simulation time 164675531794 ps
CPU time 399.63 seconds
Started Jul 12 05:05:21 PM PDT 24
Finished Jul 12 05:12:02 PM PDT 24
Peak memory 201776 kb
Host smart-8503a305-a55d-4479-9de4-ab6328dbd41b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=204735671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrup
t_fixed.204735671
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3103093595
Short name T285
Test name
Test status
Simulation time 330883348278 ps
CPU time 396.13 seconds
Started Jul 12 05:05:22 PM PDT 24
Finished Jul 12 05:11:59 PM PDT 24
Peak memory 201888 kb
Host smart-037d96aa-1739-4f34-b530-0609590e5960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103093595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3103093595
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.2191459458
Short name T423
Test name
Test status
Simulation time 324379581635 ps
CPU time 58.95 seconds
Started Jul 12 05:05:21 PM PDT 24
Finished Jul 12 05:06:21 PM PDT 24
Peak memory 201868 kb
Host smart-55e0b576-c287-4ffc-a7b0-7d04d9de8f68
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191459458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.2191459458
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.4021890642
Short name T304
Test name
Test status
Simulation time 171931044562 ps
CPU time 361 seconds
Started Jul 12 05:05:21 PM PDT 24
Finished Jul 12 05:11:23 PM PDT 24
Peak memory 201956 kb
Host smart-64ab1741-d4f0-4ea9-8628-d20faa2dbb65
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021890642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.4021890642
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2954359659
Short name T682
Test name
Test status
Simulation time 403954633817 ps
CPU time 849.04 seconds
Started Jul 12 05:05:23 PM PDT 24
Finished Jul 12 05:19:33 PM PDT 24
Peak memory 201836 kb
Host smart-77e714e2-1801-4b8f-8972-661d2b5193cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954359659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2954359659
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.3924048409
Short name T735
Test name
Test status
Simulation time 70545677186 ps
CPU time 272.61 seconds
Started Jul 12 05:05:28 PM PDT 24
Finished Jul 12 05:10:01 PM PDT 24
Peak memory 202232 kb
Host smart-4294543b-be9e-4897-ac14-45173f5cf3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924048409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.3924048409
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.853650448
Short name T486
Test name
Test status
Simulation time 37652496769 ps
CPU time 84.35 seconds
Started Jul 12 05:05:28 PM PDT 24
Finished Jul 12 05:06:53 PM PDT 24
Peak memory 201692 kb
Host smart-d9fd4f77-4c26-4205-bc07-4792d153ef88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853650448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.853650448
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.89008863
Short name T794
Test name
Test status
Simulation time 4011191706 ps
CPU time 9.9 seconds
Started Jul 12 05:05:30 PM PDT 24
Finished Jul 12 05:05:40 PM PDT 24
Peak memory 201724 kb
Host smart-a135ee79-38b1-426e-8208-3be6fbecad76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89008863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.89008863
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.102356063
Short name T432
Test name
Test status
Simulation time 6000130270 ps
CPU time 14.23 seconds
Started Jul 12 05:05:20 PM PDT 24
Finished Jul 12 05:05:35 PM PDT 24
Peak memory 201668 kb
Host smart-3b516fad-7e37-4302-a453-ab62d101231e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102356063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.102356063
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1660358854
Short name T35
Test name
Test status
Simulation time 462627928257 ps
CPU time 1350.43 seconds
Started Jul 12 05:05:29 PM PDT 24
Finished Jul 12 05:28:00 PM PDT 24
Peak memory 202244 kb
Host smart-183f8f8c-073b-4ed3-9871-8ae762499544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660358854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1660358854
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1019109723
Short name T763
Test name
Test status
Simulation time 35357170135 ps
CPU time 88.2 seconds
Started Jul 12 05:05:30 PM PDT 24
Finished Jul 12 05:06:59 PM PDT 24
Peak memory 218232 kb
Host smart-bbbe3527-8c0d-4cc5-bc4a-5e52d4b6de98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019109723 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1019109723
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.740607696
Short name T692
Test name
Test status
Simulation time 323699477 ps
CPU time 0.77 seconds
Started Jul 12 05:05:47 PM PDT 24
Finished Jul 12 05:05:48 PM PDT 24
Peak memory 201656 kb
Host smart-6a16b5ef-15f1-4a0c-96c9-8d565d088a0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740607696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.740607696
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3396985576
Short name T672
Test name
Test status
Simulation time 327144010590 ps
CPU time 628.1 seconds
Started Jul 12 05:05:37 PM PDT 24
Finished Jul 12 05:16:06 PM PDT 24
Peak memory 201864 kb
Host smart-8803586b-b7ed-4f8a-a374-ccee72a414f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396985576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3396985576
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1378522980
Short name T247
Test name
Test status
Simulation time 490732712375 ps
CPU time 935.57 seconds
Started Jul 12 05:05:36 PM PDT 24
Finished Jul 12 05:21:12 PM PDT 24
Peak memory 201928 kb
Host smart-633256b4-1fea-43d3-863d-6e33f262a439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378522980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1378522980
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.462899166
Short name T780
Test name
Test status
Simulation time 496284408890 ps
CPU time 1119.36 seconds
Started Jul 12 05:05:34 PM PDT 24
Finished Jul 12 05:24:14 PM PDT 24
Peak memory 201836 kb
Host smart-3442292e-f6c1-4274-8c75-6a93bb46cf13
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=462899166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.462899166
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.188556197
Short name T107
Test name
Test status
Simulation time 492159535263 ps
CPU time 548.84 seconds
Started Jul 12 05:05:30 PM PDT 24
Finished Jul 12 05:14:40 PM PDT 24
Peak memory 201908 kb
Host smart-46515898-6427-4fa6-9aab-0dcc97cca108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188556197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.188556197
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.293124653
Short name T587
Test name
Test status
Simulation time 329026465199 ps
CPU time 782.15 seconds
Started Jul 12 05:05:37 PM PDT 24
Finished Jul 12 05:18:40 PM PDT 24
Peak memory 201936 kb
Host smart-077d15b4-8c87-4fee-8fb3-0efd04681034
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=293124653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixe
d.293124653
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.865558488
Short name T317
Test name
Test status
Simulation time 378787690488 ps
CPU time 857.15 seconds
Started Jul 12 05:05:38 PM PDT 24
Finished Jul 12 05:19:55 PM PDT 24
Peak memory 201784 kb
Host smart-706bc681-2834-4c0f-ad86-7ffa9eaf775c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865558488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_
wakeup.865558488
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.4046464063
Short name T369
Test name
Test status
Simulation time 407602580697 ps
CPU time 977.02 seconds
Started Jul 12 05:05:33 PM PDT 24
Finished Jul 12 05:21:51 PM PDT 24
Peak memory 201876 kb
Host smart-67007720-ee7d-4bd1-bfb1-1e7404caedb9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046464063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.4046464063
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.623427299
Short name T205
Test name
Test status
Simulation time 66882872442 ps
CPU time 371.68 seconds
Started Jul 12 05:05:35 PM PDT 24
Finished Jul 12 05:11:48 PM PDT 24
Peak memory 202120 kb
Host smart-89e5969f-912c-4381-8114-d097f9784d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623427299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.623427299
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.578070755
Short name T346
Test name
Test status
Simulation time 37463653181 ps
CPU time 22.03 seconds
Started Jul 12 05:05:36 PM PDT 24
Finished Jul 12 05:05:58 PM PDT 24
Peak memory 201560 kb
Host smart-12752b0f-727c-453f-a21a-0f43319176ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578070755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.578070755
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.4126992983
Short name T6
Test name
Test status
Simulation time 4268143473 ps
CPU time 3.26 seconds
Started Jul 12 05:05:37 PM PDT 24
Finished Jul 12 05:05:41 PM PDT 24
Peak memory 201576 kb
Host smart-b4c444ee-04c8-4208-8c21-c511b02cbfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126992983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.4126992983
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1457846134
Short name T724
Test name
Test status
Simulation time 5850383607 ps
CPU time 14.89 seconds
Started Jul 12 05:05:28 PM PDT 24
Finished Jul 12 05:05:43 PM PDT 24
Peak memory 201720 kb
Host smart-de4ef0ae-7f73-44f0-8c06-7538f19de973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457846134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1457846134
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2604431374
Short name T675
Test name
Test status
Simulation time 180544366129 ps
CPU time 86.54 seconds
Started Jul 12 05:05:43 PM PDT 24
Finished Jul 12 05:07:10 PM PDT 24
Peak memory 201880 kb
Host smart-93a558f1-8234-437e-add1-eebc98dd10d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604431374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2604431374
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2054060921
Short name T98
Test name
Test status
Simulation time 314470036396 ps
CPU time 131.09 seconds
Started Jul 12 05:05:42 PM PDT 24
Finished Jul 12 05:07:54 PM PDT 24
Peak memory 210112 kb
Host smart-64050b1c-4fe5-4f33-91d0-466d77fb9259
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054060921 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2054060921
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2913238358
Short name T424
Test name
Test status
Simulation time 533363774 ps
CPU time 1.49 seconds
Started Jul 12 05:05:51 PM PDT 24
Finished Jul 12 05:05:54 PM PDT 24
Peak memory 201652 kb
Host smart-bbea54ec-505e-4e10-a50d-e241c1737155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913238358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2913238358
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.4035183165
Short name T603
Test name
Test status
Simulation time 323269486597 ps
CPU time 665.11 seconds
Started Jul 12 05:05:42 PM PDT 24
Finished Jul 12 05:16:48 PM PDT 24
Peak memory 201932 kb
Host smart-a58c8b27-e0c5-439c-a001-85a9d9ffd92f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035183165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.4035183165
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3697724829
Short name T549
Test name
Test status
Simulation time 319444047741 ps
CPU time 56.71 seconds
Started Jul 12 05:05:43 PM PDT 24
Finished Jul 12 05:06:40 PM PDT 24
Peak memory 201852 kb
Host smart-3a4715c3-6085-4411-abcb-6ec05026aba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697724829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3697724829
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.27161758
Short name T722
Test name
Test status
Simulation time 326930433798 ps
CPU time 712.08 seconds
Started Jul 12 05:05:43 PM PDT 24
Finished Jul 12 05:17:36 PM PDT 24
Peak memory 202028 kb
Host smart-802c7539-b89b-4ae3-83be-b456b4ff504f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27161758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.27161758
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3295901524
Short name T683
Test name
Test status
Simulation time 499533908018 ps
CPU time 187.95 seconds
Started Jul 12 05:05:48 PM PDT 24
Finished Jul 12 05:08:56 PM PDT 24
Peak memory 201880 kb
Host smart-b6c17c93-4d42-4645-9bf8-dd41f43e4624
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295901524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3295901524
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3886013356
Short name T565
Test name
Test status
Simulation time 160364647335 ps
CPU time 382.68 seconds
Started Jul 12 05:05:42 PM PDT 24
Finished Jul 12 05:12:06 PM PDT 24
Peak memory 201848 kb
Host smart-484f5b22-c8a5-46eb-bebb-6bf059b30244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886013356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3886013356
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1922651686
Short name T559
Test name
Test status
Simulation time 491626022695 ps
CPU time 253.44 seconds
Started Jul 12 05:05:41 PM PDT 24
Finished Jul 12 05:09:56 PM PDT 24
Peak memory 201868 kb
Host smart-a577be63-acbb-4e95-b2c0-7ac59bf528bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922651686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1922651686
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3433654979
Short name T278
Test name
Test status
Simulation time 647046674167 ps
CPU time 308.1 seconds
Started Jul 12 05:05:47 PM PDT 24
Finished Jul 12 05:10:56 PM PDT 24
Peak memory 201912 kb
Host smart-988e19da-512e-4fae-bd48-cd5d0772df64
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433654979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3433654979
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3234522969
Short name T372
Test name
Test status
Simulation time 197453634001 ps
CPU time 128.59 seconds
Started Jul 12 05:05:43 PM PDT 24
Finished Jul 12 05:07:53 PM PDT 24
Peak memory 201876 kb
Host smart-2fd81e8f-7b71-43d0-a5c8-b8a9dff2f6c4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234522969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.3234522969
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1511424539
Short name T726
Test name
Test status
Simulation time 27133826481 ps
CPU time 56.9 seconds
Started Jul 12 05:05:51 PM PDT 24
Finished Jul 12 05:06:49 PM PDT 24
Peak memory 201896 kb
Host smart-c34342a6-ffff-4aee-a9dd-131ccb278fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511424539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1511424539
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.35446260
Short name T460
Test name
Test status
Simulation time 4902381172 ps
CPU time 3.2 seconds
Started Jul 12 05:05:52 PM PDT 24
Finished Jul 12 05:05:55 PM PDT 24
Peak memory 201600 kb
Host smart-b6f23aff-117d-4f41-87dc-21ef9f1f511c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35446260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.35446260
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.482882925
Short name T498
Test name
Test status
Simulation time 5940890200 ps
CPU time 4.28 seconds
Started Jul 12 05:05:48 PM PDT 24
Finished Jul 12 05:05:52 PM PDT 24
Peak memory 201708 kb
Host smart-583aed03-455e-4344-b2ca-0b243379761d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482882925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.482882925
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.428915081
Short name T38
Test name
Test status
Simulation time 48672973761 ps
CPU time 67.21 seconds
Started Jul 12 05:05:50 PM PDT 24
Finished Jul 12 05:06:57 PM PDT 24
Peak memory 218756 kb
Host smart-e1f16b88-915f-4db3-b4f9-27a481ed3735
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428915081 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.428915081
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3480281937
Short name T395
Test name
Test status
Simulation time 493892236 ps
CPU time 0.91 seconds
Started Jul 12 05:05:58 PM PDT 24
Finished Jul 12 05:05:59 PM PDT 24
Peak memory 201624 kb
Host smart-2b09ace3-8998-457c-88ff-3753886615e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480281937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3480281937
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.2475423253
Short name T526
Test name
Test status
Simulation time 496772778700 ps
CPU time 1178.49 seconds
Started Jul 12 05:05:59 PM PDT 24
Finished Jul 12 05:25:38 PM PDT 24
Peak memory 201764 kb
Host smart-b3543f67-cd57-4cbe-a0dc-46eeb62268f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475423253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2475423253
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.3012433112
Short name T764
Test name
Test status
Simulation time 158857689775 ps
CPU time 90.95 seconds
Started Jul 12 05:05:51 PM PDT 24
Finished Jul 12 05:07:22 PM PDT 24
Peak memory 201896 kb
Host smart-c5bf709c-ead8-4fe7-a40d-c1eaf23a22e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012433112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3012433112
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3094387103
Short name T580
Test name
Test status
Simulation time 333483707651 ps
CPU time 366.37 seconds
Started Jul 12 05:05:49 PM PDT 24
Finished Jul 12 05:11:56 PM PDT 24
Peak memory 201864 kb
Host smart-dc79ee86-17ec-4795-832e-3aa230e46a9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094387103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3094387103
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2464492093
Short name T253
Test name
Test status
Simulation time 330336782947 ps
CPU time 81.32 seconds
Started Jul 12 05:05:49 PM PDT 24
Finished Jul 12 05:07:11 PM PDT 24
Peak memory 201860 kb
Host smart-d18809e7-80b4-4718-9b18-2f5b6ad3f465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464492093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2464492093
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.79367526
Short name T468
Test name
Test status
Simulation time 492507919085 ps
CPU time 508.89 seconds
Started Jul 12 05:05:51 PM PDT 24
Finished Jul 12 05:14:20 PM PDT 24
Peak memory 201848 kb
Host smart-384daf70-fdeb-4beb-9906-87c4edf0fc50
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=79367526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixed
.79367526
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2292055251
Short name T755
Test name
Test status
Simulation time 556952192367 ps
CPU time 559.05 seconds
Started Jul 12 05:05:53 PM PDT 24
Finished Jul 12 05:15:12 PM PDT 24
Peak memory 201860 kb
Host smart-11f203f1-f657-48fe-8bc2-303b0668c53e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292055251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2292055251
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1426791072
Short name T414
Test name
Test status
Simulation time 212861759680 ps
CPU time 118.65 seconds
Started Jul 12 05:05:51 PM PDT 24
Finished Jul 12 05:07:51 PM PDT 24
Peak memory 201856 kb
Host smart-9db741ea-0abb-443f-979e-cd4969820ac7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426791072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1426791072
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3773302593
Short name T330
Test name
Test status
Simulation time 103643469414 ps
CPU time 348.05 seconds
Started Jul 12 05:06:03 PM PDT 24
Finished Jul 12 05:11:51 PM PDT 24
Peak memory 202284 kb
Host smart-d18f5b68-f248-4bfa-83be-89555c0f3f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773302593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3773302593
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.367453642
Short name T737
Test name
Test status
Simulation time 30998625149 ps
CPU time 65.2 seconds
Started Jul 12 05:05:57 PM PDT 24
Finished Jul 12 05:07:03 PM PDT 24
Peak memory 201720 kb
Host smart-bce5e0b3-dbb4-45ee-a892-f28dd8ed1a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367453642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.367453642
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3525799279
Short name T451
Test name
Test status
Simulation time 4742661589 ps
CPU time 1.93 seconds
Started Jul 12 05:05:59 PM PDT 24
Finished Jul 12 05:06:01 PM PDT 24
Peak memory 201660 kb
Host smart-822b48a9-5186-4d51-81e0-b3965755d9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525799279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3525799279
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.4002664316
Short name T563
Test name
Test status
Simulation time 5864109890 ps
CPU time 14.89 seconds
Started Jul 12 05:05:52 PM PDT 24
Finished Jul 12 05:06:08 PM PDT 24
Peak memory 201744 kb
Host smart-3ecd5680-f8f8-40c1-85e0-20644fb19696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002664316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.4002664316
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.4200382427
Short name T40
Test name
Test status
Simulation time 51845424851 ps
CPU time 81.46 seconds
Started Jul 12 05:05:57 PM PDT 24
Finished Jul 12 05:07:19 PM PDT 24
Peak memory 210140 kb
Host smart-e9607843-17a9-4d69-8bef-3863d463f949
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200382427 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.4200382427
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1198530243
Short name T715
Test name
Test status
Simulation time 413677951 ps
CPU time 1.56 seconds
Started Jul 12 05:06:08 PM PDT 24
Finished Jul 12 05:06:10 PM PDT 24
Peak memory 201644 kb
Host smart-5dc78407-799f-4f47-81c0-807de33e1cb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198530243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1198530243
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.2858550615
Short name T213
Test name
Test status
Simulation time 169759782683 ps
CPU time 355.33 seconds
Started Jul 12 05:06:12 PM PDT 24
Finished Jul 12 05:12:08 PM PDT 24
Peak memory 201664 kb
Host smart-b9e57e9f-badf-4635-8baa-27c83cb90727
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858550615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.2858550615
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.959120035
Short name T84
Test name
Test status
Simulation time 494816710305 ps
CPU time 1042.62 seconds
Started Jul 12 05:05:58 PM PDT 24
Finished Jul 12 05:23:22 PM PDT 24
Peak memory 201804 kb
Host smart-15d220b5-bc3c-4780-b393-be8ad5489d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959120035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.959120035
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1034037824
Short name T640
Test name
Test status
Simulation time 162200532459 ps
CPU time 101.75 seconds
Started Jul 12 05:06:10 PM PDT 24
Finished Jul 12 05:07:52 PM PDT 24
Peak memory 201752 kb
Host smart-420036ad-7990-4762-b983-df2bc999dd8e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034037824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1034037824
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.4234322147
Short name T284
Test name
Test status
Simulation time 319049732474 ps
CPU time 395.1 seconds
Started Jul 12 05:05:59 PM PDT 24
Finished Jul 12 05:12:34 PM PDT 24
Peak memory 201832 kb
Host smart-894e711c-0594-4ef4-8879-7219ee2ef13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234322147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.4234322147
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.2640270917
Short name T762
Test name
Test status
Simulation time 169610679704 ps
CPU time 190.81 seconds
Started Jul 12 05:05:59 PM PDT 24
Finished Jul 12 05:09:10 PM PDT 24
Peak memory 201808 kb
Host smart-b0b6f209-3f8e-413b-8bf4-e3e19e7f16a4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640270917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.2640270917
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3797677231
Short name T231
Test name
Test status
Simulation time 390550521289 ps
CPU time 215.22 seconds
Started Jul 12 05:06:12 PM PDT 24
Finished Jul 12 05:09:48 PM PDT 24
Peak memory 201836 kb
Host smart-1911ab60-f734-4806-851a-89a554f9707b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797677231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3797677231
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3826788752
Short name T151
Test name
Test status
Simulation time 192989591918 ps
CPU time 52.34 seconds
Started Jul 12 05:06:07 PM PDT 24
Finished Jul 12 05:07:00 PM PDT 24
Peak memory 201892 kb
Host smart-3503e4e4-8974-4c77-9c48-3d50b150a374
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826788752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3826788752
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1238816575
Short name T618
Test name
Test status
Simulation time 23318864636 ps
CPU time 53.04 seconds
Started Jul 12 05:06:07 PM PDT 24
Finished Jul 12 05:07:00 PM PDT 24
Peak memory 201888 kb
Host smart-f39453b8-4bfe-414b-ae5c-de755e4f8920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238816575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1238816575
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3859727329
Short name T487
Test name
Test status
Simulation time 3436346640 ps
CPU time 8.87 seconds
Started Jul 12 05:06:07 PM PDT 24
Finished Jul 12 05:06:17 PM PDT 24
Peak memory 201564 kb
Host smart-87f4f852-cb25-4d86-b20b-8f2fbaf53220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859727329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3859727329
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1244318189
Short name T654
Test name
Test status
Simulation time 5799675227 ps
CPU time 1.67 seconds
Started Jul 12 05:06:00 PM PDT 24
Finished Jul 12 05:06:02 PM PDT 24
Peak memory 201640 kb
Host smart-595c0d8d-1aea-43b4-8348-96566e224119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244318189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1244318189
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.435654115
Short name T198
Test name
Test status
Simulation time 318370691775 ps
CPU time 681.83 seconds
Started Jul 12 05:06:07 PM PDT 24
Finished Jul 12 05:17:30 PM PDT 24
Peak memory 210320 kb
Host smart-64e7cc5f-1896-41d8-b617-98f0271d8137
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435654115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
435654115
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3636223107
Short name T742
Test name
Test status
Simulation time 210033769969 ps
CPU time 286.02 seconds
Started Jul 12 05:06:07 PM PDT 24
Finished Jul 12 05:10:53 PM PDT 24
Peak memory 210812 kb
Host smart-c5cb0a50-c266-4801-bc23-fe3a72b5eb60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636223107 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3636223107
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3980205669
Short name T573
Test name
Test status
Simulation time 488116823 ps
CPU time 1.22 seconds
Started Jul 12 05:04:06 PM PDT 24
Finished Jul 12 05:04:09 PM PDT 24
Peak memory 201640 kb
Host smart-1e2c3314-77c2-4365-b3b7-64bf8933a907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980205669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3980205669
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3783157627
Short name T148
Test name
Test status
Simulation time 596678282669 ps
CPU time 1263.34 seconds
Started Jul 12 05:04:09 PM PDT 24
Finished Jul 12 05:25:14 PM PDT 24
Peak memory 201920 kb
Host smart-6cf22c09-ad4b-4aea-83eb-dfa5698a4a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783157627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3783157627
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1554399944
Short name T540
Test name
Test status
Simulation time 490895683883 ps
CPU time 163.81 seconds
Started Jul 12 05:04:10 PM PDT 24
Finished Jul 12 05:06:55 PM PDT 24
Peak memory 201904 kb
Host smart-d1b93020-532f-45ea-a693-34e550edbedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554399944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1554399944
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.1339478296
Short name T556
Test name
Test status
Simulation time 159037022996 ps
CPU time 375.93 seconds
Started Jul 12 05:04:10 PM PDT 24
Finished Jul 12 05:10:27 PM PDT 24
Peak memory 201924 kb
Host smart-f434623b-8b64-4c65-b62b-7cc06ee1eec5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339478296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.1339478296
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1316565855
Short name T546
Test name
Test status
Simulation time 167817409599 ps
CPU time 77.35 seconds
Started Jul 12 05:04:08 PM PDT 24
Finished Jul 12 05:05:27 PM PDT 24
Peak memory 201788 kb
Host smart-a1f1a954-0238-4b20-8b41-eab905b08550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316565855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1316565855
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3200104624
Short name T85
Test name
Test status
Simulation time 164601648293 ps
CPU time 288.03 seconds
Started Jul 12 05:04:08 PM PDT 24
Finished Jul 12 05:08:57 PM PDT 24
Peak memory 201880 kb
Host smart-dfc51389-1657-434e-9648-baa63984c479
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200104624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3200104624
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2545593326
Short name T256
Test name
Test status
Simulation time 351333371014 ps
CPU time 79.13 seconds
Started Jul 12 05:04:06 PM PDT 24
Finished Jul 12 05:05:27 PM PDT 24
Peak memory 201900 kb
Host smart-d0329c7c-6031-4325-b627-c6c037703434
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545593326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2545593326
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.774369644
Short name T725
Test name
Test status
Simulation time 405431064257 ps
CPU time 898.28 seconds
Started Jul 12 05:04:12 PM PDT 24
Finished Jul 12 05:19:11 PM PDT 24
Peak memory 201768 kb
Host smart-fbb6d747-97b4-428a-911d-31c7fc16f158
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774369644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.774369644
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.4275486336
Short name T328
Test name
Test status
Simulation time 134157982819 ps
CPU time 703.5 seconds
Started Jul 12 05:04:07 PM PDT 24
Finished Jul 12 05:15:52 PM PDT 24
Peak memory 202204 kb
Host smart-9bcc701d-603f-43a4-8c55-95737cdc873e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275486336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.4275486336
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3953415929
Short name T507
Test name
Test status
Simulation time 23175448011 ps
CPU time 26.34 seconds
Started Jul 12 05:04:13 PM PDT 24
Finished Jul 12 05:04:40 PM PDT 24
Peak memory 201700 kb
Host smart-53962980-19c0-4d24-b7af-30adea849d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953415929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3953415929
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2610198483
Short name T492
Test name
Test status
Simulation time 5330905589 ps
CPU time 14.98 seconds
Started Jul 12 05:04:11 PM PDT 24
Finished Jul 12 05:04:27 PM PDT 24
Peak memory 201712 kb
Host smart-5b5e3826-26e9-43d5-8235-df60da0f1918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610198483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2610198483
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.2718583355
Short name T75
Test name
Test status
Simulation time 7980742455 ps
CPU time 20.1 seconds
Started Jul 12 05:04:09 PM PDT 24
Finished Jul 12 05:04:31 PM PDT 24
Peak memory 218100 kb
Host smart-e7a11823-a4a8-4c38-8f4b-a1c96f0bd717
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718583355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2718583355
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.598951364
Short name T483
Test name
Test status
Simulation time 5723443151 ps
CPU time 13.89 seconds
Started Jul 12 05:04:09 PM PDT 24
Finished Jul 12 05:04:23 PM PDT 24
Peak memory 201664 kb
Host smart-2c12d1c3-edc7-4cbb-9451-1fd2cdb2a712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598951364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.598951364
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2048783909
Short name T738
Test name
Test status
Simulation time 495139315008 ps
CPU time 537.93 seconds
Started Jul 12 05:04:08 PM PDT 24
Finished Jul 12 05:13:07 PM PDT 24
Peak memory 201852 kb
Host smart-284c959f-520f-4799-95e3-ec06b155ade1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048783909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2048783909
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.511035995
Short name T601
Test name
Test status
Simulation time 500966997 ps
CPU time 0.82 seconds
Started Jul 12 05:06:19 PM PDT 24
Finished Jul 12 05:06:21 PM PDT 24
Peak memory 201652 kb
Host smart-feaf530e-c614-4507-bfbc-1be128752bf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511035995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.511035995
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.1919385621
Short name T297
Test name
Test status
Simulation time 542153099980 ps
CPU time 323.2 seconds
Started Jul 12 05:06:14 PM PDT 24
Finished Jul 12 05:11:38 PM PDT 24
Peak memory 201672 kb
Host smart-1796bc03-d8fd-4377-9699-7e0aa662e3f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919385621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.1919385621
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.4180429135
Short name T158
Test name
Test status
Simulation time 323669636193 ps
CPU time 751.04 seconds
Started Jul 12 05:06:12 PM PDT 24
Finished Jul 12 05:18:43 PM PDT 24
Peak memory 201844 kb
Host smart-cdb5afd2-eddc-4dce-b473-55d6e872e23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180429135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.4180429135
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.859252017
Short name T641
Test name
Test status
Simulation time 338514939564 ps
CPU time 208.53 seconds
Started Jul 12 05:06:13 PM PDT 24
Finished Jul 12 05:09:42 PM PDT 24
Peak memory 201868 kb
Host smart-4306c54b-976e-4113-a0e9-d82470ce3a5a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=859252017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrup
t_fixed.859252017
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3677738828
Short name T223
Test name
Test status
Simulation time 328114278986 ps
CPU time 385.06 seconds
Started Jul 12 05:06:12 PM PDT 24
Finished Jul 12 05:12:37 PM PDT 24
Peak memory 201944 kb
Host smart-28e7ad20-e9b2-48db-a48c-5229991e5a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677738828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3677738828
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1954682217
Short name T15
Test name
Test status
Simulation time 330549381522 ps
CPU time 776.65 seconds
Started Jul 12 05:06:15 PM PDT 24
Finished Jul 12 05:19:12 PM PDT 24
Peak memory 201776 kb
Host smart-1fe23f94-f571-4d61-83c6-e90066a560c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954682217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1954682217
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1105615646
Short name T630
Test name
Test status
Simulation time 178953256204 ps
CPU time 108.37 seconds
Started Jul 12 05:06:14 PM PDT 24
Finished Jul 12 05:08:03 PM PDT 24
Peak memory 201680 kb
Host smart-fd154aa4-ba95-404e-a878-98c0107eaa8e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105615646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1105615646
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1922619816
Short name T534
Test name
Test status
Simulation time 393647536312 ps
CPU time 296.57 seconds
Started Jul 12 05:06:13 PM PDT 24
Finished Jul 12 05:11:10 PM PDT 24
Peak memory 201848 kb
Host smart-d1603e68-b942-4101-932a-89fd0a872fc7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922619816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1922619816
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3080193830
Short name T400
Test name
Test status
Simulation time 75744002959 ps
CPU time 278.71 seconds
Started Jul 12 05:06:19 PM PDT 24
Finished Jul 12 05:10:58 PM PDT 24
Peak memory 202260 kb
Host smart-92bbe88c-05a5-4017-a004-8c05aea5a09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080193830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3080193830
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.4198733230
Short name T443
Test name
Test status
Simulation time 38248336487 ps
CPU time 79.45 seconds
Started Jul 12 05:06:19 PM PDT 24
Finished Jul 12 05:07:38 PM PDT 24
Peak memory 201608 kb
Host smart-b034be33-dfa0-44bb-ad00-b5e33ddcdfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198733230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.4198733230
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1531515800
Short name T658
Test name
Test status
Simulation time 3168102922 ps
CPU time 2.09 seconds
Started Jul 12 05:06:15 PM PDT 24
Finished Jul 12 05:06:18 PM PDT 24
Peak memory 201604 kb
Host smart-6ec12714-116d-4177-a0b6-7e9f5c91ab2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531515800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1531515800
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.4134990602
Short name T93
Test name
Test status
Simulation time 6111922578 ps
CPU time 4.19 seconds
Started Jul 12 05:06:07 PM PDT 24
Finished Jul 12 05:06:12 PM PDT 24
Peak memory 201696 kb
Host smart-b4f20726-021e-4447-af6d-974d1fe4a7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134990602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.4134990602
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3636718561
Short name T521
Test name
Test status
Simulation time 340255749833 ps
CPU time 526.96 seconds
Started Jul 12 05:06:19 PM PDT 24
Finished Jul 12 05:15:06 PM PDT 24
Peak memory 201876 kb
Host smart-f2fd0cc1-32b8-4eb2-a672-0e08d77ba3fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636718561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3636718561
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3529094929
Short name T615
Test name
Test status
Simulation time 23687683801 ps
CPU time 33.03 seconds
Started Jul 12 05:06:18 PM PDT 24
Finished Jul 12 05:06:52 PM PDT 24
Peak memory 210520 kb
Host smart-d73d3702-fa1d-4986-8669-ad900161c9fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529094929 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3529094929
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2440461737
Short name T555
Test name
Test status
Simulation time 470207840 ps
CPU time 1.76 seconds
Started Jul 12 05:06:35 PM PDT 24
Finished Jul 12 05:06:37 PM PDT 24
Peak memory 201604 kb
Host smart-eb105160-d9a2-41c0-93eb-83a8b8edf331
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440461737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2440461737
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.4067815156
Short name T321
Test name
Test status
Simulation time 327790667631 ps
CPU time 187.99 seconds
Started Jul 12 05:06:26 PM PDT 24
Finished Jul 12 05:09:34 PM PDT 24
Peak memory 201988 kb
Host smart-f2cf7359-112c-4e93-b8b1-ec105eb4c300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067815156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.4067815156
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.4038635098
Short name T383
Test name
Test status
Simulation time 488064829230 ps
CPU time 536.55 seconds
Started Jul 12 05:06:27 PM PDT 24
Finished Jul 12 05:15:24 PM PDT 24
Peak memory 201828 kb
Host smart-cb604ae8-efcb-4cf1-a43e-40bc6c347de7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038635098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.4038635098
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.3271038925
Short name T307
Test name
Test status
Simulation time 164995787201 ps
CPU time 374.72 seconds
Started Jul 12 05:06:18 PM PDT 24
Finished Jul 12 05:12:33 PM PDT 24
Peak memory 201860 kb
Host smart-0933a4c9-7bd7-4f6e-aaa1-889f96180968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271038925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.3271038925
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.4068390338
Short name T633
Test name
Test status
Simulation time 326141461077 ps
CPU time 103.09 seconds
Started Jul 12 05:06:27 PM PDT 24
Finished Jul 12 05:08:10 PM PDT 24
Peak memory 201868 kb
Host smart-88b5fe29-ab73-4ac4-b7ba-4419bca535aa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068390338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.4068390338
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2126625649
Short name T430
Test name
Test status
Simulation time 169160699085 ps
CPU time 379.03 seconds
Started Jul 12 05:06:28 PM PDT 24
Finished Jul 12 05:12:47 PM PDT 24
Peak memory 201724 kb
Host smart-6489ee6d-69c8-4840-880f-f1b1a69830cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126625649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2126625649
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.996091400
Short name T727
Test name
Test status
Simulation time 398790642653 ps
CPU time 955.46 seconds
Started Jul 12 05:06:31 PM PDT 24
Finished Jul 12 05:22:26 PM PDT 24
Peak memory 201876 kb
Host smart-f8f291fe-fdff-4456-bcc1-5b2372450e28
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996091400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.996091400
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2345360462
Short name T520
Test name
Test status
Simulation time 120301315411 ps
CPU time 615.69 seconds
Started Jul 12 05:06:29 PM PDT 24
Finished Jul 12 05:16:45 PM PDT 24
Peak memory 202144 kb
Host smart-e52132c7-b3a9-4614-a6b0-0cabd24c3787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345360462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2345360462
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3312379219
Short name T29
Test name
Test status
Simulation time 42830205199 ps
CPU time 15.03 seconds
Started Jul 12 05:06:28 PM PDT 24
Finished Jul 12 05:06:43 PM PDT 24
Peak memory 201604 kb
Host smart-ea24e4f1-7a66-4467-9e92-c723f93820d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312379219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3312379219
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.2499138613
Short name T444
Test name
Test status
Simulation time 4042222431 ps
CPU time 3.05 seconds
Started Jul 12 05:06:30 PM PDT 24
Finished Jul 12 05:06:33 PM PDT 24
Peak memory 201580 kb
Host smart-c175053e-a46f-4d4c-8f1b-2fb14d859e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499138613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2499138613
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.417826300
Short name T535
Test name
Test status
Simulation time 5874178038 ps
CPU time 14.47 seconds
Started Jul 12 05:06:19 PM PDT 24
Finished Jul 12 05:06:34 PM PDT 24
Peak memory 201684 kb
Host smart-750766c3-2782-4812-a53f-34eab6f70e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417826300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.417826300
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.322242783
Short name T270
Test name
Test status
Simulation time 760191671728 ps
CPU time 1708.79 seconds
Started Jul 12 05:06:37 PM PDT 24
Finished Jul 12 05:35:06 PM PDT 24
Peak memory 202252 kb
Host smart-7492ab7c-d1ed-42d9-851d-ec9cef70e15c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322242783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.
322242783
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1291718596
Short name T41
Test name
Test status
Simulation time 50044308176 ps
CPU time 86.05 seconds
Started Jul 12 05:06:39 PM PDT 24
Finished Jul 12 05:08:05 PM PDT 24
Peak memory 217984 kb
Host smart-43f963a9-6305-45df-95b6-d5f0ee031208
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291718596 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1291718596
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2005503550
Short name T419
Test name
Test status
Simulation time 481739175 ps
CPU time 0.8 seconds
Started Jul 12 05:06:34 PM PDT 24
Finished Jul 12 05:06:36 PM PDT 24
Peak memory 201640 kb
Host smart-1d831e1f-f4e3-4a5f-ba37-cfadff17b3a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005503550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2005503550
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3687551485
Short name T306
Test name
Test status
Simulation time 570188009994 ps
CPU time 620.7 seconds
Started Jul 12 05:06:35 PM PDT 24
Finished Jul 12 05:16:57 PM PDT 24
Peak memory 201784 kb
Host smart-e5e6e4bb-0803-40c2-b397-d57ce5634e5d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687551485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3687551485
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3364223361
Short name T170
Test name
Test status
Simulation time 333226723258 ps
CPU time 180.26 seconds
Started Jul 12 05:06:34 PM PDT 24
Finished Jul 12 05:09:34 PM PDT 24
Peak memory 201872 kb
Host smart-6316ec0e-6315-4364-9313-8b24f86c964c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364223361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3364223361
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3578873022
Short name T734
Test name
Test status
Simulation time 160429893582 ps
CPU time 189.35 seconds
Started Jul 12 05:06:35 PM PDT 24
Finished Jul 12 05:09:45 PM PDT 24
Peak memory 201724 kb
Host smart-4e3b462f-f2c2-412e-b6e3-55d75b5f2ff0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578873022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3578873022
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1239001453
Short name T624
Test name
Test status
Simulation time 329719274811 ps
CPU time 683.71 seconds
Started Jul 12 05:06:34 PM PDT 24
Finished Jul 12 05:17:58 PM PDT 24
Peak memory 201984 kb
Host smart-2f549730-e40c-496e-a782-432ba4c4ab9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239001453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1239001453
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1851531420
Short name T760
Test name
Test status
Simulation time 499146839007 ps
CPU time 280.54 seconds
Started Jul 12 05:06:34 PM PDT 24
Finished Jul 12 05:11:16 PM PDT 24
Peak memory 201884 kb
Host smart-b9e73a77-9b7a-4805-bcfc-cac162a34b6b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851531420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1851531420
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3440405435
Short name T5
Test name
Test status
Simulation time 395427687746 ps
CPU time 173.22 seconds
Started Jul 12 05:06:34 PM PDT 24
Finished Jul 12 05:09:28 PM PDT 24
Peak memory 201864 kb
Host smart-44aff039-0398-4da1-9f80-4c7264c4201b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440405435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3440405435
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2095152950
Short name T784
Test name
Test status
Simulation time 409822295558 ps
CPU time 866.23 seconds
Started Jul 12 05:06:36 PM PDT 24
Finished Jul 12 05:21:03 PM PDT 24
Peak memory 201940 kb
Host smart-b9c934bd-2b84-427b-94b4-501f0b647de9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095152950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2095152950
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.4116841706
Short name T200
Test name
Test status
Simulation time 102190290760 ps
CPU time 580.07 seconds
Started Jul 12 05:06:35 PM PDT 24
Finished Jul 12 05:16:16 PM PDT 24
Peak memory 202216 kb
Host smart-fc5df5c6-45e8-4afe-82d7-e9ffe8dff859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116841706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.4116841706
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3234359680
Short name T536
Test name
Test status
Simulation time 27848207505 ps
CPU time 61.16 seconds
Started Jul 12 05:06:33 PM PDT 24
Finished Jul 12 05:07:34 PM PDT 24
Peak memory 201484 kb
Host smart-dbc9b791-d758-4b00-8625-021aa9b5f358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234359680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3234359680
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.334707318
Short name T502
Test name
Test status
Simulation time 4730323880 ps
CPU time 3.88 seconds
Started Jul 12 05:06:34 PM PDT 24
Finished Jul 12 05:06:39 PM PDT 24
Peak memory 201700 kb
Host smart-930d3d86-7553-4a00-8d66-1f47fe81de23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334707318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.334707318
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2328135411
Short name T362
Test name
Test status
Simulation time 5877812176 ps
CPU time 14.1 seconds
Started Jul 12 05:06:36 PM PDT 24
Finished Jul 12 05:06:50 PM PDT 24
Peak memory 201576 kb
Host smart-20cd5bb8-0345-410e-b627-a158534b2fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328135411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2328135411
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3032689056
Short name T500
Test name
Test status
Simulation time 334220459303 ps
CPU time 741.9 seconds
Started Jul 12 05:06:35 PM PDT 24
Finished Jul 12 05:18:57 PM PDT 24
Peak memory 210360 kb
Host smart-a4c2fcbf-2383-4815-bcbc-2b49ce460fa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032689056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3032689056
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.4242636446
Short name T748
Test name
Test status
Simulation time 316849154778 ps
CPU time 244.47 seconds
Started Jul 12 05:06:38 PM PDT 24
Finished Jul 12 05:10:43 PM PDT 24
Peak memory 217248 kb
Host smart-04eef60a-93bb-4efd-9be8-f8fc9d3683d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242636446 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.4242636446
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2149024573
Short name T398
Test name
Test status
Simulation time 384667991 ps
CPU time 1.51 seconds
Started Jul 12 05:06:51 PM PDT 24
Finished Jul 12 05:06:53 PM PDT 24
Peak memory 201644 kb
Host smart-c8eed324-023f-4598-a751-df219bac1559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149024573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2149024573
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.1925085099
Short name T271
Test name
Test status
Simulation time 545284716865 ps
CPU time 191.83 seconds
Started Jul 12 05:06:41 PM PDT 24
Finished Jul 12 05:09:54 PM PDT 24
Peak memory 201748 kb
Host smart-9e18402b-f07c-4ea5-9e55-395a38021fe7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925085099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.1925085099
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2875592979
Short name T244
Test name
Test status
Simulation time 352121848187 ps
CPU time 755.86 seconds
Started Jul 12 05:06:44 PM PDT 24
Finished Jul 12 05:19:20 PM PDT 24
Peak memory 201912 kb
Host smart-7166a4f7-f5c1-4765-88ef-2e4f66459593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875592979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2875592979
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2606211972
Short name T614
Test name
Test status
Simulation time 164935183539 ps
CPU time 29.36 seconds
Started Jul 12 05:06:42 PM PDT 24
Finished Jul 12 05:07:12 PM PDT 24
Peak memory 201956 kb
Host smart-a7653308-a832-40f1-a936-821f9491ae1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606211972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2606211972
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1581328940
Short name T477
Test name
Test status
Simulation time 169839083569 ps
CPU time 373.66 seconds
Started Jul 12 05:06:43 PM PDT 24
Finished Jul 12 05:12:57 PM PDT 24
Peak memory 201876 kb
Host smart-e5954a36-1d89-4b1d-8731-2699e96d5603
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581328940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1581328940
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2830653204
Short name T611
Test name
Test status
Simulation time 336656152159 ps
CPU time 784.24 seconds
Started Jul 12 05:06:44 PM PDT 24
Finished Jul 12 05:19:49 PM PDT 24
Peak memory 201980 kb
Host smart-27fbff41-b071-4cb1-b2ab-0adcf854fa9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830653204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2830653204
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1930397722
Short name T686
Test name
Test status
Simulation time 332132092688 ps
CPU time 173.72 seconds
Started Jul 12 05:06:41 PM PDT 24
Finished Jul 12 05:09:35 PM PDT 24
Peak memory 201728 kb
Host smart-af42b927-c619-4889-ac97-64abee0dcd17
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930397722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1930397722
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.1500668865
Short name T276
Test name
Test status
Simulation time 361109399573 ps
CPU time 401.43 seconds
Started Jul 12 05:06:42 PM PDT 24
Finished Jul 12 05:13:25 PM PDT 24
Peak memory 201872 kb
Host smart-a992a249-c302-4407-9555-b026e52f2fc7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500668865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.1500668865
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1649396690
Short name T718
Test name
Test status
Simulation time 192528558439 ps
CPU time 403.3 seconds
Started Jul 12 05:06:42 PM PDT 24
Finished Jul 12 05:13:27 PM PDT 24
Peak memory 201840 kb
Host smart-ba9fdfa0-22fc-4c3e-b665-1246ec1341a3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649396690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1649396690
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2860773584
Short name T332
Test name
Test status
Simulation time 95915687174 ps
CPU time 328.49 seconds
Started Jul 12 05:06:49 PM PDT 24
Finished Jul 12 05:12:18 PM PDT 24
Peak memory 202216 kb
Host smart-f83bf98e-e9ba-4b17-8be2-080b2475e7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860773584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2860773584
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.1218648907
Short name T741
Test name
Test status
Simulation time 23786072190 ps
CPU time 5.87 seconds
Started Jul 12 05:06:50 PM PDT 24
Finished Jul 12 05:06:56 PM PDT 24
Peak memory 201700 kb
Host smart-48b413c0-a5b9-4091-8550-4f7a4165c266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218648907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.1218648907
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3486938033
Short name T100
Test name
Test status
Simulation time 3029473574 ps
CPU time 1.97 seconds
Started Jul 12 05:06:44 PM PDT 24
Finished Jul 12 05:06:46 PM PDT 24
Peak memory 201620 kb
Host smart-9f0981f7-517a-4060-8386-36f72fe921d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486938033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3486938033
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1573688871
Short name T452
Test name
Test status
Simulation time 6056806547 ps
CPU time 7.41 seconds
Started Jul 12 05:06:34 PM PDT 24
Finished Jul 12 05:06:43 PM PDT 24
Peak memory 201660 kb
Host smart-7ae6e3f3-8a87-43cf-9a9c-56e58abbec80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573688871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1573688871
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1347202056
Short name T309
Test name
Test status
Simulation time 502541967604 ps
CPU time 227.99 seconds
Started Jul 12 05:06:50 PM PDT 24
Finished Jul 12 05:10:39 PM PDT 24
Peak memory 201892 kb
Host smart-b112beec-1398-4cbd-b537-fdcf86472cde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347202056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1347202056
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1363758891
Short name T579
Test name
Test status
Simulation time 32135906969 ps
CPU time 52.68 seconds
Started Jul 12 05:06:50 PM PDT 24
Finished Jul 12 05:07:43 PM PDT 24
Peak memory 210504 kb
Host smart-36862e07-787f-4131-b562-8e6b7c2badeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363758891 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1363758891
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1788333950
Short name T408
Test name
Test status
Simulation time 304025486 ps
CPU time 0.81 seconds
Started Jul 12 05:07:03 PM PDT 24
Finished Jul 12 05:07:04 PM PDT 24
Peak memory 201592 kb
Host smart-6f438e3f-9408-4e2b-9e8a-04fdb5dcd260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788333950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1788333950
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3733639996
Short name T44
Test name
Test status
Simulation time 322544101899 ps
CPU time 228.9 seconds
Started Jul 12 05:06:58 PM PDT 24
Finished Jul 12 05:10:48 PM PDT 24
Peak memory 201836 kb
Host smart-203c08b5-78e6-463a-93e6-80a3622a8418
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733639996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3733639996
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.400222348
Short name T194
Test name
Test status
Simulation time 526889114499 ps
CPU time 298.87 seconds
Started Jul 12 05:06:58 PM PDT 24
Finished Jul 12 05:11:58 PM PDT 24
Peak memory 201768 kb
Host smart-6c91eec7-1c7d-440c-9ff1-3a2a19812567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400222348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.400222348
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2885303329
Short name T319
Test name
Test status
Simulation time 491526020081 ps
CPU time 163.6 seconds
Started Jul 12 05:06:51 PM PDT 24
Finished Jul 12 05:09:36 PM PDT 24
Peak memory 201844 kb
Host smart-82af6624-634a-4e3f-8d96-6643bf346d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885303329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2885303329
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1934646560
Short name T99
Test name
Test status
Simulation time 484876589065 ps
CPU time 556.73 seconds
Started Jul 12 05:06:51 PM PDT 24
Finished Jul 12 05:16:09 PM PDT 24
Peak memory 201844 kb
Host smart-f9e83a8f-a78a-4ce0-a88c-3a3c19418614
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934646560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1934646560
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1882004322
Short name T523
Test name
Test status
Simulation time 324570111282 ps
CPU time 193.54 seconds
Started Jul 12 05:06:53 PM PDT 24
Finished Jul 12 05:10:07 PM PDT 24
Peak memory 201776 kb
Host smart-759d89e7-78a2-4041-9adb-ab691bdb8f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882004322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1882004322
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1185791219
Short name T361
Test name
Test status
Simulation time 161120185407 ps
CPU time 100.24 seconds
Started Jul 12 05:06:51 PM PDT 24
Finished Jul 12 05:08:31 PM PDT 24
Peak memory 201864 kb
Host smart-26149cd5-b690-417e-b5b5-671802cd5408
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185791219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1185791219
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1123668313
Short name T149
Test name
Test status
Simulation time 510416289568 ps
CPU time 132.21 seconds
Started Jul 12 05:06:52 PM PDT 24
Finished Jul 12 05:09:04 PM PDT 24
Peak memory 201912 kb
Host smart-e558973f-ce8b-4469-960d-15a26b361ced
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123668313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1123668313
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3844977679
Short name T469
Test name
Test status
Simulation time 392005800120 ps
CPU time 225.83 seconds
Started Jul 12 05:06:49 PM PDT 24
Finished Jul 12 05:10:35 PM PDT 24
Peak memory 201920 kb
Host smart-242f9d47-9c40-4e1d-b563-a7ba516fefd1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844977679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3844977679
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2843777080
Short name T454
Test name
Test status
Simulation time 82841851210 ps
CPU time 284.37 seconds
Started Jul 12 05:07:03 PM PDT 24
Finished Jul 12 05:11:47 PM PDT 24
Peak memory 202256 kb
Host smart-956bd104-840a-4dab-b02a-62cc4a43528e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843777080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2843777080
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1148182393
Short name T696
Test name
Test status
Simulation time 21250702468 ps
CPU time 44.65 seconds
Started Jul 12 05:06:57 PM PDT 24
Finished Jul 12 05:07:42 PM PDT 24
Peak memory 201624 kb
Host smart-4de3245c-a070-45af-8318-510e938c47f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148182393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1148182393
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.2244671905
Short name T80
Test name
Test status
Simulation time 4549023954 ps
CPU time 6.35 seconds
Started Jul 12 05:06:58 PM PDT 24
Finished Jul 12 05:07:04 PM PDT 24
Peak memory 201592 kb
Host smart-85e0cbdb-a250-47b2-aabc-191ba41aba8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244671905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2244671905
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1075682878
Short name T677
Test name
Test status
Simulation time 6130604881 ps
CPU time 6.96 seconds
Started Jul 12 05:06:50 PM PDT 24
Finished Jul 12 05:06:57 PM PDT 24
Peak memory 201552 kb
Host smart-5c24e83b-729b-452e-ad53-e18f594df6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075682878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1075682878
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1977208913
Short name T512
Test name
Test status
Simulation time 461425726498 ps
CPU time 1409.47 seconds
Started Jul 12 05:06:58 PM PDT 24
Finished Jul 12 05:30:29 PM PDT 24
Peak memory 202180 kb
Host smart-250e7f94-cd9a-4dc2-8c12-681ebf3ce428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977208913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1977208913
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.68270282
Short name T662
Test name
Test status
Simulation time 190517698746 ps
CPU time 237.83 seconds
Started Jul 12 05:06:57 PM PDT 24
Finished Jul 12 05:10:56 PM PDT 24
Peak memory 210532 kb
Host smart-e2333995-4a21-46e1-be02-d08b691d0a38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68270282 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.68270282
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.3817489634
Short name T717
Test name
Test status
Simulation time 500193995 ps
CPU time 1.14 seconds
Started Jul 12 05:07:05 PM PDT 24
Finished Jul 12 05:07:07 PM PDT 24
Peak memory 201644 kb
Host smart-e7c04fa0-36b3-4153-93aa-bd996aab993b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817489634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.3817489634
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2924631397
Short name T221
Test name
Test status
Simulation time 506628719116 ps
CPU time 1144.62 seconds
Started Jul 12 05:07:04 PM PDT 24
Finished Jul 12 05:26:09 PM PDT 24
Peak memory 201788 kb
Host smart-e4224e79-6f6a-47bb-b650-2ac7508652e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924631397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2924631397
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.2403911048
Short name T109
Test name
Test status
Simulation time 340436615151 ps
CPU time 802.58 seconds
Started Jul 12 05:07:05 PM PDT 24
Finished Jul 12 05:20:28 PM PDT 24
Peak memory 201904 kb
Host smart-ed6cc07d-21eb-4cd1-aac6-94d3e3d2d056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403911048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2403911048
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1766658916
Short name T363
Test name
Test status
Simulation time 165735881764 ps
CPU time 146.32 seconds
Started Jul 12 05:06:58 PM PDT 24
Finished Jul 12 05:09:25 PM PDT 24
Peak memory 201856 kb
Host smart-bede6d5b-7599-4b5b-a904-dfe9ab669097
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766658916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1766658916
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3951005594
Short name T639
Test name
Test status
Simulation time 163636131627 ps
CPU time 190.37 seconds
Started Jul 12 05:06:58 PM PDT 24
Finished Jul 12 05:10:08 PM PDT 24
Peak memory 201904 kb
Host smart-9ba2d00a-a95b-4477-83ed-ac1d0408a62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951005594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3951005594
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.720429560
Short name T426
Test name
Test status
Simulation time 486470556951 ps
CPU time 541.39 seconds
Started Jul 12 05:06:59 PM PDT 24
Finished Jul 12 05:16:01 PM PDT 24
Peak memory 201880 kb
Host smart-f3d9eaa6-0d5d-4015-96d3-fd865c6a4ea5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=720429560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.720429560
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.1084766363
Short name T245
Test name
Test status
Simulation time 344082352689 ps
CPU time 798.28 seconds
Started Jul 12 05:07:06 PM PDT 24
Finished Jul 12 05:20:25 PM PDT 24
Peak memory 201776 kb
Host smart-eb5b5277-eabd-4d4f-af78-5bae89c474c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084766363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.1084766363
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.261920844
Short name T391
Test name
Test status
Simulation time 613845930952 ps
CPU time 91.37 seconds
Started Jul 12 05:07:05 PM PDT 24
Finished Jul 12 05:08:37 PM PDT 24
Peak memory 201876 kb
Host smart-3b42b778-19fc-4d87-88d9-61256b1cbd29
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261920844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.261920844
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1340293227
Short name T768
Test name
Test status
Simulation time 82218528244 ps
CPU time 452.64 seconds
Started Jul 12 05:07:05 PM PDT 24
Finished Jul 12 05:14:38 PM PDT 24
Peak memory 202288 kb
Host smart-c4c17084-1f35-4192-abe1-c24d449718b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340293227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1340293227
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2794401005
Short name T666
Test name
Test status
Simulation time 25496066227 ps
CPU time 13.91 seconds
Started Jul 12 05:07:04 PM PDT 24
Finished Jul 12 05:07:19 PM PDT 24
Peak memory 201596 kb
Host smart-9bcc16fa-1f34-46d2-bf0b-86d83efd9257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794401005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2794401005
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3940619156
Short name T564
Test name
Test status
Simulation time 2947160364 ps
CPU time 2.42 seconds
Started Jul 12 05:07:04 PM PDT 24
Finished Jul 12 05:07:07 PM PDT 24
Peak memory 201772 kb
Host smart-faec118d-101c-40a1-970f-cbfdc7028362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940619156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3940619156
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.223456303
Short name T411
Test name
Test status
Simulation time 5923054714 ps
CPU time 1.87 seconds
Started Jul 12 05:06:56 PM PDT 24
Finished Jul 12 05:06:58 PM PDT 24
Peak memory 201608 kb
Host smart-4bf6f143-e487-4b2d-8995-ce599fa31653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223456303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.223456303
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3557561253
Short name T527
Test name
Test status
Simulation time 431990403132 ps
CPU time 1288.38 seconds
Started Jul 12 05:07:05 PM PDT 24
Finished Jul 12 05:28:35 PM PDT 24
Peak memory 202192 kb
Host smart-d4376170-ff98-46af-9f8b-68f6ed80e74e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557561253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3557561253
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1721163205
Short name T22
Test name
Test status
Simulation time 132960311736 ps
CPU time 67.88 seconds
Started Jul 12 05:07:04 PM PDT 24
Finished Jul 12 05:08:12 PM PDT 24
Peak memory 210404 kb
Host smart-6da9a960-5a8e-4aa6-af58-c5e6d72d3c06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721163205 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1721163205
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2900597480
Short name T341
Test name
Test status
Simulation time 316302375 ps
CPU time 0.79 seconds
Started Jul 12 05:07:20 PM PDT 24
Finished Jul 12 05:07:21 PM PDT 24
Peak memory 201648 kb
Host smart-eaa5cde5-665f-41ed-8109-54e96aafd627
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900597480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2900597480
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.660028067
Short name T711
Test name
Test status
Simulation time 160315569334 ps
CPU time 96.38 seconds
Started Jul 12 05:07:19 PM PDT 24
Finished Jul 12 05:08:56 PM PDT 24
Peak memory 201836 kb
Host smart-6172b351-2cbb-411a-a948-0244d1ba5ba3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660028067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.660028067
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3441472781
Short name T252
Test name
Test status
Simulation time 386617613642 ps
CPU time 458.41 seconds
Started Jul 12 05:07:18 PM PDT 24
Finished Jul 12 05:14:57 PM PDT 24
Peak memory 201800 kb
Host smart-97b98c57-90b5-4583-a2e2-f9686ac326c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441472781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3441472781
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2007107899
Short name T237
Test name
Test status
Simulation time 163220244014 ps
CPU time 93.01 seconds
Started Jul 12 05:07:12 PM PDT 24
Finished Jul 12 05:08:46 PM PDT 24
Peak memory 201948 kb
Host smart-b3dd6f7a-226a-4087-841f-1bf16ae3abcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007107899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2007107899
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1416129859
Short name T88
Test name
Test status
Simulation time 168132579661 ps
CPU time 193.16 seconds
Started Jul 12 05:07:13 PM PDT 24
Finished Jul 12 05:10:27 PM PDT 24
Peak memory 201752 kb
Host smart-4bb1367a-d681-4b38-80a7-6bece22f2767
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416129859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.1416129859
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.236715750
Short name T286
Test name
Test status
Simulation time 326387504831 ps
CPU time 185.04 seconds
Started Jul 12 05:07:14 PM PDT 24
Finished Jul 12 05:10:20 PM PDT 24
Peak memory 201792 kb
Host smart-fac72013-b93f-4822-b4c2-332716367976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236715750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.236715750
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2503287446
Short name T409
Test name
Test status
Simulation time 326531980827 ps
CPU time 176.75 seconds
Started Jul 12 05:07:14 PM PDT 24
Finished Jul 12 05:10:11 PM PDT 24
Peak memory 201740 kb
Host smart-bff25c55-f34c-455a-a18a-e29a4fc4f5fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503287446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2503287446
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3263340177
Short name T275
Test name
Test status
Simulation time 348340718296 ps
CPU time 379.56 seconds
Started Jul 12 05:07:11 PM PDT 24
Finished Jul 12 05:13:31 PM PDT 24
Peak memory 201912 kb
Host smart-141726be-6d7a-443e-818a-8756dea16c90
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263340177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3263340177
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2158418962
Short name T509
Test name
Test status
Simulation time 590426724758 ps
CPU time 628.28 seconds
Started Jul 12 05:07:12 PM PDT 24
Finished Jul 12 05:17:41 PM PDT 24
Peak memory 201856 kb
Host smart-b387db8b-f873-4e2f-8cc9-49e3d9763b82
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158418962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2158418962
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.431459338
Short name T643
Test name
Test status
Simulation time 129638033630 ps
CPU time 549.75 seconds
Started Jul 12 05:07:19 PM PDT 24
Finished Jul 12 05:16:30 PM PDT 24
Peak memory 202176 kb
Host smart-1ebc1245-69bc-425b-bb68-0947229c8c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431459338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.431459338
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3509498327
Short name T700
Test name
Test status
Simulation time 28106551160 ps
CPU time 23.91 seconds
Started Jul 12 05:07:19 PM PDT 24
Finished Jul 12 05:07:43 PM PDT 24
Peak memory 201668 kb
Host smart-deff5818-132b-4923-9e05-5d6c78b2ec4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509498327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3509498327
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1663016578
Short name T394
Test name
Test status
Simulation time 4177371481 ps
CPU time 1.23 seconds
Started Jul 12 05:07:20 PM PDT 24
Finished Jul 12 05:07:22 PM PDT 24
Peak memory 201692 kb
Host smart-d48b1d10-c8ea-49b7-a5f7-e26c1f145d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663016578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1663016578
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1772182432
Short name T95
Test name
Test status
Simulation time 6033044611 ps
CPU time 2.37 seconds
Started Jul 12 05:07:04 PM PDT 24
Finished Jul 12 05:07:07 PM PDT 24
Peak memory 201580 kb
Host smart-e83fcafd-ab64-4dbb-8520-625967b9f9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772182432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1772182432
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3877514943
Short name T632
Test name
Test status
Simulation time 121372556617 ps
CPU time 440.65 seconds
Started Jul 12 05:07:19 PM PDT 24
Finished Jul 12 05:14:40 PM PDT 24
Peak memory 210456 kb
Host smart-b89392dd-b5e2-4d9e-9783-193e925576b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877514943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3877514943
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.59019158
Short name T322
Test name
Test status
Simulation time 58289246570 ps
CPU time 127.65 seconds
Started Jul 12 05:07:19 PM PDT 24
Finished Jul 12 05:09:27 PM PDT 24
Peak memory 210516 kb
Host smart-0e8f2b04-3db6-43cd-8d08-c31efaba036f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59019158 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.59019158
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2183372874
Short name T385
Test name
Test status
Simulation time 461111696 ps
CPU time 0.88 seconds
Started Jul 12 05:07:25 PM PDT 24
Finished Jul 12 05:07:27 PM PDT 24
Peak memory 201568 kb
Host smart-ac7e4040-c668-4429-bc55-3331e5c936e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183372874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2183372874
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3153518748
Short name T720
Test name
Test status
Simulation time 346438514442 ps
CPU time 383.46 seconds
Started Jul 12 05:07:27 PM PDT 24
Finished Jul 12 05:13:51 PM PDT 24
Peak memory 201756 kb
Host smart-75c62ccf-2e12-40ac-a593-610a1beee052
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153518748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3153518748
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1536021033
Short name T691
Test name
Test status
Simulation time 164284850800 ps
CPU time 101.44 seconds
Started Jul 12 06:55:54 PM PDT 24
Finished Jul 12 06:57:37 PM PDT 24
Peak memory 201980 kb
Host smart-b030a7c4-56e5-4247-b964-34e44e797151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536021033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1536021033
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3932623224
Short name T291
Test name
Test status
Simulation time 493442701360 ps
CPU time 280.34 seconds
Started Jul 12 05:07:26 PM PDT 24
Finished Jul 12 05:12:07 PM PDT 24
Peak memory 201848 kb
Host smart-e80ae1dc-17e0-4c6e-aa35-e55b0191f770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932623224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3932623224
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3831758378
Short name T404
Test name
Test status
Simulation time 497114538815 ps
CPU time 1134.77 seconds
Started Jul 12 05:07:28 PM PDT 24
Finished Jul 12 05:26:24 PM PDT 24
Peak memory 201840 kb
Host smart-bf840371-d2b5-496f-9ddb-30ec02b35754
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831758378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.3831758378
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.4178970225
Short name T799
Test name
Test status
Simulation time 162280251223 ps
CPU time 191 seconds
Started Jul 12 05:07:19 PM PDT 24
Finished Jul 12 05:10:30 PM PDT 24
Peak memory 201880 kb
Host smart-836a504e-bdb0-43ad-a1c0-770d7516ce92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178970225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.4178970225
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2297012708
Short name T8
Test name
Test status
Simulation time 329973010581 ps
CPU time 379.59 seconds
Started Jul 12 05:07:17 PM PDT 24
Finished Jul 12 05:13:37 PM PDT 24
Peak memory 201772 kb
Host smart-c55e129f-bdad-4444-817e-c8f637a9ec5f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297012708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2297012708
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2020321593
Short name T282
Test name
Test status
Simulation time 182010786346 ps
CPU time 205.76 seconds
Started Jul 12 05:07:27 PM PDT 24
Finished Jul 12 05:10:54 PM PDT 24
Peak memory 201952 kb
Host smart-2734ccfb-2cac-4af1-b4e9-dfe98c319a7c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020321593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2020321593
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2792133796
Short name T351
Test name
Test status
Simulation time 200109393137 ps
CPU time 245.13 seconds
Started Jul 12 05:07:26 PM PDT 24
Finished Jul 12 05:11:33 PM PDT 24
Peak memory 201708 kb
Host smart-0653ca98-9b9b-4da6-9d32-3525dca46578
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792133796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2792133796
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3463516823
Short name T590
Test name
Test status
Simulation time 132235185775 ps
CPU time 444.47 seconds
Started Jul 12 05:12:41 PM PDT 24
Finished Jul 12 05:20:06 PM PDT 24
Peak memory 202188 kb
Host smart-7e89f18c-e31a-4489-ae7a-91d9ca8ea2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463516823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3463516823
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1686696232
Short name T439
Test name
Test status
Simulation time 45200634024 ps
CPU time 100 seconds
Started Jul 12 05:12:12 PM PDT 24
Finished Jul 12 05:13:55 PM PDT 24
Peak memory 201584 kb
Host smart-a74b173d-a6d6-4760-8c75-8078307303fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686696232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1686696232
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2762860755
Short name T690
Test name
Test status
Simulation time 5304932143 ps
CPU time 3.04 seconds
Started Jul 12 05:12:06 PM PDT 24
Finished Jul 12 05:12:10 PM PDT 24
Peak memory 201624 kb
Host smart-2036a170-38c8-4713-a4b1-e2ae0f5ca8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762860755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2762860755
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.4068176099
Short name T374
Test name
Test status
Simulation time 5944239406 ps
CPU time 3.95 seconds
Started Jul 12 05:07:17 PM PDT 24
Finished Jul 12 05:07:22 PM PDT 24
Peak memory 201688 kb
Host smart-d364db6f-a729-48e3-8662-8306ca8d280c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068176099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.4068176099
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2051725634
Short name T246
Test name
Test status
Simulation time 176867411839 ps
CPU time 54.41 seconds
Started Jul 12 05:18:30 PM PDT 24
Finished Jul 12 05:19:25 PM PDT 24
Peak memory 201912 kb
Host smart-19f011e6-acb0-4b02-947a-099b18a88d05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051725634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2051725634
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.317052562
Short name T800
Test name
Test status
Simulation time 162968033739 ps
CPU time 212.91 seconds
Started Jul 12 05:07:28 PM PDT 24
Finished Jul 12 05:11:02 PM PDT 24
Peak memory 211432 kb
Host smart-88bbbe35-be94-4e1c-b759-b450616a0d56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317052562 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.317052562
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.390354639
Short name T571
Test name
Test status
Simulation time 384009491 ps
CPU time 1.4 seconds
Started Jul 12 05:07:32 PM PDT 24
Finished Jul 12 05:07:34 PM PDT 24
Peak memory 201508 kb
Host smart-44442a8b-9037-4a13-8e70-a84ed91d0002
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390354639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.390354639
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2844202797
Short name T250
Test name
Test status
Simulation time 193481932212 ps
CPU time 67.23 seconds
Started Jul 12 05:07:32 PM PDT 24
Finished Jul 12 05:08:40 PM PDT 24
Peak memory 201768 kb
Host smart-b9f3f802-9bfc-4b27-a8b0-5312a1e814c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844202797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2844202797
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1208736167
Short name T793
Test name
Test status
Simulation time 164269617373 ps
CPU time 349.16 seconds
Started Jul 12 05:07:26 PM PDT 24
Finished Jul 12 05:13:16 PM PDT 24
Peak memory 201804 kb
Host smart-a8c986a1-12b9-4e6f-a569-f2768169909a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208736167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1208736167
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.712885320
Short name T532
Test name
Test status
Simulation time 164194211843 ps
CPU time 183.08 seconds
Started Jul 12 05:07:24 PM PDT 24
Finished Jul 12 05:10:28 PM PDT 24
Peak memory 201824 kb
Host smart-8af0e6ef-ef16-498f-b77b-3ad48ce4bbdf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=712885320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.712885320
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3416537096
Short name T576
Test name
Test status
Simulation time 168947066661 ps
CPU time 365.75 seconds
Started Jul 12 05:07:25 PM PDT 24
Finished Jul 12 05:13:32 PM PDT 24
Peak memory 201908 kb
Host smart-01c78044-22eb-475d-b81c-35dc9524ebfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416537096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3416537096
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2192281411
Short name T450
Test name
Test status
Simulation time 163165975965 ps
CPU time 183.41 seconds
Started Jul 12 05:07:26 PM PDT 24
Finished Jul 12 05:10:31 PM PDT 24
Peak memory 201728 kb
Host smart-a2fffb3c-ccdf-44fb-873a-1ae0e82e97b3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192281411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2192281411
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.196840526
Short name T661
Test name
Test status
Simulation time 400064570347 ps
CPU time 977.54 seconds
Started Jul 12 05:07:36 PM PDT 24
Finished Jul 12 05:23:54 PM PDT 24
Peak memory 201876 kb
Host smart-429d7e2b-0ba2-4759-a97e-d727bf753c07
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196840526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
adc_ctrl_filters_wakeup_fixed.196840526
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1327157617
Short name T510
Test name
Test status
Simulation time 24636674884 ps
CPU time 10.04 seconds
Started Jul 12 05:07:33 PM PDT 24
Finished Jul 12 05:07:44 PM PDT 24
Peak memory 201656 kb
Host smart-16b0e12c-e04f-4ceb-b531-d248aa5c23e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327157617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1327157617
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1846801487
Short name T384
Test name
Test status
Simulation time 5450981836 ps
CPU time 3.73 seconds
Started Jul 12 05:07:34 PM PDT 24
Finished Jul 12 05:07:38 PM PDT 24
Peak memory 201904 kb
Host smart-4c6871d5-6a62-4400-b398-b7200985808e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846801487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1846801487
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.178901191
Short name T431
Test name
Test status
Simulation time 5880076355 ps
CPU time 3.83 seconds
Started Jul 12 06:12:32 PM PDT 24
Finished Jul 12 06:14:03 PM PDT 24
Peak memory 201672 kb
Host smart-61c65f90-64e5-4bc8-85a4-d0033f1c97b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178901191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.178901191
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3558457468
Short name T749
Test name
Test status
Simulation time 342683128450 ps
CPU time 100.83 seconds
Started Jul 12 05:07:33 PM PDT 24
Finished Jul 12 05:09:15 PM PDT 24
Peak memory 201928 kb
Host smart-b0437b62-eb63-4858-976d-fd10ae489288
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558457468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3558457468
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3425252768
Short name T636
Test name
Test status
Simulation time 702731530595 ps
CPU time 402.92 seconds
Started Jul 12 05:09:46 PM PDT 24
Finished Jul 12 05:16:29 PM PDT 24
Peak memory 210536 kb
Host smart-460eb7fa-d069-4e0e-a53c-acb81165936e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425252768 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3425252768
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.800456546
Short name T699
Test name
Test status
Simulation time 309821687 ps
CPU time 0.94 seconds
Started Jul 12 05:07:39 PM PDT 24
Finished Jul 12 05:07:41 PM PDT 24
Peak memory 201604 kb
Host smart-f749a66d-1b06-4634-8b3e-38a31b9425f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800456546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.800456546
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3531979607
Short name T178
Test name
Test status
Simulation time 177785506919 ps
CPU time 84.45 seconds
Started Jul 12 05:07:39 PM PDT 24
Finished Jul 12 05:09:05 PM PDT 24
Peak memory 201912 kb
Host smart-a5ea55ca-3992-43d5-aa9d-3354ed006fc4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531979607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3531979607
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.503282173
Short name T298
Test name
Test status
Simulation time 331611822799 ps
CPU time 211.76 seconds
Started Jul 12 05:07:39 PM PDT 24
Finished Jul 12 05:11:12 PM PDT 24
Peak memory 201804 kb
Host smart-49666feb-8973-4b84-9cbb-40431691b761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503282173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.503282173
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2034843178
Short name T196
Test name
Test status
Simulation time 165897951387 ps
CPU time 360.18 seconds
Started Jul 12 05:07:36 PM PDT 24
Finished Jul 12 05:13:37 PM PDT 24
Peak memory 202152 kb
Host smart-d94aa1aa-265a-4cdb-b084-bdbb9ce0f2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034843178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2034843178
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3710568966
Short name T368
Test name
Test status
Simulation time 337110007315 ps
CPU time 86.27 seconds
Started Jul 12 05:07:38 PM PDT 24
Finished Jul 12 05:09:06 PM PDT 24
Peak memory 201872 kb
Host smart-f63d8624-f149-4a08-9aef-539ef0457c94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710568966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3710568966
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.4062316721
Short name T759
Test name
Test status
Simulation time 168783810312 ps
CPU time 186.32 seconds
Started Jul 12 05:07:36 PM PDT 24
Finished Jul 12 05:10:43 PM PDT 24
Peak memory 201860 kb
Host smart-8d4258e0-6960-4857-92c7-61a881f344e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062316721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.4062316721
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.225429241
Short name T81
Test name
Test status
Simulation time 330725232819 ps
CPU time 811.76 seconds
Started Jul 12 05:07:33 PM PDT 24
Finished Jul 12 05:21:06 PM PDT 24
Peak memory 201964 kb
Host smart-dec9fe20-f6f3-40a5-b835-e30cee7b3ae8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=225429241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixe
d.225429241
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2743600981
Short name T105
Test name
Test status
Simulation time 184232186107 ps
CPU time 85.81 seconds
Started Jul 12 05:07:39 PM PDT 24
Finished Jul 12 05:09:06 PM PDT 24
Peak memory 201860 kb
Host smart-b1b1e183-da8c-44f5-aa3c-11573d71e136
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743600981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2743600981
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.890351183
Short name T798
Test name
Test status
Simulation time 209083298108 ps
CPU time 449.85 seconds
Started Jul 12 05:07:42 PM PDT 24
Finished Jul 12 05:15:13 PM PDT 24
Peak memory 202048 kb
Host smart-1ad6fe3e-4690-4338-a3f9-65826defc514
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890351183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.890351183
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.4065520011
Short name T2
Test name
Test status
Simulation time 118810786899 ps
CPU time 406.09 seconds
Started Jul 12 05:07:38 PM PDT 24
Finished Jul 12 05:14:25 PM PDT 24
Peak memory 202216 kb
Host smart-381d876d-935e-4978-b409-4a38e502deeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065520011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.4065520011
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2079354948
Short name T496
Test name
Test status
Simulation time 27915122234 ps
CPU time 16.19 seconds
Started Jul 12 05:07:38 PM PDT 24
Finished Jul 12 05:07:54 PM PDT 24
Peak memory 201900 kb
Host smart-54b077fe-f1f0-4ca1-9d7c-c29f3c3b42c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079354948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2079354948
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2831138015
Short name T410
Test name
Test status
Simulation time 4636722136 ps
CPU time 12.22 seconds
Started Jul 12 05:07:38 PM PDT 24
Finished Jul 12 05:07:51 PM PDT 24
Peak memory 201612 kb
Host smart-25b32819-5166-4397-a721-dc9c9b540d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831138015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2831138015
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2515180775
Short name T616
Test name
Test status
Simulation time 5583547062 ps
CPU time 14.17 seconds
Started Jul 12 05:07:33 PM PDT 24
Finished Jul 12 05:07:48 PM PDT 24
Peak memory 201692 kb
Host smart-0cd59535-d415-4634-89a7-767f2fa0b573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515180775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2515180775
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1542614178
Short name T18
Test name
Test status
Simulation time 85974855640 ps
CPU time 46.51 seconds
Started Jul 12 05:07:38 PM PDT 24
Finished Jul 12 05:08:25 PM PDT 24
Peak memory 210076 kb
Host smart-57ed26d7-8c97-4336-bd81-62b7c783bd90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542614178 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1542614178
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1816947189
Short name T406
Test name
Test status
Simulation time 315971994 ps
CPU time 0.83 seconds
Started Jul 12 05:04:11 PM PDT 24
Finished Jul 12 05:04:13 PM PDT 24
Peak memory 201620 kb
Host smart-8d4399b0-8dd4-4da5-98b3-190758002bc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816947189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1816947189
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3585327583
Short name T225
Test name
Test status
Simulation time 354679499626 ps
CPU time 815.56 seconds
Started Jul 12 05:04:07 PM PDT 24
Finished Jul 12 05:17:44 PM PDT 24
Peak memory 201792 kb
Host smart-5f6e012a-d50b-4996-acc5-d30d6cb1fd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585327583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3585327583
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1579692889
Short name T736
Test name
Test status
Simulation time 326244019658 ps
CPU time 784.63 seconds
Started Jul 12 05:04:12 PM PDT 24
Finished Jul 12 05:17:17 PM PDT 24
Peak memory 200592 kb
Host smart-81437b99-65dd-4266-a181-89c3972ba116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579692889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1579692889
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2726219813
Short name T743
Test name
Test status
Simulation time 160588579967 ps
CPU time 173.04 seconds
Started Jul 12 05:04:07 PM PDT 24
Finished Jul 12 05:07:02 PM PDT 24
Peak memory 201764 kb
Host smart-d87f31d7-5b4b-4478-9f93-4692c56a4656
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726219813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2726219813
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3463874187
Short name T797
Test name
Test status
Simulation time 322713447907 ps
CPU time 744 seconds
Started Jul 12 05:04:12 PM PDT 24
Finished Jul 12 05:16:37 PM PDT 24
Peak memory 201860 kb
Host smart-5ed1245b-a600-4720-9bc7-e0c4e31f747b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463874187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3463874187
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2428959325
Short name T458
Test name
Test status
Simulation time 160843552041 ps
CPU time 107.06 seconds
Started Jul 12 05:04:06 PM PDT 24
Finished Jul 12 05:05:54 PM PDT 24
Peak memory 201940 kb
Host smart-64e8ab48-a386-4c8d-be70-8280d9d89e70
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428959325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2428959325
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1916471798
Short name T421
Test name
Test status
Simulation time 168877936478 ps
CPU time 98.85 seconds
Started Jul 12 05:04:12 PM PDT 24
Finished Jul 12 05:05:52 PM PDT 24
Peak memory 201680 kb
Host smart-ae0608e7-7f9c-49df-a5d7-2596770ce052
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916471798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1916471798
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1408838114
Short name T382
Test name
Test status
Simulation time 191182274409 ps
CPU time 121.85 seconds
Started Jul 12 05:04:10 PM PDT 24
Finished Jul 12 05:06:13 PM PDT 24
Peak memory 201736 kb
Host smart-7f871320-13d5-4486-acd0-ace76cdddae0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408838114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.1408838114
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3835764286
Short name T772
Test name
Test status
Simulation time 158993735052 ps
CPU time 408.46 seconds
Started Jul 12 05:04:12 PM PDT 24
Finished Jul 12 05:11:02 PM PDT 24
Peak memory 202340 kb
Host smart-d89ab99b-27fc-415b-93bb-cfa2307bd23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835764286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3835764286
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1588835339
Short name T617
Test name
Test status
Simulation time 28922822607 ps
CPU time 16 seconds
Started Jul 12 05:04:12 PM PDT 24
Finished Jul 12 05:04:30 PM PDT 24
Peak memory 201480 kb
Host smart-5c47c732-25b7-4ea5-812d-16f9a6aa7b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588835339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1588835339
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.514211274
Short name T651
Test name
Test status
Simulation time 5457246526 ps
CPU time 6.44 seconds
Started Jul 12 05:04:07 PM PDT 24
Finished Jul 12 05:04:14 PM PDT 24
Peak memory 201692 kb
Host smart-e7172fb2-bd8a-417a-9073-6f7b454331bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514211274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.514211274
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1420253991
Short name T74
Test name
Test status
Simulation time 3844130572 ps
CPU time 5.81 seconds
Started Jul 12 05:04:08 PM PDT 24
Finished Jul 12 05:04:15 PM PDT 24
Peak memory 217092 kb
Host smart-4ca598b1-7ce1-48fa-8da1-e597020cf03c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420253991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1420253991
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.802436128
Short name T593
Test name
Test status
Simulation time 5484064956 ps
CPU time 3.43 seconds
Started Jul 12 05:04:11 PM PDT 24
Finished Jul 12 05:04:16 PM PDT 24
Peak memory 201472 kb
Host smart-fcc9bda3-1e76-429a-9387-f552c9c6d6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802436128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.802436128
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2810945068
Short name T602
Test name
Test status
Simulation time 489101320 ps
CPU time 1.14 seconds
Started Jul 12 05:07:55 PM PDT 24
Finished Jul 12 05:07:57 PM PDT 24
Peak memory 201608 kb
Host smart-9681bcd8-d51c-4456-a4d0-ea964a10f48b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810945068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2810945068
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2126050093
Short name T622
Test name
Test status
Simulation time 207802814610 ps
CPU time 230.77 seconds
Started Jul 12 05:07:52 PM PDT 24
Finished Jul 12 05:11:44 PM PDT 24
Peak memory 201780 kb
Host smart-f8427619-ad05-4d1e-bf94-8ded2cf8a799
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126050093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2126050093
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2653230007
Short name T294
Test name
Test status
Simulation time 531255347550 ps
CPU time 318.59 seconds
Started Jul 12 05:07:51 PM PDT 24
Finished Jul 12 05:13:10 PM PDT 24
Peak memory 201904 kb
Host smart-fc6b9c3b-2d0c-42d7-a0cb-0eb039ee22e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653230007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2653230007
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3807141642
Short name T538
Test name
Test status
Simulation time 325231271613 ps
CPU time 785.45 seconds
Started Jul 12 05:07:43 PM PDT 24
Finished Jul 12 05:20:49 PM PDT 24
Peak memory 201860 kb
Host smart-68b00877-84eb-4845-81bd-b63b227e2722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807141642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3807141642
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2555228288
Short name T463
Test name
Test status
Simulation time 491399999414 ps
CPU time 1168.82 seconds
Started Jul 12 05:07:52 PM PDT 24
Finished Jul 12 05:27:22 PM PDT 24
Peak memory 201868 kb
Host smart-bcf2c481-2314-475d-b85d-8ff18d9191ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555228288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2555228288
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3159181737
Short name T135
Test name
Test status
Simulation time 165281281040 ps
CPU time 371.46 seconds
Started Jul 12 05:07:51 PM PDT 24
Finished Jul 12 05:14:03 PM PDT 24
Peak memory 201904 kb
Host smart-45c193ec-69c0-4d91-be70-5ce7b8ea2f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159181737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3159181737
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3570973096
Short name T177
Test name
Test status
Simulation time 333094060158 ps
CPU time 734.21 seconds
Started Jul 12 05:07:45 PM PDT 24
Finished Jul 12 05:19:59 PM PDT 24
Peak memory 201928 kb
Host smart-6f9f4479-189d-4038-b254-a381ea6bc8d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570973096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3570973096
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1545908037
Short name T747
Test name
Test status
Simulation time 395506802451 ps
CPU time 211.09 seconds
Started Jul 12 05:07:49 PM PDT 24
Finished Jul 12 05:11:21 PM PDT 24
Peak memory 201892 kb
Host smart-79dbe849-acbf-4533-895c-243d1373188a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545908037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1545908037
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2576189241
Short name T659
Test name
Test status
Simulation time 608438926495 ps
CPU time 1122.54 seconds
Started Jul 12 05:07:54 PM PDT 24
Finished Jul 12 05:26:38 PM PDT 24
Peak memory 201728 kb
Host smart-54f39a13-29fe-4e82-b894-6bcee76a0c68
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576189241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2576189241
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1377618155
Short name T202
Test name
Test status
Simulation time 105177068919 ps
CPU time 367.08 seconds
Started Jul 12 05:07:51 PM PDT 24
Finished Jul 12 05:13:59 PM PDT 24
Peak memory 202180 kb
Host smart-4b29a838-2434-4436-ad92-6d20d4129969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377618155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1377618155
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1004485833
Short name T689
Test name
Test status
Simulation time 40871168490 ps
CPU time 25.47 seconds
Started Jul 12 05:07:51 PM PDT 24
Finished Jul 12 05:08:17 PM PDT 24
Peak memory 201696 kb
Host smart-dfd9f1ca-8bb1-473b-9955-c709ed349118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004485833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1004485833
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.4072243565
Short name T645
Test name
Test status
Simulation time 3702868282 ps
CPU time 2.66 seconds
Started Jul 12 05:07:51 PM PDT 24
Finished Jul 12 05:07:55 PM PDT 24
Peak memory 201668 kb
Host smart-34a1f85a-1e96-4d21-9700-59a8d8314666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072243565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.4072243565
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3733769833
Short name T370
Test name
Test status
Simulation time 6016798049 ps
CPU time 14.35 seconds
Started Jul 12 05:07:38 PM PDT 24
Finished Jul 12 05:07:54 PM PDT 24
Peak memory 201692 kb
Host smart-297885fc-73ee-4cce-b5e8-0af10df80316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733769833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3733769833
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3277630174
Short name T141
Test name
Test status
Simulation time 334339776661 ps
CPU time 767.45 seconds
Started Jul 12 05:07:52 PM PDT 24
Finished Jul 12 05:20:41 PM PDT 24
Peak memory 201892 kb
Host smart-ae641ce0-cbe6-472f-aa53-f1d38e188426
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277630174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3277630174
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.730136845
Short name T268
Test name
Test status
Simulation time 53220218940 ps
CPU time 112.8 seconds
Started Jul 12 05:07:53 PM PDT 24
Finished Jul 12 05:09:47 PM PDT 24
Peak memory 218540 kb
Host smart-331df6af-0cd9-473f-92ce-47a62fb6964f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730136845 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.730136845
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2005178223
Short name T381
Test name
Test status
Simulation time 459416235 ps
CPU time 1.64 seconds
Started Jul 12 05:08:05 PM PDT 24
Finished Jul 12 05:08:08 PM PDT 24
Peak memory 201640 kb
Host smart-9d185a94-9aa0-4b0e-9ada-0cee1032d85a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005178223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2005178223
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2260282921
Short name T312
Test name
Test status
Simulation time 518395845446 ps
CPU time 783.87 seconds
Started Jul 12 05:07:59 PM PDT 24
Finished Jul 12 05:21:04 PM PDT 24
Peak memory 201800 kb
Host smart-c55fb1e0-8241-40bc-98fc-7361c1c472ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260282921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2260282921
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1994828928
Short name T650
Test name
Test status
Simulation time 321309467193 ps
CPU time 362.44 seconds
Started Jul 12 05:08:00 PM PDT 24
Finished Jul 12 05:14:03 PM PDT 24
Peak memory 202152 kb
Host smart-74bef074-7db5-4e21-8de9-e947fc4efdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994828928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1994828928
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2559226019
Short name T517
Test name
Test status
Simulation time 329750082998 ps
CPU time 370.25 seconds
Started Jul 12 05:08:00 PM PDT 24
Finished Jul 12 05:14:11 PM PDT 24
Peak memory 201884 kb
Host smart-a9e52106-11f2-4b69-8841-34768c1e54f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559226019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2559226019
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3633371138
Short name T364
Test name
Test status
Simulation time 162187221018 ps
CPU time 366.33 seconds
Started Jul 12 05:07:59 PM PDT 24
Finished Jul 12 05:14:06 PM PDT 24
Peak memory 201840 kb
Host smart-95d00544-1d86-42ec-b912-62340a9b2d29
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633371138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3633371138
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3131751987
Short name T281
Test name
Test status
Simulation time 207957493606 ps
CPU time 118.46 seconds
Started Jul 12 05:07:57 PM PDT 24
Finished Jul 12 05:09:56 PM PDT 24
Peak memory 201960 kb
Host smart-97f2c37f-0aa6-45d1-b4c4-b0c055a40c57
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131751987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3131751987
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1053544613
Short name T407
Test name
Test status
Simulation time 396075733303 ps
CPU time 213.15 seconds
Started Jul 12 05:07:59 PM PDT 24
Finished Jul 12 05:11:33 PM PDT 24
Peak memory 201864 kb
Host smart-5afe4409-fe6c-46a8-951a-3a467c44cc07
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053544613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1053544613
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3871925959
Short name T104
Test name
Test status
Simulation time 136093181916 ps
CPU time 499.7 seconds
Started Jul 12 05:08:01 PM PDT 24
Finished Jul 12 05:16:21 PM PDT 24
Peak memory 202220 kb
Host smart-c37a0e12-79e9-4f31-a83a-67695edc68bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871925959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3871925959
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1454555378
Short name T376
Test name
Test status
Simulation time 36424709585 ps
CPU time 60.03 seconds
Started Jul 12 05:07:59 PM PDT 24
Finished Jul 12 05:09:00 PM PDT 24
Peak memory 201680 kb
Host smart-9ef5e2ff-efaa-49a6-a205-caa48e235974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454555378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1454555378
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.4046347696
Short name T79
Test name
Test status
Simulation time 4726211025 ps
CPU time 3.65 seconds
Started Jul 12 05:07:58 PM PDT 24
Finished Jul 12 05:08:04 PM PDT 24
Peak memory 201668 kb
Host smart-e9df809a-3691-447f-a591-dc041f8b6ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046347696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.4046347696
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.324800634
Short name T418
Test name
Test status
Simulation time 5977771216 ps
CPU time 3.84 seconds
Started Jul 12 05:07:54 PM PDT 24
Finished Jul 12 05:07:59 PM PDT 24
Peak memory 201660 kb
Host smart-92a882e5-70c5-41c1-8117-57d36d201b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324800634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.324800634
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1926032441
Short name T226
Test name
Test status
Simulation time 495129567309 ps
CPU time 301.35 seconds
Started Jul 12 05:08:00 PM PDT 24
Finished Jul 12 05:13:02 PM PDT 24
Peak memory 201904 kb
Host smart-965435a8-5e37-45d1-8f44-7028a71159fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926032441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1926032441
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.543048853
Short name T653
Test name
Test status
Simulation time 48239158311 ps
CPU time 23.9 seconds
Started Jul 12 05:07:58 PM PDT 24
Finished Jul 12 05:08:23 PM PDT 24
Peak memory 201960 kb
Host smart-acd9ea18-5739-47da-90c0-e92d2d8fb23d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543048853 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.543048853
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1202058326
Short name T493
Test name
Test status
Simulation time 312077781 ps
CPU time 0.84 seconds
Started Jul 12 05:08:19 PM PDT 24
Finished Jul 12 05:08:21 PM PDT 24
Peak memory 201528 kb
Host smart-2e1d5d26-90eb-4f25-ac4a-e3eafc4efa9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202058326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1202058326
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2472475420
Short name T644
Test name
Test status
Simulation time 506825395520 ps
CPU time 773.43 seconds
Started Jul 12 05:08:11 PM PDT 24
Finished Jul 12 05:21:05 PM PDT 24
Peak memory 201748 kb
Host smart-3a329900-6f0c-4b8d-982a-d9af6738ecf5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472475420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2472475420
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.404746422
Short name T242
Test name
Test status
Simulation time 364719152473 ps
CPU time 111.74 seconds
Started Jul 12 05:08:18 PM PDT 24
Finished Jul 12 05:10:10 PM PDT 24
Peak memory 201972 kb
Host smart-93dec143-e6c9-43a0-8728-ce32f41b8075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404746422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.404746422
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3567624396
Short name T153
Test name
Test status
Simulation time 320277615305 ps
CPU time 188.73 seconds
Started Jul 12 05:08:11 PM PDT 24
Finished Jul 12 05:11:20 PM PDT 24
Peak memory 201820 kb
Host smart-f7926aed-6294-4aad-bcff-ee588579a4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567624396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3567624396
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3231958050
Short name T403
Test name
Test status
Simulation time 484299338707 ps
CPU time 298.45 seconds
Started Jul 12 05:08:11 PM PDT 24
Finished Jul 12 05:13:10 PM PDT 24
Peak memory 201924 kb
Host smart-07977814-59c3-45a6-b25d-657a6601af46
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231958050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3231958050
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.4290125751
Short name T264
Test name
Test status
Simulation time 496957649973 ps
CPU time 278.36 seconds
Started Jul 12 05:08:06 PM PDT 24
Finished Jul 12 05:12:45 PM PDT 24
Peak memory 202112 kb
Host smart-697200b8-99bc-41d3-b9d3-adc75dd36a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290125751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.4290125751
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2518821980
Short name T455
Test name
Test status
Simulation time 487811057887 ps
CPU time 1087.01 seconds
Started Jul 12 05:08:10 PM PDT 24
Finished Jul 12 05:26:18 PM PDT 24
Peak memory 201860 kb
Host smart-11b6c924-8ec5-4a2d-9be2-647c25a6282b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518821980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2518821980
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1041934260
Short name T262
Test name
Test status
Simulation time 363181465982 ps
CPU time 415.59 seconds
Started Jul 12 05:08:12 PM PDT 24
Finished Jul 12 05:15:08 PM PDT 24
Peak memory 202036 kb
Host smart-b07dfad7-e72a-4971-ab18-55b38538a0dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041934260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1041934260
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.102806739
Short name T150
Test name
Test status
Simulation time 598330064830 ps
CPU time 194.78 seconds
Started Jul 12 05:08:10 PM PDT 24
Finished Jul 12 05:11:25 PM PDT 24
Peak memory 201888 kb
Host smart-138afbe3-c65d-4705-996f-d143e442d191
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102806739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
adc_ctrl_filters_wakeup_fixed.102806739
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2655436978
Short name T613
Test name
Test status
Simulation time 84858764094 ps
CPU time 483.65 seconds
Started Jul 12 05:08:18 PM PDT 24
Finished Jul 12 05:16:22 PM PDT 24
Peak memory 202444 kb
Host smart-1acd92b0-ced2-4afc-8dec-49dd57ff0587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655436978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2655436978
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2345101332
Short name T453
Test name
Test status
Simulation time 27293549002 ps
CPU time 61.49 seconds
Started Jul 12 05:08:20 PM PDT 24
Finished Jul 12 05:09:22 PM PDT 24
Peak memory 201612 kb
Host smart-e1c30b95-d806-4b17-a5eb-85826a881427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345101332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2345101332
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.971675864
Short name T348
Test name
Test status
Simulation time 5197806557 ps
CPU time 3.74 seconds
Started Jul 12 05:08:16 PM PDT 24
Finished Jul 12 05:08:21 PM PDT 24
Peak memory 201696 kb
Host smart-b804db6b-17cc-4638-850a-8b40fc31ee9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971675864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.971675864
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1082170977
Short name T433
Test name
Test status
Simulation time 5984519579 ps
CPU time 3.44 seconds
Started Jul 12 05:08:05 PM PDT 24
Finished Jul 12 05:08:09 PM PDT 24
Peak memory 201508 kb
Host smart-df37efbc-07ac-4e9d-8135-5aaddbd06db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082170977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1082170977
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1205817061
Short name T668
Test name
Test status
Simulation time 200962953763 ps
CPU time 220.63 seconds
Started Jul 12 05:08:18 PM PDT 24
Finished Jul 12 05:11:59 PM PDT 24
Peak memory 201700 kb
Host smart-c6305780-2b3f-4c19-ab90-adf9276c643b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205817061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1205817061
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.197714774
Short name T313
Test name
Test status
Simulation time 118533269826 ps
CPU time 387.92 seconds
Started Jul 12 05:08:16 PM PDT 24
Finished Jul 12 05:14:45 PM PDT 24
Peak memory 210580 kb
Host smart-ec5a88ac-2bb0-45f1-ac90-fcb3e89921a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197714774 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.197714774
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2765480055
Short name T562
Test name
Test status
Simulation time 415053346 ps
CPU time 0.77 seconds
Started Jul 12 05:08:36 PM PDT 24
Finished Jul 12 05:08:37 PM PDT 24
Peak memory 201540 kb
Host smart-44172f0d-4249-4614-939c-edf1e690a889
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765480055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2765480055
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3611764627
Short name T280
Test name
Test status
Simulation time 408667033244 ps
CPU time 104.63 seconds
Started Jul 12 05:08:24 PM PDT 24
Finished Jul 12 05:10:09 PM PDT 24
Peak memory 201776 kb
Host smart-d0f51493-30bf-469d-8790-60697756b622
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611764627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3611764627
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2994913288
Short name T604
Test name
Test status
Simulation time 334468297428 ps
CPU time 70.74 seconds
Started Jul 12 05:08:24 PM PDT 24
Finished Jul 12 05:09:35 PM PDT 24
Peak memory 201800 kb
Host smart-8e54cc4b-4a5d-4bc8-a418-c4af5e63b65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994913288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2994913288
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3568543936
Short name T751
Test name
Test status
Simulation time 164998159387 ps
CPU time 88.02 seconds
Started Jul 12 05:08:24 PM PDT 24
Finished Jul 12 05:09:52 PM PDT 24
Peak memory 201812 kb
Host smart-8910d19a-8da4-406a-9039-c36bb070a757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568543936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3568543936
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.684012064
Short name T594
Test name
Test status
Simulation time 320295203022 ps
CPU time 694.53 seconds
Started Jul 12 05:08:34 PM PDT 24
Finished Jul 12 05:20:09 PM PDT 24
Peak memory 201760 kb
Host smart-2f45d21c-aad6-41bc-a435-273b547fd964
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=684012064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.684012064
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3445008318
Short name T707
Test name
Test status
Simulation time 166633577969 ps
CPU time 354.44 seconds
Started Jul 12 05:08:33 PM PDT 24
Finished Jul 12 05:14:28 PM PDT 24
Peak memory 201800 kb
Host smart-b9d3b2e6-f7f5-4db3-abd0-3597b6927026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445008318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3445008318
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1464676856
Short name T505
Test name
Test status
Simulation time 167967846576 ps
CPU time 200.78 seconds
Started Jul 12 05:08:27 PM PDT 24
Finished Jul 12 05:11:48 PM PDT 24
Peak memory 201876 kb
Host smart-1e0ff597-f317-4607-aac6-ae501f81bc1b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464676856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1464676856
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2408272134
Short name T685
Test name
Test status
Simulation time 585079118491 ps
CPU time 1339.49 seconds
Started Jul 12 05:08:25 PM PDT 24
Finished Jul 12 05:30:44 PM PDT 24
Peak memory 201896 kb
Host smart-f717ee02-d18c-4f19-a576-e97f031e6328
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408272134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2408272134
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2787537835
Short name T401
Test name
Test status
Simulation time 215240026139 ps
CPU time 118.82 seconds
Started Jul 12 05:08:34 PM PDT 24
Finished Jul 12 05:10:34 PM PDT 24
Peak memory 201768 kb
Host smart-ec824663-99c6-4339-9f93-7d0c345724c1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787537835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2787537835
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.218967155
Short name T334
Test name
Test status
Simulation time 132400514215 ps
CPU time 399.62 seconds
Started Jul 12 05:08:25 PM PDT 24
Finished Jul 12 05:15:05 PM PDT 24
Peak memory 202284 kb
Host smart-67e8a75a-a4bf-493a-af0f-9c41efa135fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218967155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.218967155
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.2414783817
Short name T36
Test name
Test status
Simulation time 46581595410 ps
CPU time 53.71 seconds
Started Jul 12 05:08:32 PM PDT 24
Finished Jul 12 05:09:26 PM PDT 24
Peak memory 201592 kb
Host smart-74104b3c-4e7f-49ce-bd5f-6b9a40a78efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414783817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2414783817
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2505023506
Short name T345
Test name
Test status
Simulation time 5244996065 ps
CPU time 11.07 seconds
Started Jul 12 05:08:27 PM PDT 24
Finished Jul 12 05:08:38 PM PDT 24
Peak memory 201672 kb
Host smart-6f561e0f-28ba-469d-b069-89d6cd36c1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505023506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2505023506
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.162973973
Short name T340
Test name
Test status
Simulation time 6112734722 ps
CPU time 7.26 seconds
Started Jul 12 05:08:35 PM PDT 24
Finished Jul 12 05:08:43 PM PDT 24
Peak memory 201592 kb
Host smart-d0dcdc89-8764-47e3-9a60-e0f59d30867b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162973973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.162973973
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1137397974
Short name T155
Test name
Test status
Simulation time 396505740592 ps
CPU time 914.1 seconds
Started Jul 12 05:08:22 PM PDT 24
Finished Jul 12 05:23:37 PM PDT 24
Peak memory 201860 kb
Host smart-7b9f2499-d31a-43b0-87b1-e5f81e51a9fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137397974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1137397974
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2905320829
Short name T790
Test name
Test status
Simulation time 10628209290 ps
CPU time 43.55 seconds
Started Jul 12 05:08:23 PM PDT 24
Finished Jul 12 05:09:07 PM PDT 24
Peak memory 210192 kb
Host smart-43efc9b8-d70d-44f1-9a83-0bfd41b48b23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905320829 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.2905320829
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.161450923
Short name T530
Test name
Test status
Simulation time 430495356 ps
CPU time 1.64 seconds
Started Jul 12 05:08:36 PM PDT 24
Finished Jul 12 05:08:38 PM PDT 24
Peak memory 201652 kb
Host smart-5420df10-7d09-4768-b854-5b7a7304cf34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161450923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.161450923
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.749131744
Short name T728
Test name
Test status
Simulation time 334581671225 ps
CPU time 436.22 seconds
Started Jul 12 05:08:30 PM PDT 24
Finished Jul 12 05:15:47 PM PDT 24
Peak memory 201880 kb
Host smart-0399e6b7-6eea-46a1-962d-fcce6a701229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749131744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.749131744
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2501379761
Short name T152
Test name
Test status
Simulation time 490669224488 ps
CPU time 235.99 seconds
Started Jul 12 05:08:33 PM PDT 24
Finished Jul 12 05:12:29 PM PDT 24
Peak memory 201728 kb
Host smart-0ba783f5-7c62-46fb-8ac6-73054c35c06a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501379761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2501379761
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.532293003
Short name T566
Test name
Test status
Simulation time 488718856248 ps
CPU time 1030.3 seconds
Started Jul 12 05:08:30 PM PDT 24
Finished Jul 12 05:25:41 PM PDT 24
Peak memory 201808 kb
Host smart-7dbd8ca2-7825-40c0-a319-6b2855837d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532293003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.532293003
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.4097819582
Short name T698
Test name
Test status
Simulation time 332354036995 ps
CPU time 198.41 seconds
Started Jul 12 05:08:29 PM PDT 24
Finished Jul 12 05:11:48 PM PDT 24
Peak memory 201840 kb
Host smart-3e0894f1-257b-410f-9678-e645ad956941
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097819582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.4097819582
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3439056608
Short name T667
Test name
Test status
Simulation time 194791488984 ps
CPU time 85.14 seconds
Started Jul 12 05:08:29 PM PDT 24
Finished Jul 12 05:09:55 PM PDT 24
Peak memory 201836 kb
Host smart-e8aed0e1-4b67-4a33-8acb-baf8b919c78b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439056608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3439056608
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1268345569
Short name T740
Test name
Test status
Simulation time 40534474081 ps
CPU time 11.4 seconds
Started Jul 12 05:08:35 PM PDT 24
Finished Jul 12 05:08:46 PM PDT 24
Peak memory 201696 kb
Host smart-b4180a98-aeac-4b13-beac-a15197641c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268345569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1268345569
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2116420560
Short name T357
Test name
Test status
Simulation time 4227844623 ps
CPU time 3.12 seconds
Started Jul 12 05:08:29 PM PDT 24
Finished Jul 12 05:08:33 PM PDT 24
Peak memory 201728 kb
Host smart-c6bff7b0-23b5-443f-b203-213ef7afdf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116420560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2116420560
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1057189008
Short name T619
Test name
Test status
Simulation time 6154996567 ps
CPU time 4.42 seconds
Started Jul 12 05:08:28 PM PDT 24
Finished Jul 12 05:08:33 PM PDT 24
Peak memory 201672 kb
Host smart-225c0495-5dba-4ae0-830e-0fc90a1d2f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057189008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1057189008
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1457269186
Short name T37
Test name
Test status
Simulation time 129800460427 ps
CPU time 379.48 seconds
Started Jul 12 05:08:37 PM PDT 24
Finished Jul 12 05:14:57 PM PDT 24
Peak memory 210424 kb
Host smart-0ae5097b-9745-4cc0-8562-75caa118ca29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457269186 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1457269186
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2860938616
Short name T585
Test name
Test status
Simulation time 524542698 ps
CPU time 1.75 seconds
Started Jul 12 05:08:46 PM PDT 24
Finished Jul 12 05:08:49 PM PDT 24
Peak memory 201640 kb
Host smart-db206577-40e2-4c69-bc67-b1dd724cbcd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860938616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2860938616
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2714063724
Short name T786
Test name
Test status
Simulation time 332838457187 ps
CPU time 760.55 seconds
Started Jul 12 05:08:49 PM PDT 24
Finished Jul 12 05:21:30 PM PDT 24
Peak memory 201872 kb
Host smart-801cb71e-74d7-402f-bd85-3b0d2426565e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714063724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2714063724
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2060062315
Short name T608
Test name
Test status
Simulation time 332365515600 ps
CPU time 336.89 seconds
Started Jul 12 05:08:41 PM PDT 24
Finished Jul 12 05:14:18 PM PDT 24
Peak memory 201896 kb
Host smart-1063061c-1650-4b49-96e4-8eb1be6c9c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060062315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2060062315
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1542246040
Short name T758
Test name
Test status
Simulation time 328641119452 ps
CPU time 187.81 seconds
Started Jul 12 05:08:42 PM PDT 24
Finished Jul 12 05:11:51 PM PDT 24
Peak memory 201864 kb
Host smart-a9ef262c-0f5e-4b1d-ba84-b86e87b1b528
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542246040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1542246040
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.2988307797
Short name T249
Test name
Test status
Simulation time 493376487656 ps
CPU time 1068.6 seconds
Started Jul 12 05:08:39 PM PDT 24
Finished Jul 12 05:26:28 PM PDT 24
Peak memory 201952 kb
Host smart-afd23699-63d4-44b9-ae37-13dc5ff0a7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988307797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2988307797
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1603078884
Short name T339
Test name
Test status
Simulation time 321387847122 ps
CPU time 340.89 seconds
Started Jul 12 05:08:37 PM PDT 24
Finished Jul 12 05:14:18 PM PDT 24
Peak memory 202072 kb
Host smart-a3f9096c-446c-446f-bbfe-baa38d22bf33
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603078884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1603078884
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1619467284
Short name T673
Test name
Test status
Simulation time 200982122084 ps
CPU time 122.95 seconds
Started Jul 12 05:08:40 PM PDT 24
Finished Jul 12 05:10:44 PM PDT 24
Peak memory 201824 kb
Host smart-e3b98ed3-7ad4-4484-9a36-2ff597fcdc34
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619467284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1619467284
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.226127620
Short name T524
Test name
Test status
Simulation time 407396649084 ps
CPU time 231.29 seconds
Started Jul 12 05:08:40 PM PDT 24
Finished Jul 12 05:12:32 PM PDT 24
Peak memory 201844 kb
Host smart-3c0f466d-2e67-450b-aca6-699c68daced0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226127620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
adc_ctrl_filters_wakeup_fixed.226127620
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2903701535
Short name T4
Test name
Test status
Simulation time 141831467414 ps
CPU time 481.53 seconds
Started Jul 12 05:08:48 PM PDT 24
Finished Jul 12 05:16:50 PM PDT 24
Peak memory 202284 kb
Host smart-6d0966c4-ff87-4cf4-b85f-9cd5b90366b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903701535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2903701535
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1813190702
Short name T481
Test name
Test status
Simulation time 39046646220 ps
CPU time 82.67 seconds
Started Jul 12 05:08:48 PM PDT 24
Finished Jul 12 05:10:11 PM PDT 24
Peak memory 201668 kb
Host smart-3e072c76-09cc-42df-9f37-ba4ce99f1234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813190702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1813190702
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2462255551
Short name T623
Test name
Test status
Simulation time 4146132184 ps
CPU time 4.94 seconds
Started Jul 12 05:08:48 PM PDT 24
Finished Jul 12 05:08:54 PM PDT 24
Peak memory 201668 kb
Host smart-013bfb11-bc88-471b-b6f3-020b9acac86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462255551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2462255551
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.830020769
Short name T478
Test name
Test status
Simulation time 5983787396 ps
CPU time 13.36 seconds
Started Jul 12 05:08:34 PM PDT 24
Finished Jul 12 05:08:48 PM PDT 24
Peak memory 201696 kb
Host smart-3f3c5438-e7a8-4f60-929c-17609ab467f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830020769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.830020769
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.4282290984
Short name T138
Test name
Test status
Simulation time 174485812403 ps
CPU time 408.73 seconds
Started Jul 12 05:08:47 PM PDT 24
Finished Jul 12 05:15:36 PM PDT 24
Peak memory 201896 kb
Host smart-d73b3cc6-f696-4813-8603-b2fa3e62fb07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282290984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.4282290984
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3523591885
Short name T23
Test name
Test status
Simulation time 61277456814 ps
CPU time 137.5 seconds
Started Jul 12 05:08:48 PM PDT 24
Finished Jul 12 05:11:06 PM PDT 24
Peak memory 210232 kb
Host smart-4561c780-3c3d-470d-b063-eaae9ace2588
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523591885 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3523591885
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.274450104
Short name T513
Test name
Test status
Simulation time 478494444 ps
CPU time 0.92 seconds
Started Jul 12 05:09:04 PM PDT 24
Finished Jul 12 05:09:06 PM PDT 24
Peak memory 201636 kb
Host smart-2ed60f56-115d-4e5f-8d19-ae5574c6dc09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274450104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.274450104
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1506079871
Short name T94
Test name
Test status
Simulation time 164927150085 ps
CPU time 94.57 seconds
Started Jul 12 05:09:04 PM PDT 24
Finished Jul 12 05:10:40 PM PDT 24
Peak memory 201876 kb
Host smart-1f3d60c5-5452-44d3-aafb-67b9153e4ce4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506079871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1506079871
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2325894118
Short name T181
Test name
Test status
Simulation time 521264576843 ps
CPU time 252.5 seconds
Started Jul 12 05:09:04 PM PDT 24
Finished Jul 12 05:13:18 PM PDT 24
Peak memory 201896 kb
Host smart-0531f55d-6520-45ad-a529-bf31f1b5ef9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325894118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2325894118
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1010491167
Short name T137
Test name
Test status
Simulation time 487408936348 ps
CPU time 1094 seconds
Started Jul 12 05:09:00 PM PDT 24
Finished Jul 12 05:27:14 PM PDT 24
Peak memory 201892 kb
Host smart-68c146fd-0cb9-48f5-beb4-ef9b52ca052b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010491167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1010491167
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1329195247
Short name T449
Test name
Test status
Simulation time 486438144117 ps
CPU time 575.64 seconds
Started Jul 12 05:08:51 PM PDT 24
Finished Jul 12 05:18:27 PM PDT 24
Peak memory 201752 kb
Host smart-f5218465-c34a-4886-b2af-139feefbcd07
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329195247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.1329195247
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2969863309
Short name T657
Test name
Test status
Simulation time 166033730638 ps
CPU time 402.66 seconds
Started Jul 12 05:08:54 PM PDT 24
Finished Jul 12 05:15:37 PM PDT 24
Peak memory 201772 kb
Host smart-3afc9bc9-360d-4c40-8ec2-ea4a86905324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969863309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2969863309
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.639588189
Short name T416
Test name
Test status
Simulation time 166745360613 ps
CPU time 100.24 seconds
Started Jul 12 05:08:53 PM PDT 24
Finished Jul 12 05:10:33 PM PDT 24
Peak memory 201880 kb
Host smart-b4918a80-407b-48ab-9708-d39c85d58571
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=639588189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixe
d.639588189
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.2222609178
Short name T176
Test name
Test status
Simulation time 368890403142 ps
CPU time 909.7 seconds
Started Jul 12 05:09:01 PM PDT 24
Finished Jul 12 05:24:12 PM PDT 24
Peak memory 201904 kb
Host smart-cac666fd-b7ff-469e-a2f3-768b059456e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222609178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.2222609178
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2374291672
Short name T596
Test name
Test status
Simulation time 201429804651 ps
CPU time 225.45 seconds
Started Jul 12 05:08:59 PM PDT 24
Finished Jul 12 05:12:45 PM PDT 24
Peak memory 201872 kb
Host smart-a8070f70-a9cd-4eea-8869-b3bbb13889f1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374291672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2374291672
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3910998635
Short name T652
Test name
Test status
Simulation time 85806893703 ps
CPU time 427.11 seconds
Started Jul 12 05:08:58 PM PDT 24
Finished Jul 12 05:16:06 PM PDT 24
Peak memory 202196 kb
Host smart-5b4c9655-dd19-48d3-bcba-9a0c6891224b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910998635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3910998635
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.1664930673
Short name T379
Test name
Test status
Simulation time 37669593738 ps
CPU time 33.7 seconds
Started Jul 12 05:09:02 PM PDT 24
Finished Jul 12 05:09:36 PM PDT 24
Peak memory 201664 kb
Host smart-f21deba5-563d-4c95-ba85-35f688e27a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664930673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.1664930673
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3459880257
Short name T360
Test name
Test status
Simulation time 3335557199 ps
CPU time 6.99 seconds
Started Jul 12 05:08:59 PM PDT 24
Finished Jul 12 05:09:06 PM PDT 24
Peak memory 201712 kb
Host smart-1b93d791-32c2-4e14-807d-8af94a6fab6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459880257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3459880257
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.69311848
Short name T665
Test name
Test status
Simulation time 5704913479 ps
CPU time 4.2 seconds
Started Jul 12 05:08:53 PM PDT 24
Finished Jul 12 05:08:57 PM PDT 24
Peak memory 201888 kb
Host smart-69730c91-fc37-443a-828a-3fbdf6821757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69311848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.69311848
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.4234879033
Short name T625
Test name
Test status
Simulation time 487654170 ps
CPU time 1.78 seconds
Started Jul 12 05:09:10 PM PDT 24
Finished Jul 12 05:09:13 PM PDT 24
Peak memory 201616 kb
Host smart-ee04967a-fc42-465a-96a1-7a3fc437f73a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234879033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.4234879033
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2868362423
Short name T192
Test name
Test status
Simulation time 338677262373 ps
CPU time 105.81 seconds
Started Jul 12 05:09:06 PM PDT 24
Finished Jul 12 05:10:52 PM PDT 24
Peak memory 201844 kb
Host smart-a164f582-03ed-4549-9769-b3ceedd4b082
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868362423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2868362423
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2700312140
Short name T274
Test name
Test status
Simulation time 362686090060 ps
CPU time 407.73 seconds
Started Jul 12 05:09:04 PM PDT 24
Finished Jul 12 05:15:52 PM PDT 24
Peak memory 201960 kb
Host smart-716fbf37-afe4-4883-ae5f-46c0e72941fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700312140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2700312140
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.528671765
Short name T164
Test name
Test status
Simulation time 493974864024 ps
CPU time 276.79 seconds
Started Jul 12 05:09:04 PM PDT 24
Finished Jul 12 05:13:42 PM PDT 24
Peak memory 201776 kb
Host smart-164a3fa0-0773-4122-8f42-d56f1b508fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528671765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.528671765
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2189257958
Short name T572
Test name
Test status
Simulation time 326158126989 ps
CPU time 164.66 seconds
Started Jul 12 05:09:04 PM PDT 24
Finished Jul 12 05:11:50 PM PDT 24
Peak memory 201728 kb
Host smart-a6f29f10-e15e-4877-ac96-86c13f56cf77
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189257958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2189257958
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1331700104
Short name T289
Test name
Test status
Simulation time 493238405101 ps
CPU time 566.08 seconds
Started Jul 12 05:09:02 PM PDT 24
Finished Jul 12 05:18:28 PM PDT 24
Peak memory 201968 kb
Host smart-b5dfc2e1-635e-421e-92f1-623569ae36f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331700104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1331700104
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1616758722
Short name T695
Test name
Test status
Simulation time 480312402114 ps
CPU time 1023.21 seconds
Started Jul 12 05:09:03 PM PDT 24
Finished Jul 12 05:26:07 PM PDT 24
Peak memory 201748 kb
Host smart-739bcfac-6333-464d-adcb-8d6957257783
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616758722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1616758722
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2448820995
Short name T723
Test name
Test status
Simulation time 356904319990 ps
CPU time 109.84 seconds
Started Jul 12 05:09:06 PM PDT 24
Finished Jul 12 05:10:57 PM PDT 24
Peak memory 201828 kb
Host smart-ba8fe4b7-bd32-406b-b7cf-986ac2263d5a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448820995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2448820995
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1087734291
Short name T497
Test name
Test status
Simulation time 198227478380 ps
CPU time 460.59 seconds
Started Jul 12 05:09:05 PM PDT 24
Finished Jul 12 05:16:46 PM PDT 24
Peak memory 201840 kb
Host smart-4cdd6a14-02fd-4c8a-83af-37ceae05671e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087734291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1087734291
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1483452815
Short name T48
Test name
Test status
Simulation time 114373431468 ps
CPU time 551 seconds
Started Jul 12 05:09:10 PM PDT 24
Finished Jul 12 05:18:22 PM PDT 24
Peak memory 202144 kb
Host smart-cd62fd7d-7a89-436c-bb9b-3aa05814fd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483452815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1483452815
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.1476657722
Short name T550
Test name
Test status
Simulation time 29930634738 ps
CPU time 70.9 seconds
Started Jul 12 05:09:10 PM PDT 24
Finished Jul 12 05:10:21 PM PDT 24
Peak memory 201712 kb
Host smart-8c70a70d-45e5-4480-be2f-293c10642efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476657722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.1476657722
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3694249862
Short name T390
Test name
Test status
Simulation time 5278284830 ps
CPU time 11.9 seconds
Started Jul 12 05:09:15 PM PDT 24
Finished Jul 12 05:09:27 PM PDT 24
Peak memory 201664 kb
Host smart-a138042c-fd2b-4fb6-b8f4-b13a3bab5db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694249862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3694249862
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2586243679
Short name T350
Test name
Test status
Simulation time 6037411803 ps
CPU time 14.15 seconds
Started Jul 12 05:08:58 PM PDT 24
Finished Jul 12 05:09:14 PM PDT 24
Peak memory 201576 kb
Host smart-6b163ed9-1f11-4292-8fc6-1db77ec92ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586243679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2586243679
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.3177121515
Short name T761
Test name
Test status
Simulation time 262265747223 ps
CPU time 615.13 seconds
Started Jul 12 05:09:11 PM PDT 24
Finished Jul 12 05:19:27 PM PDT 24
Peak memory 202288 kb
Host smart-d6e9e9e5-bbb4-4ab4-830a-1913200ad3ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177121515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.3177121515
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.612745942
Short name T20
Test name
Test status
Simulation time 119848299085 ps
CPU time 146.32 seconds
Started Jul 12 05:09:15 PM PDT 24
Finished Jul 12 05:11:42 PM PDT 24
Peak memory 210268 kb
Host smart-73ead740-caaf-4aba-9127-01c2cbe402d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612745942 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.612745942
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.402161930
Short name T31
Test name
Test status
Simulation time 558409621 ps
CPU time 0.91 seconds
Started Jul 12 05:09:23 PM PDT 24
Finished Jul 12 05:09:25 PM PDT 24
Peak memory 201560 kb
Host smart-1cab327f-c7f6-413e-936a-34f1e225b157
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402161930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.402161930
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3192580487
Short name T255
Test name
Test status
Simulation time 558702498894 ps
CPU time 275.42 seconds
Started Jul 12 05:09:19 PM PDT 24
Finished Jul 12 05:13:55 PM PDT 24
Peak memory 201948 kb
Host smart-ff69a625-2d65-474c-8036-3cb524615207
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192580487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3192580487
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1830411223
Short name T664
Test name
Test status
Simulation time 179456767517 ps
CPU time 222.87 seconds
Started Jul 12 05:09:16 PM PDT 24
Finished Jul 12 05:12:59 PM PDT 24
Peak memory 201884 kb
Host smart-a5fde108-4f9f-4a61-8974-b4c7a6d7ae13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830411223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1830411223
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.970562338
Short name T612
Test name
Test status
Simulation time 501444349290 ps
CPU time 136.74 seconds
Started Jul 12 05:09:16 PM PDT 24
Finished Jul 12 05:11:33 PM PDT 24
Peak memory 201868 kb
Host smart-a69ef082-253d-4066-b124-15ede03593af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=970562338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.970562338
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2540620590
Short name T299
Test name
Test status
Simulation time 168172126694 ps
CPU time 196.93 seconds
Started Jul 12 05:09:10 PM PDT 24
Finished Jul 12 05:12:28 PM PDT 24
Peak memory 201928 kb
Host smart-9d5526b4-89c0-49ba-82a9-cf4db945d6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540620590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2540620590
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3366670460
Short name T506
Test name
Test status
Simulation time 328947618561 ps
CPU time 771.74 seconds
Started Jul 12 05:09:17 PM PDT 24
Finished Jul 12 05:22:09 PM PDT 24
Peak memory 202120 kb
Host smart-81ff60d9-9c25-43ae-812e-5d55fad15eed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366670460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3366670460
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.512624480
Short name T239
Test name
Test status
Simulation time 178338829437 ps
CPU time 82.26 seconds
Started Jul 12 05:09:18 PM PDT 24
Finished Jul 12 05:10:40 PM PDT 24
Peak memory 201844 kb
Host smart-e72dd1ef-6ba8-4b29-895e-c7bc8ae238af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512624480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.512624480
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3274375788
Short name T781
Test name
Test status
Simulation time 405038247293 ps
CPU time 418.92 seconds
Started Jul 12 05:09:16 PM PDT 24
Finished Jul 12 05:16:16 PM PDT 24
Peak memory 201780 kb
Host smart-2bfa1bd6-50ac-4369-b6e7-dc86de5bf8ec
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274375788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3274375788
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.742307039
Short name T46
Test name
Test status
Simulation time 133401760847 ps
CPU time 668.77 seconds
Started Jul 12 05:09:16 PM PDT 24
Finished Jul 12 05:20:25 PM PDT 24
Peak memory 202276 kb
Host smart-2b483c49-f220-448c-82c3-81fcdb6d72ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742307039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.742307039
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2216868175
Short name T515
Test name
Test status
Simulation time 34077924385 ps
CPU time 10.6 seconds
Started Jul 12 05:09:16 PM PDT 24
Finished Jul 12 05:09:27 PM PDT 24
Peak memory 201560 kb
Host smart-80a2d265-4c44-4c9e-977f-7aab01fc5008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216868175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2216868175
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3884331337
Short name T702
Test name
Test status
Simulation time 5479664519 ps
CPU time 1.67 seconds
Started Jul 12 05:09:16 PM PDT 24
Finished Jul 12 05:09:19 PM PDT 24
Peak memory 201672 kb
Host smart-9ede346b-cbcb-410a-8f01-e6c2043997d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884331337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3884331337
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.657979987
Short name T514
Test name
Test status
Simulation time 5749069485 ps
CPU time 14.5 seconds
Started Jul 12 05:09:14 PM PDT 24
Finished Jul 12 05:09:29 PM PDT 24
Peak memory 201688 kb
Host smart-f2de316a-3bae-4c45-bcf3-97a6b4b71cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657979987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.657979987
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.948935301
Short name T575
Test name
Test status
Simulation time 69202736970 ps
CPU time 77.33 seconds
Started Jul 12 05:09:19 PM PDT 24
Finished Jul 12 05:10:37 PM PDT 24
Peak memory 210164 kb
Host smart-b657af3a-36fc-436b-9982-b433886b071a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948935301 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.948935301
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1357091236
Short name T27
Test name
Test status
Simulation time 450089376 ps
CPU time 1.11 seconds
Started Jul 12 05:09:36 PM PDT 24
Finished Jul 12 05:09:38 PM PDT 24
Peak memory 201632 kb
Host smart-7da9531d-c271-44b8-8ef0-b94acc0aa7cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357091236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1357091236
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2214463871
Short name T87
Test name
Test status
Simulation time 643219468576 ps
CPU time 277.41 seconds
Started Jul 12 05:09:28 PM PDT 24
Finished Jul 12 05:14:06 PM PDT 24
Peak memory 201860 kb
Host smart-1c93470a-85cb-4876-a9a6-482debe944fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214463871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2214463871
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.850520172
Short name T739
Test name
Test status
Simulation time 369038266589 ps
CPU time 810.73 seconds
Started Jul 12 05:09:30 PM PDT 24
Finished Jul 12 05:23:01 PM PDT 24
Peak memory 201972 kb
Host smart-3bc46dc8-5691-492b-b647-a00b371f108c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850520172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.850520172
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3487930914
Short name T756
Test name
Test status
Simulation time 162991403629 ps
CPU time 97.76 seconds
Started Jul 12 05:09:23 PM PDT 24
Finished Jul 12 05:11:01 PM PDT 24
Peak memory 201772 kb
Host smart-0a9204bc-f709-47b3-be7b-94334938f59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487930914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3487930914
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1848129503
Short name T365
Test name
Test status
Simulation time 330901847329 ps
CPU time 221.1 seconds
Started Jul 12 05:09:30 PM PDT 24
Finished Jul 12 05:13:11 PM PDT 24
Peak memory 201880 kb
Host smart-00d4c296-9086-470b-99c5-60128f00b4ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848129503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1848129503
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.3953621012
Short name T592
Test name
Test status
Simulation time 491323420765 ps
CPU time 834.9 seconds
Started Jul 12 05:09:22 PM PDT 24
Finished Jul 12 05:23:18 PM PDT 24
Peak memory 201864 kb
Host smart-8756f337-5402-4b55-b2a7-fa4588305a4d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953621012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.3953621012
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1518137453
Short name T472
Test name
Test status
Simulation time 196074677303 ps
CPU time 443.48 seconds
Started Jul 12 05:09:27 PM PDT 24
Finished Jul 12 05:16:52 PM PDT 24
Peak memory 201952 kb
Host smart-7527edea-0305-4bc0-958b-16816aa0ca4e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518137453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1518137453
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.4095356430
Short name T766
Test name
Test status
Simulation time 607348491689 ps
CPU time 887.93 seconds
Started Jul 12 05:09:28 PM PDT 24
Finished Jul 12 05:24:17 PM PDT 24
Peak memory 201928 kb
Host smart-1a580422-fbeb-4bb0-b3db-db13639cb26c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095356430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.4095356430
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3823173499
Short name T655
Test name
Test status
Simulation time 74309479782 ps
CPU time 304.61 seconds
Started Jul 12 05:09:39 PM PDT 24
Finished Jul 12 05:14:44 PM PDT 24
Peak memory 202192 kb
Host smart-22a671fe-0253-48e9-b0ba-ef67d4f8d286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823173499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3823173499
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1866475930
Short name T714
Test name
Test status
Simulation time 40413059822 ps
CPU time 25.01 seconds
Started Jul 12 05:09:28 PM PDT 24
Finished Jul 12 05:09:53 PM PDT 24
Peak memory 201688 kb
Host smart-e7b839d8-d920-4613-8226-07e93d4a6ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866475930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1866475930
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2923971417
Short name T670
Test name
Test status
Simulation time 3460513018 ps
CPU time 2.46 seconds
Started Jul 12 05:09:29 PM PDT 24
Finished Jul 12 05:09:32 PM PDT 24
Peak memory 201512 kb
Host smart-f9637fd7-c226-4517-8096-d47a539c9c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923971417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2923971417
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2159998705
Short name T425
Test name
Test status
Simulation time 5756234743 ps
CPU time 3.77 seconds
Started Jul 12 05:09:23 PM PDT 24
Finished Jul 12 05:09:28 PM PDT 24
Peak memory 201616 kb
Host smart-61293f93-5c2b-4a41-9819-580823ff12f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159998705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2159998705
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.978594687
Short name T34
Test name
Test status
Simulation time 350106957471 ps
CPU time 788.19 seconds
Started Jul 12 05:09:35 PM PDT 24
Finished Jul 12 05:22:45 PM PDT 24
Peak memory 201844 kb
Host smart-5963d519-f20a-4248-9875-6cbce0af17ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978594687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
978594687
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1407856678
Short name T539
Test name
Test status
Simulation time 22703788662 ps
CPU time 61.87 seconds
Started Jul 12 05:09:38 PM PDT 24
Finished Jul 12 05:10:41 PM PDT 24
Peak memory 210544 kb
Host smart-afbea037-e9ba-4c6c-837c-4f9a73bf54ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407856678 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1407856678
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3268262924
Short name T440
Test name
Test status
Simulation time 462841818 ps
CPU time 1.64 seconds
Started Jul 12 05:04:18 PM PDT 24
Finished Jul 12 05:04:20 PM PDT 24
Peak memory 201632 kb
Host smart-8cec4662-0ba8-491d-87e8-f14e78cde4b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268262924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3268262924
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2029453825
Short name T634
Test name
Test status
Simulation time 520422990872 ps
CPU time 518.89 seconds
Started Jul 12 05:04:23 PM PDT 24
Finished Jul 12 05:13:03 PM PDT 24
Peak memory 201920 kb
Host smart-6e56a9a1-5c38-48d5-a2c9-3f90175547aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029453825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2029453825
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3736612264
Short name T257
Test name
Test status
Simulation time 175645624635 ps
CPU time 86.88 seconds
Started Jul 12 05:04:21 PM PDT 24
Finished Jul 12 05:05:49 PM PDT 24
Peak memory 201980 kb
Host smart-12a493c8-7a80-4f58-953c-62553ead2c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736612264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3736612264
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.116305477
Short name T89
Test name
Test status
Simulation time 319621680082 ps
CPU time 179.1 seconds
Started Jul 12 05:04:18 PM PDT 24
Finished Jul 12 05:07:18 PM PDT 24
Peak memory 201876 kb
Host smart-05b3053e-1fdb-4261-90f3-011c9f860f1a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=116305477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt
_fixed.116305477
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2746858252
Short name T258
Test name
Test status
Simulation time 486542956144 ps
CPU time 266.75 seconds
Started Jul 12 05:04:16 PM PDT 24
Finished Jul 12 05:08:44 PM PDT 24
Peak memory 201904 kb
Host smart-e84557e8-d643-490f-acbe-623c7c768923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746858252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2746858252
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2792477641
Short name T476
Test name
Test status
Simulation time 325261544666 ps
CPU time 165.38 seconds
Started Jul 12 05:04:15 PM PDT 24
Finished Jul 12 05:07:01 PM PDT 24
Peak memory 201784 kb
Host smart-dc141d6a-3765-47db-91ec-1445e0c14ee4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792477641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2792477641
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1913381283
Short name T144
Test name
Test status
Simulation time 557091789131 ps
CPU time 1218.98 seconds
Started Jul 12 05:04:18 PM PDT 24
Finished Jul 12 05:24:38 PM PDT 24
Peak memory 201892 kb
Host smart-6a8594d0-2a05-4a73-b896-070855e307a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913381283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1913381283
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1587558617
Short name T503
Test name
Test status
Simulation time 200989700207 ps
CPU time 113.41 seconds
Started Jul 12 05:04:20 PM PDT 24
Finished Jul 12 05:06:14 PM PDT 24
Peak memory 201868 kb
Host smart-bfa8cf4e-8976-457a-9e22-c20ac6ddf0f6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587558617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1587558617
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3636677923
Short name T631
Test name
Test status
Simulation time 116032588191 ps
CPU time 495.21 seconds
Started Jul 12 05:04:20 PM PDT 24
Finished Jul 12 05:12:36 PM PDT 24
Peak memory 202236 kb
Host smart-62c5b2fd-b057-4446-94df-284488b223ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636677923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3636677923
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.3696193802
Short name T626
Test name
Test status
Simulation time 28630062672 ps
CPU time 67.78 seconds
Started Jul 12 05:04:17 PM PDT 24
Finished Jul 12 05:05:25 PM PDT 24
Peak memory 201560 kb
Host smart-4dd36f4d-6b04-4ea8-9806-b121c98bbc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696193802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3696193802
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.194797110
Short name T710
Test name
Test status
Simulation time 3019103631 ps
CPU time 1.49 seconds
Started Jul 12 05:04:14 PM PDT 24
Finished Jul 12 05:04:16 PM PDT 24
Peak memory 201676 kb
Host smart-9f26d356-f152-4888-b8f0-e6077ac0e935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194797110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.194797110
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2695123292
Short name T25
Test name
Test status
Simulation time 5583524922 ps
CPU time 7.74 seconds
Started Jul 12 05:04:15 PM PDT 24
Finished Jul 12 05:04:23 PM PDT 24
Peak memory 201660 kb
Host smart-00672a92-c67e-4fb4-a3c3-96941424881b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695123292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2695123292
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2152679147
Short name T159
Test name
Test status
Simulation time 340853838827 ps
CPU time 195.28 seconds
Started Jul 12 05:04:21 PM PDT 24
Finished Jul 12 05:07:37 PM PDT 24
Peak memory 201856 kb
Host smart-fa864efb-a53e-4426-9e1a-9f02dbafb212
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152679147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2152679147
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.4118323745
Short name T795
Test name
Test status
Simulation time 40073941612 ps
CPU time 110.67 seconds
Started Jul 12 05:04:16 PM PDT 24
Finished Jul 12 05:06:07 PM PDT 24
Peak memory 218236 kb
Host smart-bc1da8e1-79e3-4088-a11c-27795952b2b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118323745 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.4118323745
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1581725577
Short name T730
Test name
Test status
Simulation time 552323333 ps
CPU time 0.74 seconds
Started Jul 12 05:04:17 PM PDT 24
Finished Jul 12 05:04:18 PM PDT 24
Peak memory 201496 kb
Host smart-5c9a435d-da62-487b-a1d4-2ac244f171c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581725577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1581725577
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.4090764355
Short name T560
Test name
Test status
Simulation time 172804657078 ps
CPU time 107.83 seconds
Started Jul 12 05:04:22 PM PDT 24
Finished Jul 12 05:06:10 PM PDT 24
Peak memory 201912 kb
Host smart-51cacd47-b2f7-4a62-9c98-411363258a04
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090764355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.4090764355
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.4294286918
Short name T791
Test name
Test status
Simulation time 358517539225 ps
CPU time 425.56 seconds
Started Jul 12 05:04:17 PM PDT 24
Finished Jul 12 05:11:24 PM PDT 24
Peak memory 201928 kb
Host smart-3ad39184-e846-4d61-a74e-975fa7e4c845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294286918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.4294286918
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3492249313
Short name T621
Test name
Test status
Simulation time 486617072066 ps
CPU time 374.59 seconds
Started Jul 12 05:04:17 PM PDT 24
Finished Jul 12 05:10:32 PM PDT 24
Peak memory 201800 kb
Host smart-fda18eea-70c8-486d-89ae-3d6b76afb148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492249313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3492249313
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2970841477
Short name T375
Test name
Test status
Simulation time 493665498965 ps
CPU time 294.61 seconds
Started Jul 12 05:04:16 PM PDT 24
Finished Jul 12 05:09:11 PM PDT 24
Peak memory 201792 kb
Host smart-22ddc88e-d41b-4ed2-8ff3-b185a6644196
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970841477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.2970841477
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.540285615
Short name T656
Test name
Test status
Simulation time 500820931861 ps
CPU time 1102.51 seconds
Started Jul 12 05:04:17 PM PDT 24
Finished Jul 12 05:22:40 PM PDT 24
Peak memory 201952 kb
Host smart-20ccf303-afff-492e-b4c5-f6700d3f1c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540285615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.540285615
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3200904332
Short name T533
Test name
Test status
Simulation time 498878666235 ps
CPU time 996.49 seconds
Started Jul 12 05:04:21 PM PDT 24
Finished Jul 12 05:20:58 PM PDT 24
Peak memory 201884 kb
Host smart-9e4acfd6-86c5-4c2e-81c0-5a89744a140f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200904332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3200904332
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.4107830472
Short name T173
Test name
Test status
Simulation time 549215751541 ps
CPU time 102.2 seconds
Started Jul 12 05:04:16 PM PDT 24
Finished Jul 12 05:05:59 PM PDT 24
Peak memory 201968 kb
Host smart-e2a1e7f9-d859-4259-ac32-9fefac9e3d8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107830472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.4107830472
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3787525128
Short name T353
Test name
Test status
Simulation time 393484978593 ps
CPU time 409.75 seconds
Started Jul 12 05:04:15 PM PDT 24
Finished Jul 12 05:11:05 PM PDT 24
Peak memory 201876 kb
Host smart-672f81cb-6b48-42f8-86e4-bcbfafbeda29
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787525128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3787525128
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.311081994
Short name T327
Test name
Test status
Simulation time 87566354989 ps
CPU time 292.58 seconds
Started Jul 12 05:04:16 PM PDT 24
Finished Jul 12 05:09:10 PM PDT 24
Peak memory 202136 kb
Host smart-346916b8-4018-472b-bd82-2ac9121d4915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311081994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.311081994
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.312268446
Short name T609
Test name
Test status
Simulation time 23482587497 ps
CPU time 4.18 seconds
Started Jul 12 05:04:13 PM PDT 24
Finished Jul 12 05:04:18 PM PDT 24
Peak memory 201712 kb
Host smart-d52714d9-246c-41f8-aa4d-e2afbb77501f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312268446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.312268446
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2455640320
Short name T28
Test name
Test status
Simulation time 3372388993 ps
CPU time 8.26 seconds
Started Jul 12 05:04:15 PM PDT 24
Finished Jul 12 05:04:24 PM PDT 24
Peak memory 201648 kb
Host smart-00f35c81-d2eb-4f1d-9d55-9eb1849bed71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455640320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2455640320
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.646097664
Short name T586
Test name
Test status
Simulation time 5657377291 ps
CPU time 13.05 seconds
Started Jul 12 05:04:14 PM PDT 24
Finished Jul 12 05:04:28 PM PDT 24
Peak memory 201652 kb
Host smart-2516adc9-b211-47f3-8a01-3bfed0fdc89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646097664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.646097664
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1203126930
Short name T218
Test name
Test status
Simulation time 902084495455 ps
CPU time 1712.25 seconds
Started Jul 12 05:04:17 PM PDT 24
Finished Jul 12 05:32:50 PM PDT 24
Peak memory 201884 kb
Host smart-ea3c3fd1-654e-40ab-94a0-ba3763def235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203126930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1203126930
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2330145677
Short name T272
Test name
Test status
Simulation time 54969043682 ps
CPU time 116.32 seconds
Started Jul 12 05:04:22 PM PDT 24
Finished Jul 12 05:06:19 PM PDT 24
Peak memory 210788 kb
Host smart-89ee06e1-831f-443f-9942-04078403b743
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330145677 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2330145677
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.1685140976
Short name T68
Test name
Test status
Simulation time 498665615 ps
CPU time 0.83 seconds
Started Jul 12 05:04:26 PM PDT 24
Finished Jul 12 05:04:28 PM PDT 24
Peak memory 201548 kb
Host smart-4bf37d83-af0d-4b78-978e-943cd013d50a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685140976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1685140976
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2125774364
Short name T266
Test name
Test status
Simulation time 166080552498 ps
CPU time 324.86 seconds
Started Jul 12 05:04:26 PM PDT 24
Finished Jul 12 05:09:53 PM PDT 24
Peak memory 201892 kb
Host smart-2e2ef3e8-beb6-4343-a523-1c00016dff3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125774364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2125774364
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1521112025
Short name T501
Test name
Test status
Simulation time 489487468401 ps
CPU time 308.11 seconds
Started Jul 12 05:04:30 PM PDT 24
Finished Jul 12 05:09:40 PM PDT 24
Peak memory 201864 kb
Host smart-05c081e1-911b-4f41-a5a6-44cf5ef826f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521112025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1521112025
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1758706768
Short name T557
Test name
Test status
Simulation time 163424519886 ps
CPU time 376.27 seconds
Started Jul 12 05:04:18 PM PDT 24
Finished Jul 12 05:10:35 PM PDT 24
Peak memory 201776 kb
Host smart-4a704f53-4ba1-4c0b-93da-c9381775b3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758706768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1758706768
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.224337731
Short name T377
Test name
Test status
Simulation time 486578147154 ps
CPU time 1113.04 seconds
Started Jul 12 05:04:24 PM PDT 24
Finished Jul 12 05:22:58 PM PDT 24
Peak memory 202056 kb
Host smart-7007c4c6-67a3-4e10-a0f5-6a231b0e333a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=224337731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.224337731
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2493242576
Short name T525
Test name
Test status
Simulation time 185550280848 ps
CPU time 426.53 seconds
Started Jul 12 05:04:27 PM PDT 24
Finished Jul 12 05:11:36 PM PDT 24
Peak memory 201928 kb
Host smart-ee726fd1-f370-426c-9950-18b33108b98b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493242576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2493242576
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.4291126045
Short name T396
Test name
Test status
Simulation time 400386552966 ps
CPU time 449.73 seconds
Started Jul 12 05:04:25 PM PDT 24
Finished Jul 12 05:11:57 PM PDT 24
Peak memory 201792 kb
Host smart-f3c03a98-2124-4d0a-a640-1dabc5e9adb4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291126045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.4291126045
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1352067659
Short name T413
Test name
Test status
Simulation time 71222293157 ps
CPU time 255.6 seconds
Started Jul 12 05:04:26 PM PDT 24
Finished Jul 12 05:08:43 PM PDT 24
Peak memory 202200 kb
Host smart-2474d340-a201-41ff-8690-f791f3d132bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352067659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1352067659
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2165991792
Short name T577
Test name
Test status
Simulation time 37630047309 ps
CPU time 82.63 seconds
Started Jul 12 05:04:26 PM PDT 24
Finished Jul 12 05:05:51 PM PDT 24
Peak memory 201660 kb
Host smart-4a134c71-5881-480f-a2a3-d0804695d684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165991792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2165991792
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.4224740905
Short name T708
Test name
Test status
Simulation time 4406014178 ps
CPU time 3.28 seconds
Started Jul 12 05:04:27 PM PDT 24
Finished Jul 12 05:04:33 PM PDT 24
Peak memory 201596 kb
Host smart-a2b05bdd-df00-4794-abcb-4b08e80f4ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224740905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.4224740905
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1831329679
Short name T397
Test name
Test status
Simulation time 5747447868 ps
CPU time 7.37 seconds
Started Jul 12 05:04:20 PM PDT 24
Finished Jul 12 05:04:28 PM PDT 24
Peak memory 201692 kb
Host smart-87a43c97-9aef-4237-b5fb-492b4dfecbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831329679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1831329679
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.2632188329
Short name T314
Test name
Test status
Simulation time 228106945323 ps
CPU time 251.97 seconds
Started Jul 12 05:04:25 PM PDT 24
Finished Jul 12 05:08:37 PM PDT 24
Peak memory 201856 kb
Host smart-a0ff4306-1f42-4ff7-b367-9df867856fdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632188329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
2632188329
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2549732807
Short name T776
Test name
Test status
Simulation time 121935319417 ps
CPU time 446.11 seconds
Started Jul 12 05:04:26 PM PDT 24
Finished Jul 12 05:11:54 PM PDT 24
Peak memory 210580 kb
Host smart-6826cd6b-437e-4c67-946d-1a7e516d7807
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549732807 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2549732807
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.272250761
Short name T96
Test name
Test status
Simulation time 421212307 ps
CPU time 1.13 seconds
Started Jul 12 05:04:24 PM PDT 24
Finished Jul 12 05:04:26 PM PDT 24
Peak memory 201636 kb
Host smart-fa7d9e5f-0240-4cf8-ae41-d9ea2ef06623
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272250761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.272250761
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1193581454
Short name T706
Test name
Test status
Simulation time 491904987202 ps
CPU time 743.29 seconds
Started Jul 12 05:04:27 PM PDT 24
Finished Jul 12 05:16:53 PM PDT 24
Peak memory 201884 kb
Host smart-69a3b6af-3d2e-467a-836f-d63d5481eec5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193581454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1193581454
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.246586209
Short name T311
Test name
Test status
Simulation time 523728034248 ps
CPU time 1096.8 seconds
Started Jul 12 05:04:31 PM PDT 24
Finished Jul 12 05:22:50 PM PDT 24
Peak memory 201980 kb
Host smart-773bcf48-1656-48f2-9c4f-e436cb3a4753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246586209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.246586209
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2647326108
Short name T290
Test name
Test status
Simulation time 330159023067 ps
CPU time 345.05 seconds
Started Jul 12 05:04:27 PM PDT 24
Finished Jul 12 05:10:15 PM PDT 24
Peak memory 201912 kb
Host smart-75c8da7a-5619-48ac-a412-b6680deb1abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647326108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2647326108
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1328784566
Short name T547
Test name
Test status
Simulation time 323217662841 ps
CPU time 737.02 seconds
Started Jul 12 05:04:26 PM PDT 24
Finished Jul 12 05:16:45 PM PDT 24
Peak memory 201756 kb
Host smart-ac7b3c93-e1f5-49f8-b7aa-9c766ce9046e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328784566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.1328784566
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.1216649754
Short name T279
Test name
Test status
Simulation time 321014059773 ps
CPU time 549.61 seconds
Started Jul 12 05:04:26 PM PDT 24
Finished Jul 12 05:13:38 PM PDT 24
Peak memory 201968 kb
Host smart-70b6e5ca-05ed-49f7-b7a8-9e5f17b64140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216649754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1216649754
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.4288692741
Short name T574
Test name
Test status
Simulation time 492565310599 ps
CPU time 240.53 seconds
Started Jul 12 05:04:26 PM PDT 24
Finished Jul 12 05:08:29 PM PDT 24
Peak memory 201892 kb
Host smart-f6520d15-f215-4b09-845e-0e481b6a601e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288692741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.4288692741
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.132413461
Short name T207
Test name
Test status
Simulation time 81612310381 ps
CPU time 309.52 seconds
Started Jul 12 05:04:30 PM PDT 24
Finished Jul 12 05:09:41 PM PDT 24
Peak memory 202216 kb
Host smart-62957694-90a0-45b3-b042-b11a7afc1fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132413461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.132413461
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.916599734
Short name T389
Test name
Test status
Simulation time 46338856063 ps
CPU time 105.86 seconds
Started Jul 12 05:04:25 PM PDT 24
Finished Jul 12 05:06:12 PM PDT 24
Peak memory 201560 kb
Host smart-7e9182a5-42c6-444d-b5ec-d787b5c966cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916599734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.916599734
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2311788202
Short name T484
Test name
Test status
Simulation time 3913814368 ps
CPU time 8.7 seconds
Started Jul 12 05:04:26 PM PDT 24
Finished Jul 12 05:04:37 PM PDT 24
Peak memory 201700 kb
Host smart-d63ca10f-39e9-4911-9b1d-091dc73cbc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311788202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2311788202
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1219164605
Short name T420
Test name
Test status
Simulation time 5717793136 ps
CPU time 13.47 seconds
Started Jul 12 05:04:24 PM PDT 24
Finished Jul 12 05:04:38 PM PDT 24
Peak memory 201676 kb
Host smart-d6c35836-561f-4259-a984-9b5a8e81a079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219164605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1219164605
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.694585074
Short name T598
Test name
Test status
Simulation time 356907546480 ps
CPU time 331.89 seconds
Started Jul 12 05:04:24 PM PDT 24
Finished Jul 12 05:09:57 PM PDT 24
Peak memory 201768 kb
Host smart-33c12e32-e26a-4685-a7fd-63926dbf3bd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694585074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.694585074
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3026462825
Short name T24
Test name
Test status
Simulation time 96119200978 ps
CPU time 137.51 seconds
Started Jul 12 05:04:34 PM PDT 24
Finished Jul 12 05:06:53 PM PDT 24
Peak memory 217720 kb
Host smart-230d6402-737f-4c86-9291-c5126a2f421e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026462825 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3026462825
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3871495626
Short name T703
Test name
Test status
Simulation time 459900796 ps
CPU time 1.62 seconds
Started Jul 12 05:04:29 PM PDT 24
Finished Jul 12 05:04:32 PM PDT 24
Peak memory 201652 kb
Host smart-6a7a0a74-ab9a-49b5-a058-cb399ae08540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871495626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3871495626
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.153885299
Short name T169
Test name
Test status
Simulation time 170122205530 ps
CPU time 38.88 seconds
Started Jul 12 05:04:28 PM PDT 24
Finished Jul 12 05:05:09 PM PDT 24
Peak memory 201916 kb
Host smart-cbe75771-489b-4654-9361-eca436605203
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153885299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.153885299
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.3455203410
Short name T687
Test name
Test status
Simulation time 172538819121 ps
CPU time 414.17 seconds
Started Jul 12 05:04:26 PM PDT 24
Finished Jul 12 05:11:22 PM PDT 24
Peak memory 201880 kb
Host smart-5f3f271e-9e33-4d65-b819-7e0563915f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455203410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3455203410
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.4199825516
Short name T261
Test name
Test status
Simulation time 501924591390 ps
CPU time 343.76 seconds
Started Jul 12 05:04:26 PM PDT 24
Finished Jul 12 05:10:13 PM PDT 24
Peak memory 201896 kb
Host smart-7120e9e3-52d0-4d55-a480-dcd970447c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199825516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.4199825516
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3840429322
Short name T480
Test name
Test status
Simulation time 169775348355 ps
CPU time 353 seconds
Started Jul 12 05:04:29 PM PDT 24
Finished Jul 12 05:10:24 PM PDT 24
Peak memory 201868 kb
Host smart-43a9a8f3-55a5-4883-9017-071ed023a755
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840429322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3840429322
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2733874383
Short name T519
Test name
Test status
Simulation time 328110806278 ps
CPU time 367.85 seconds
Started Jul 12 05:04:31 PM PDT 24
Finished Jul 12 05:10:41 PM PDT 24
Peak memory 201968 kb
Host smart-f2e6155a-07f1-4658-ba09-342371576fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733874383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2733874383
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2543649454
Short name T78
Test name
Test status
Simulation time 326085257660 ps
CPU time 198.8 seconds
Started Jul 12 05:04:26 PM PDT 24
Finished Jul 12 05:07:47 PM PDT 24
Peak memory 201896 kb
Host smart-f706f2ff-049d-464c-ad93-0601497b479c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543649454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2543649454
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.3241800016
Short name T146
Test name
Test status
Simulation time 163681670491 ps
CPU time 393.63 seconds
Started Jul 12 05:04:28 PM PDT 24
Finished Jul 12 05:11:04 PM PDT 24
Peak memory 201796 kb
Host smart-06f2a5f7-fc0b-4115-adfd-9a1a336384eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241800016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.3241800016
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2173918601
Short name T436
Test name
Test status
Simulation time 202270569592 ps
CPU time 425.31 seconds
Started Jul 12 05:04:25 PM PDT 24
Finished Jul 12 05:11:32 PM PDT 24
Peak memory 201888 kb
Host smart-aafd4d4c-72b9-4c28-930d-e8287fea5de4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173918601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2173918601
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3272789900
Short name T441
Test name
Test status
Simulation time 88038419445 ps
CPU time 458.79 seconds
Started Jul 12 05:04:25 PM PDT 24
Finished Jul 12 05:12:06 PM PDT 24
Peak memory 202204 kb
Host smart-da810996-3522-4626-9ff5-8be70195fd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272789900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3272789900
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3029327874
Short name T349
Test name
Test status
Simulation time 23649792310 ps
CPU time 54.89 seconds
Started Jul 12 05:04:31 PM PDT 24
Finished Jul 12 05:05:27 PM PDT 24
Peak memory 201684 kb
Host smart-97e15100-a2d1-4587-b56f-371d781fa620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029327874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3029327874
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1350855685
Short name T354
Test name
Test status
Simulation time 5014812326 ps
CPU time 2.73 seconds
Started Jul 12 05:04:29 PM PDT 24
Finished Jul 12 05:04:33 PM PDT 24
Peak memory 201468 kb
Host smart-6a87b2d3-e8d5-4691-85d6-7f4bc31c6d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350855685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1350855685
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.154178808
Short name T558
Test name
Test status
Simulation time 5882560982 ps
CPU time 2.02 seconds
Started Jul 12 05:04:28 PM PDT 24
Finished Jul 12 05:04:32 PM PDT 24
Peak memory 201712 kb
Host smart-ad88b7b4-f425-411b-bfda-71bf41585461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154178808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.154178808
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2607470408
Short name T405
Test name
Test status
Simulation time 226449098517 ps
CPU time 267.66 seconds
Started Jul 12 05:04:26 PM PDT 24
Finished Jul 12 05:08:56 PM PDT 24
Peak memory 201876 kb
Host smart-807a1243-81b4-491e-b76e-0a197b9bc501
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607470408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2607470408
Directory /workspace/9.adc_ctrl_stress_all/latest
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