Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1235682	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1203550

1

T4

4

T1

6337

T2

463

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2137321	1			T4	1		T1	11980		T3	3595
values[0x0]	150219	1			T4	8		T1	359		T2	568
values[0x1]	151692	1			T4	3		T1	391		T2	585

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	989933	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1449299

1

T4

4

T1

7597

T2

558

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7250	1			T1	25		T3	15		T8	13
valid_sources[0x01]	13062	1			T1	47		T3	20		T10	21
valid_sources[0x02]	7456	1			T1	49		T3	15		T8	12
valid_sources[0x03]	12011	1			T1	49		T3	19		T8	3
valid_sources[0x04]	12836	1			T1	59		T3	22		T8	3
valid_sources[0x05]	7494	1			T1	34		T3	17		T8	5
valid_sources[0x06]	11319	1			T1	49		T3	16		T10	59
valid_sources[0x07]	7294	1			T1	51		T3	18		T8	13
valid_sources[0x08]	7966	1			T1	39		T3	24		T8	18
valid_sources[0x09]	7146	1			T1	40		T3	27		T8	14
valid_sources[0x0a]	7579	1			T1	48		T3	21		T8	18
valid_sources[0x0b]	7410	1			T1	26		T3	27		T8	1
valid_sources[0x0c]	7648	1			T1	55		T3	19		T10	36
valid_sources[0x0d]	7870	1			T1	61		T3	16		T10	34
valid_sources[0x0e]	16300	1			T1	78		T3	11		T8	6
valid_sources[0x0f]	8492	1			T1	63		T3	23		T10	30
valid_sources[0x10]	10539	1			T1	91		T3	26		T10	36
valid_sources[0x11]	8659	1			T1	43		T3	19		T8	6
valid_sources[0x12]	7174	1			T1	38		T3	20		T5	1
valid_sources[0x13]	7334	1			T1	53		T3	20		T7	2
valid_sources[0x14]	11783	1			T1	72		T3	19		T10	28
valid_sources[0x15]	7383	1			T1	51		T3	19		T8	11
valid_sources[0x16]	9153	1			T1	36		T3	19		T10	44
valid_sources[0x17]	10892	1			T1	58		T3	12		T10	50
valid_sources[0x18]	7302	1			T1	49		T3	15		T8	6
valid_sources[0x19]	7343	1			T1	35		T3	12		T10	35
valid_sources[0x1a]	12778	1			T1	54		T3	17		T8	3
valid_sources[0x1b]	14473	1			T1	48		T3	29		T8	1
valid_sources[0x1c]	11513	1			T1	56		T3	17		T10	30
valid_sources[0x1d]	7717	1			T1	34		T3	24		T10	53
valid_sources[0x1e]	8587	1			T1	53		T3	15		T10	31
valid_sources[0x1f]	14361	1			T1	53		T3	17		T10	47
valid_sources[0x20]	7922	1			T4	3		T1	46		T3	20
valid_sources[0x21]	7858	1			T1	44		T3	22		T8	12
valid_sources[0x22]	12821	1			T1	64		T3	19		T8	1
valid_sources[0x23]	14143	1			T1	58		T3	14		T10	36
valid_sources[0x24]	8536	1			T1	31		T2	1153		T3	17
valid_sources[0x25]	7194	1			T1	82		T3	18		T8	2
valid_sources[0x26]	7731	1			T1	65		T3	22		T8	3
valid_sources[0x27]	7521	1			T1	33		T3	24		T10	34
valid_sources[0x28]	8263	1			T1	49		T3	20		T8	4
valid_sources[0x29]	8117	1			T1	27		T3	16		T8	10
valid_sources[0x2a]	15410	1			T1	47		T3	20		T8	5
valid_sources[0x2b]	12309	1			T1	62		T3	17		T8	7
valid_sources[0x2c]	12436	1			T1	50		T3	16		T10	32
valid_sources[0x2d]	8442	1			T1	52		T3	21		T10	33
valid_sources[0x2e]	10034	1			T1	53		T3	17		T10	38
valid_sources[0x2f]	7412	1			T1	56		T3	25		T10	35
valid_sources[0x30]	12380	1			T1	73		T3	23		T10	13
valid_sources[0x31]	7268	1			T1	42		T3	10		T10	38
valid_sources[0x32]	8028	1			T1	81		T3	21		T8	7
valid_sources[0x33]	9701	1			T1	47		T3	10		T8	30
valid_sources[0x34]	10174	1			T1	38		T3	16		T10	38
valid_sources[0x35]	7730	1			T1	25		T3	22		T8	5
valid_sources[0x36]	12907	1			T1	65		T3	12		T8	3
valid_sources[0x37]	7572	1			T1	68		T3	16		T10	48
valid_sources[0x38]	8466	1			T1	43		T3	16		T10	32
valid_sources[0x39]	8398	1			T1	46		T3	14		T8	6
valid_sources[0x3a]	7533	1			T1	28		T3	21		T10	25
valid_sources[0x3b]	12976	1			T1	24		T3	20		T10	32
valid_sources[0x3c]	8814	1			T1	45		T3	22		T8	8
valid_sources[0x3d]	8555	1			T1	33		T3	18		T10	27
valid_sources[0x3e]	7802	1			T1	78		T3	19		T10	61
valid_sources[0x3f]	7544	1			T1	32		T3	10		T10	39
valid_sources[0x40]	7580	1			T1	49		T3	18		T8	10
valid_sources[0x41]	7565	1			T1	45		T3	19		T8	1
valid_sources[0x42]	7762	1			T1	44		T3	16		T7	1
valid_sources[0x43]	24395	1			T1	40		T3	25		T8	4
valid_sources[0x44]	7184	1			T1	33		T3	17		T7	1
valid_sources[0x45]	7082	1			T1	58		T3	16		T10	39
valid_sources[0x46]	7888	1			T1	100		T3	26		T10	36
valid_sources[0x47]	9616	1			T1	63		T3	20		T10	33
valid_sources[0x48]	7328	1			T1	49		T3	15		T10	28
valid_sources[0x49]	15198	1			T1	57		T3	17		T8	7
valid_sources[0x4a]	7564	1			T1	56		T3	20		T10	49
valid_sources[0x4b]	11423	1			T1	35		T3	20		T10	23
valid_sources[0x4c]	7525	1			T1	38		T3	21		T8	15
valid_sources[0x4d]	7634	1			T1	70		T3	16		T8	7
valid_sources[0x4e]	11350	1			T1	42		T3	24		T7	1
valid_sources[0x4f]	7822	1			T1	58		T3	23		T8	4
valid_sources[0x50]	7491	1			T1	15		T3	27		T8	4
valid_sources[0x51]	7773	1			T1	62		T3	23		T10	27
valid_sources[0x52]	12180	1			T1	55		T3	11		T8	10
valid_sources[0x53]	7385	1			T1	51		T3	12		T8	4
valid_sources[0x54]	7537	1			T1	87		T3	14		T10	34
valid_sources[0x55]	8544	1			T1	44		T3	13		T10	49
valid_sources[0x56]	9445	1			T1	50		T3	20		T10	54
valid_sources[0x57]	7802	1			T1	59		T3	10		T10	25
valid_sources[0x58]	7209	1			T1	32		T3	23		T8	3
valid_sources[0x59]	8267	1			T1	68		T3	9		T8	16
valid_sources[0x5a]	8215	1			T1	51		T3	16		T8	21
valid_sources[0x5b]	16027	1			T1	44		T3	25		T9	8576
valid_sources[0x5c]	10559	1			T1	36		T3	14		T8	15
valid_sources[0x5d]	7754	1			T1	35		T3	19		T8	5
valid_sources[0x5e]	7615	1			T1	53		T3	14		T7	1
valid_sources[0x5f]	16069	1			T1	56		T3	19		T10	61
valid_sources[0x60]	7379	1			T1	31		T3	21		T10	20
valid_sources[0x61]	13442	1			T1	46		T3	21		T10	4158
valid_sources[0x62]	8455	1			T1	48		T3	29		T10	35
valid_sources[0x63]	7237	1			T1	53		T3	19		T10	32
valid_sources[0x64]	8518	1			T1	83		T3	25		T10	63
valid_sources[0x65]	11978	1			T1	89		T3	16		T10	17
valid_sources[0x66]	11689	1			T1	36		T3	25		T8	7
valid_sources[0x67]	8929	1			T1	53		T3	14		T10	37
valid_sources[0x68]	8609	1			T1	34		T3	19		T10	25
valid_sources[0x69]	10891	1			T1	32		T3	15		T8	1
valid_sources[0x6a]	10462	1			T1	75		T3	19		T8	16
valid_sources[0x6b]	7595	1			T1	49		T3	17		T10	32
valid_sources[0x6c]	7526	1			T1	33		T3	25		T10	27
valid_sources[0x6d]	7522	1			T1	46		T3	16		T10	30
valid_sources[0x6e]	7434	1			T1	29		T3	18		T8	14
valid_sources[0x6f]	7205	1			T1	66		T3	19		T8	8
valid_sources[0x70]	11203	1			T1	51		T3	15		T8	3
valid_sources[0x71]	7295	1			T4	2		T1	27		T3	17
valid_sources[0x72]	8322	1			T1	50		T3	26		T8	1
valid_sources[0x73]	14681	1			T1	38		T3	16		T8	12
valid_sources[0x74]	10129	1			T1	54		T3	17		T8	13
valid_sources[0x75]	7253	1			T1	39		T3	22		T8	13
valid_sources[0x76]	7890	1			T1	70		T3	16		T8	6
valid_sources[0x77]	12394	1			T1	44		T3	18		T10	51
valid_sources[0x78]	7191	1			T1	73		T3	13		T10	21
valid_sources[0x79]	11522	1			T1	50		T3	16		T10	35
valid_sources[0x7a]	11708	1			T4	1		T1	40		T3	30
valid_sources[0x7b]	7444	1			T1	39		T3	18		T10	34
valid_sources[0x7c]	16004	1			T1	55		T3	13		T10	51
valid_sources[0x7d]	8826	1			T1	65		T3	22		T8	4
valid_sources[0x7e]	8367	1			T1	51		T3	23		T7	3
valid_sources[0x7f]	10252	1			T1	54		T3	25		T8	2
valid_sources[0x80]	12607	1			T1	31		T3	15		T10	33

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1063119

1

T4

1

T1

6051

T3

1790

values[0x0]

all_enables

biggest_size

81493

1

T4

3

T1

164

T2

277

values[0x1]

all_enables

biggest_size

58938

1

T1

122

T2

186

T3

205