Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30916	1			T1	23		T2	333		T3	257
auto[PWRUP]	125	1			T2	1		T6	2		T38	3
auto[ONEST_0]	76	1			T3	1		T38	1		T14	5
auto[ONEST_021]	18	1			T44	1		T27	2		T51	2
auto[ONEST_1]	89	1			T2	1		T6	1		T14	1
auto[ONEST_DONE]	7	1			T2	1		T38	1		T20	1
auto[LP_0]	116	1			T2	1		T3	3		T6	3
auto[LP_021]	31	1			T2	2		T196	1		T193	1
auto[LP_1]	148	1			T2	2		T3	3		T6	2
auto[LP_EVAL]	89	1			T2	3		T3	1		T6	3
auto[LP_SLP]	557	1			T2	8		T3	3		T6	7
auto[LP_PWRUP]	25	1			T6	2		T14	1		T44	2
auto[NP_0]	154	1			T2	1		T3	4		T6	4
auto[NP_021]	31	1			T6	1		T14	1		T15	1
auto[NP_1]	187	1			T2	1		T3	4		T6	4
auto[NP_EVAL]	34	1			T38	1		T14	1		T44	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

4

1

T3

1

T200

1

T201

1

min

30375

1

T1

23

T2

316

T3

245

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30377	1			T1	23		T2	316		T3	245
pow[0x1]	10	1			T51	1		T45	1		T202	1
pow[0x2]	25	1			T15	1		T27	1		T196	1
pow[0x3]	37	1			T2	1		T38	1		T14	1
pow[0x4]	65	1			T2	1		T3	3		T6	1
pow[0x5]	135	1			T6	2		T38	1		T14	1
pow[0x6]	279	1			T2	6		T3	5		T6	2
pow[0x7]	583	1			T2	7		T3	12		T6	15

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

200

1

T2

2

T3

1

T6

2

min

29847

1

T1

23

T2

307

T3

245

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x5]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29847	1			T1	23		T2	307		T3	245
pow[0x4]	1	1			T45	1		-	-		-	-
pow[0x6]	1	1			T203	1		-	-		-	-
pow[0x8]	4	1			T199	1		T204	1		T205	1
pow[0x9]	12	1			T2	1		T38	1		T206	1
pow[0xa]	21	1			T2	1		T3	1		T38	1
pow[0xb]	34	1			T2	1		T6	1		T27	1
pow[0xc]	63	1			T2	1		T6	3		T38	1
pow[0xd]	155	1			T2	1		T6	4		T38	1
pow[0xe]	301	1			T2	4		T3	3		T6	6
pow[0xf]	665	1			T2	12		T3	6		T6	10