Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2488	1			T2	8		T3	22		T6	14
auto[PWRUP]	133	1			T2	2		T3	2		T6	2
auto[ONEST_0]	74	1			T2	1		T3	1		T38	2
auto[ONEST_021]	15	1			T332	1		T41	1		T333	1
auto[ONEST_1]	97	1			T2	3		T3	1		T6	1
auto[ONEST_DONE]	3	1			T200	1		T206	1		T334	1
auto[LP_0]	127	1			T2	2		T6	3		T38	1
auto[LP_021]	30	1			T2	2		T38	1		T14	1
auto[LP_1]	162	1			T2	1		T3	1		T6	3
auto[LP_EVAL]	73	1			T3	2		T6	1		T38	1
auto[LP_SLP]	547	1			T2	2		T3	4		T6	8
auto[LP_PWRUP]	23	1			T15	1		T332	1		T196	2
auto[NP_0]	224	1			T2	1		T3	2		T6	3
auto[NP_021]	50	1			T38	1		T14	2		T27	1
auto[NP_1]	256	1			T2	1		T3	2		T6	3
auto[NP_EVAL]	28	1			T6	1		T15	1		T193	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T178

1

T335

1

T206

1

min

2059

1

T2

4

T3

17

T6

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2074	1			T2	4		T3	17		T6	10
pow[0x1]	7	1			T14	1		T184	1		T336	1
pow[0x2]	13	1			T14	1		T333	3		T296	1
pow[0x3]	38	1			T38	1		T15	1		T27	2
pow[0x4]	78	1			T3	1		T14	2		T44	1
pow[0x5]	144	1			T2	3		T3	2		T6	2
pow[0x6]	305	1			T2	4		T3	3		T6	6
pow[0x7]	541	1			T2	3		T3	6		T6	10

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

227

1

T2

1

T3

3

T6

4

min

1453

1

T2

1

T3

10

T6

4

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1459	1			T2	1		T3	10		T6	4
pow[0x1]	13	1			T37	1		T265	1		T110	6
pow[0x2]	19	1			T37	1		T42	2		T18	3
pow[0x3]	47	1			T3	2		T37	3		T41	1
pow[0x4]	71	1			T15	3		T37	1		T41	2
pow[0x6]	2	1			T327	1		T337	1		-	-
pow[0x7]	3	1			T338	1		T339	1		T340	1
pow[0x8]	3	1			T3	1		T202	1		T341	1
pow[0x9]	14	1			T14	1		T44	1		T193	1
pow[0xa]	23	1			T15	1		T27	1		T51	1
pow[0xb]	34	1			T14	1		T51	1		T332	2
pow[0xc]	71	1			T3	2		T38	1		T14	1
pow[0xd]	154	1			T6	2		T14	1		T15	1
pow[0xe]	313	1			T2	3		T3	4		T6	5
pow[0xf]	645	1			T2	5		T3	5		T6	8