Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1917	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1885	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1940	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1779	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1862	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1918	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1650	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1938	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1839	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1905	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2096	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1866	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1872	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1976	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1995	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1888	0	0
adc_en_ctl_rd_A	2147483647	1525	0	0
adc_fsm_rst_rd_A	2147483647	1313	0	0
adc_intr_ctl_rd_A	2147483647	1669	0	0
adc_lp_sample_ctl_rd_A	2147483647	1357	0	0
adc_pd_ctl_rd_A	2147483647	1785	0	0
adc_sample_ctl_rd_A	2147483647	1224	0	0
adc_wakeup_ctl_rd_A	2147483647	1564	0	0
intr_enable_rd_A	2147483647	2022	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1917	0	0
T15	454253	22	0	0
T16	0	16	0	0
T17	0	12	0	0
T18	0	44	0	0
T19	0	12	0	0
T20	0	23	0	0
T21	0	15	0	0
T22	0	7	0	0
T23	0	42	0	0
T24	0	26	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1885	0	0
T15	454253	15	0	0
T16	0	22	0	0
T17	0	13	0	0
T18	0	40	0	0
T19	0	8	0	0
T20	0	7	0	0
T21	0	9	0	0
T22	0	25	0	0
T23	0	32	0	0
T24	0	49	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1940	0	0
T15	454253	12	0	0
T16	0	17	0	0
T17	0	14	0	0
T18	0	34	0	0
T19	0	7	0	0
T20	0	17	0	0
T21	0	12	0	0
T22	0	33	0	0
T23	0	29	0	0
T24	0	36	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1779	0	0
T15	454253	15	0	0
T16	0	14	0	0
T17	0	4	0	0
T18	0	23	0	0
T19	0	7	0	0
T20	0	28	0	0
T21	0	18	0	0
T22	0	15	0	0
T23	0	43	0	0
T24	0	45	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1862	0	0
T15	454253	21	0	0
T16	0	21	0	0
T17	0	6	0	0
T18	0	32	0	0
T19	0	9	0	0
T20	0	30	0	0
T21	0	21	0	0
T22	0	28	0	0
T23	0	49	0	0
T24	0	36	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1918	0	0
T15	454253	23	0	0
T16	0	18	0	0
T17	0	22	0	0
T18	0	27	0	0
T19	0	15	0	0
T20	0	10	0	0
T21	0	25	0	0
T22	0	29	0	0
T23	0	22	0	0
T24	0	30	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1650	0	0
T15	454253	19	0	0
T16	0	27	0	0
T17	0	17	0	0
T18	0	26	0	0
T19	0	14	0	0
T20	0	27	0	0
T21	0	7	0	0
T22	0	19	0	0
T23	0	43	0	0
T24	0	52	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1938	0	0
T15	454253	15	0	0
T16	0	25	0	0
T17	0	7	0	0
T18	0	17	0	0
T19	0	4	0	0
T20	0	21	0	0
T21	0	12	0	0
T22	0	34	0	0
T23	0	44	0	0
T24	0	31	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1839	0	0
T15	454253	15	0	0
T16	0	33	0	0
T17	0	12	0	0
T18	0	34	0	0
T19	0	14	0	0
T20	0	17	0	0
T21	0	22	0	0
T22	0	18	0	0
T23	0	36	0	0
T24	0	41	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1905	0	0
T15	454253	13	0	0
T16	0	17	0	0
T17	0	4	0	0
T18	0	29	0	0
T19	0	14	0	0
T20	0	29	0	0
T21	0	11	0	0
T22	0	25	0	0
T23	0	44	0	0
T24	0	38	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2096	0	0
T15	454253	20	0	0
T16	0	7	0	0
T17	0	4	0	0
T18	0	29	0	0
T19	0	1	0	0
T20	0	20	0	0
T21	0	27	0	0
T22	0	29	0	0
T23	0	38	0	0
T24	0	32	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1866	0	0
T15	454253	12	0	0
T16	0	5	0	0
T17	0	7	0	0
T18	0	28	0	0
T19	0	7	0	0
T20	0	20	0	0
T21	0	10	0	0
T22	0	35	0	0
T23	0	26	0	0
T24	0	41	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1872	0	0
T15	454253	23	0	0
T16	0	20	0	0
T18	0	36	0	0
T19	0	8	0	0
T20	0	19	0	0
T21	0	30	0	0
T22	0	20	0	0
T23	0	38	0	0
T24	0	45	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0
T34	0	11	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1976	0	0
T15	454253	15	0	0
T16	0	16	0	0
T18	0	32	0	0
T19	0	14	0	0
T20	0	21	0	0
T21	0	18	0	0
T22	0	25	0	0
T23	0	32	0	0
T24	0	40	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0
T34	0	23	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1995	0	0
T15	454253	24	0	0
T16	0	17	0	0
T18	0	28	0	0
T19	0	15	0	0
T20	0	25	0	0
T21	0	22	0	0
T22	0	49	0	0
T23	0	37	0	0
T24	0	30	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0
T34	0	30	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1888	0	0
T15	454253	13	0	0
T16	0	22	0	0
T17	0	22	0	0
T18	0	33	0	0
T19	0	1	0	0
T20	0	17	0	0
T21	0	16	0	0
T22	0	20	0	0
T23	0	43	0	0
T24	0	31	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1525	0	0
T15	454253	9	0	0
T16	0	21	0	0
T17	0	7	0	0
T18	0	34	0	0
T19	0	5	0	0
T20	0	31	0	0
T21	0	20	0	0
T22	0	35	0	0
T23	0	28	0	0
T24	0	39	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1313	0	0
T15	454253	16	0	0
T16	0	24	0	0
T17	0	7	0	0
T18	0	33	0	0
T19	0	9	0	0
T20	0	29	0	0
T21	0	21	0	0
T22	0	18	0	0
T23	0	33	0	0
T24	0	34	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1669	0	0
T15	454253	7	0	0
T16	0	8	0	0
T17	0	9	0	0
T18	0	17	0	0
T19	0	7	0	0
T20	0	14	0	0
T21	0	20	0	0
T22	0	26	0	0
T23	0	39	0	0
T24	0	43	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1357	0	0
T15	454253	14	0	0
T16	0	23	0	0
T17	0	8	0	0
T18	0	38	0	0
T19	0	2	0	0
T20	0	14	0	0
T21	0	21	0	0
T22	0	25	0	0
T23	0	26	0	0
T24	0	54	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1785	0	0
T15	454253	12	0	0
T16	0	11	0	0
T17	0	4	0	0
T18	0	23	0	0
T19	0	12	0	0
T20	0	32	0	0
T21	0	16	0	0
T22	0	29	0	0
T23	0	40	0	0
T24	0	25	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1224	0	0
T15	454253	20	0	0
T16	0	30	0	0
T17	0	14	0	0
T18	0	30	0	0
T19	0	8	0	0
T20	0	17	0	0
T21	0	18	0	0
T22	0	23	0	0
T23	0	37	0	0
T24	0	34	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1564	0	0
T15	454253	11	0	0
T16	0	21	0	0
T17	0	4	0	0
T18	0	44	0	0
T19	0	12	0	0
T20	0	16	0	0
T21	0	30	0	0
T22	0	32	0	0
T23	0	34	0	0
T24	0	44	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2022	0	0
T15	454253	23	0	0
T16	0	31	0	0
T17	0	8	0	0
T18	0	60	0	0
T19	0	22	0	0
T20	0	25	0	0
T21	0	53	0	0
T22	0	61	0	0
T25	289526	0	0	0
T26	485948	0	0	0
T27	124362	0	0	0
T28	955935	0	0	0
T29	10690	0	0	0
T30	317469	0	0	0
T31	341731	0	0	0
T32	173152	0	0	0
T33	170435	0	0	0
T35	0	38	0	0
T36	0	5	0	0