Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1220706	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1189053

1

T1

2091

T4

6

T2

348

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2107506	1			T1	3975		T4	1		T3	81
values[0x0]	150765	1			T1	134		T4	12		T2	433
values[0x1]	151488	1			T1	122		T4	7		T2	454

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	978117	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1431642

1

T1

2498

T4

6

T2

417

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7696	1			T1	11		T3	4		T5	17
valid_sources[0x01]	7267	1			T1	16		T2	2		T5	7
valid_sources[0x02]	7481	1			T1	7		T2	5		T5	10
valid_sources[0x03]	7139	1			T1	12		T2	7		T5	10
valid_sources[0x04]	7623	1			T1	4		T5	10		T6	13
valid_sources[0x05]	7433	1			T1	20		T2	7		T5	10
valid_sources[0x06]	7242	1			T1	19		T5	6		T6	5
valid_sources[0x07]	8356	1			T1	10		T4	1		T2	2
valid_sources[0x08]	6898	1			T1	17		T2	1		T5	11
valid_sources[0x09]	10204	1			T1	10		T2	6		T5	4
valid_sources[0x0a]	11599	1			T1	2		T5	11		T6	5
valid_sources[0x0b]	7375	1			T1	27		T2	5		T5	11
valid_sources[0x0c]	7883	1			T1	9		T2	9		T5	12
valid_sources[0x0d]	7374	1			T1	6		T2	2		T5	7
valid_sources[0x0e]	7331	1			T1	17		T2	15		T5	5
valid_sources[0x0f]	8271	1			T1	13		T2	2		T3	4
valid_sources[0x10]	8423	1			T1	18		T4	1		T2	3
valid_sources[0x11]	7233	1			T1	16		T5	18		T6	7
valid_sources[0x12]	7549	1			T1	12		T2	6		T5	11
valid_sources[0x13]	7473	1			T1	3		T2	2		T5	9
valid_sources[0x14]	7081	1			T1	39		T2	8		T3	3
valid_sources[0x15]	7210	1			T1	8		T2	1		T5	11
valid_sources[0x16]	10243	1			T1	24		T5	9		T6	17
valid_sources[0x17]	7310	1			T1	23		T2	7		T3	4
valid_sources[0x18]	7777	1			T1	19		T5	10		T6	16
valid_sources[0x19]	10894	1			T1	9		T2	2		T5	14
valid_sources[0x1a]	8003	1			T1	21		T2	1		T5	7
valid_sources[0x1b]	7325	1			T1	20		T2	12		T5	14
valid_sources[0x1c]	8039	1			T1	7		T3	11		T5	12
valid_sources[0x1d]	11682	1			T1	5		T5	15		T6	11
valid_sources[0x1e]	7256	1			T1	28		T5	12		T6	10
valid_sources[0x1f]	13213	1			T1	16		T2	3		T5	10
valid_sources[0x20]	7386	1			T1	10		T5	14		T6	8
valid_sources[0x21]	9168	1			T1	4		T2	8		T5	4
valid_sources[0x22]	11388	1			T1	10		T4	1		T2	6
valid_sources[0x23]	12661	1			T1	16		T2	5		T5	20
valid_sources[0x24]	11689	1			T1	39		T2	12		T5	8
valid_sources[0x25]	12426	1			T1	51		T5	9		T6	15
valid_sources[0x26]	8039	1			T1	21		T2	2		T5	16
valid_sources[0x27]	8382	1			T1	15		T2	6		T5	8
valid_sources[0x28]	12249	1			T1	18		T2	1		T5	12
valid_sources[0x29]	7095	1			T1	7		T2	2		T5	11
valid_sources[0x2a]	16958	1			T1	19		T2	7		T5	12
valid_sources[0x2b]	11864	1			T5	12		T6	10		T10	9
valid_sources[0x2c]	11476	1			T1	10		T5	16		T6	16
valid_sources[0x2d]	12016	1			T1	13		T3	6		T5	13
valid_sources[0x2e]	13624	1			T1	7		T2	5		T3	12
valid_sources[0x2f]	7294	1			T1	5		T2	9		T5	9
valid_sources[0x30]	16800	1			T1	2		T2	6		T5	10
valid_sources[0x31]	11487	1			T1	9		T2	1		T3	3
valid_sources[0x32]	9234	1			T1	11		T5	17		T6	10
valid_sources[0x33]	8934	1			T1	12		T2	1		T5	16
valid_sources[0x34]	8572	1			T1	21		T2	3		T5	11
valid_sources[0x35]	7112	1			T1	18		T2	1		T5	6
valid_sources[0x36]	7594	1			T1	11		T2	2		T5	10
valid_sources[0x37]	11277	1			T1	22		T2	11		T5	14
valid_sources[0x38]	7335	1			T1	22		T5	8		T6	8
valid_sources[0x39]	15970	1			T1	13		T2	5		T5	8
valid_sources[0x3a]	11592	1			T1	23		T5	15		T6	9
valid_sources[0x3b]	11313	1			T1	11		T2	3		T5	8
valid_sources[0x3c]	12366	1			T1	4		T2	4		T5	10
valid_sources[0x3d]	8400	1			T1	8		T5	11		T6	21
valid_sources[0x3e]	7063	1			T1	8		T5	9		T6	5
valid_sources[0x3f]	8785	1			T1	23		T4	9		T2	1
valid_sources[0x40]	8619	1			T1	24		T2	13		T5	14
valid_sources[0x41]	13594	1			T1	14		T2	11		T5	9
valid_sources[0x42]	7235	1			T1	41		T5	14		T6	4
valid_sources[0x43]	8414	1			T1	19		T5	10		T6	14
valid_sources[0x44]	8371	1			T1	6		T2	2		T5	9
valid_sources[0x45]	9934	1			T1	11		T5	13		T6	16
valid_sources[0x46]	10826	1			T1	21		T2	3		T5	10
valid_sources[0x47]	11386	1			T1	17		T2	17		T5	9
valid_sources[0x48]	11673	1			T1	18		T2	6		T5	8
valid_sources[0x49]	7395	1			T1	19		T2	1		T5	17
valid_sources[0x4a]	7399	1			T1	40		T3	3		T5	9
valid_sources[0x4b]	14192	1			T1	19		T2	3		T5	11
valid_sources[0x4c]	7215	1			T1	27		T2	4		T5	10
valid_sources[0x4d]	11367	1			T1	21		T2	8		T5	9
valid_sources[0x4e]	8504	1			T1	12		T2	1		T5	15
valid_sources[0x4f]	7016	1			T1	39		T2	2		T3	1
valid_sources[0x50]	7304	1			T1	5		T2	2		T5	14
valid_sources[0x51]	12263	1			T1	10		T5	4		T6	12
valid_sources[0x52]	10085	1			T1	15		T2	8		T5	6
valid_sources[0x53]	13951	1			T1	13		T2	12		T5	8
valid_sources[0x54]	14044	1			T1	12		T4	1		T2	5
valid_sources[0x55]	11456	1			T1	10		T2	10		T5	10
valid_sources[0x56]	9557	1			T1	38		T3	2		T5	7
valid_sources[0x57]	8424	1			T1	18		T5	10		T6	12
valid_sources[0x58]	7463	1			T1	23		T2	10		T5	19
valid_sources[0x59]	7522	1			T1	5		T2	1		T5	14
valid_sources[0x5a]	7626	1			T1	13		T2	2		T3	4
valid_sources[0x5b]	7513	1			T1	8		T2	6		T5	10
valid_sources[0x5c]	8246	1			T1	17		T2	1		T5	15
valid_sources[0x5d]	13273	1			T1	10		T2	3		T5	8
valid_sources[0x5e]	12526	1			T1	17		T2	2		T5	12
valid_sources[0x5f]	7973	1			T1	27		T5	9		T6	2
valid_sources[0x60]	7572	1			T1	18		T2	1		T5	14
valid_sources[0x61]	11336	1			T1	16		T2	3		T5	8
valid_sources[0x62]	7627	1			T1	7		T2	7		T5	10
valid_sources[0x63]	8618	1			T1	3		T5	12		T6	5
valid_sources[0x64]	9376	1			T1	8		T2	4		T5	19
valid_sources[0x65]	7737	1			T1	30		T2	1		T5	17
valid_sources[0x66]	16120	1			T1	32		T2	7		T5	11
valid_sources[0x67]	7199	1			T1	28		T5	14		T6	18
valid_sources[0x68]	8472	1			T1	3		T2	2		T5	10
valid_sources[0x69]	8074	1			T1	20		T3	1		T5	14
valid_sources[0x6a]	7700	1			T1	11		T2	10		T5	17
valid_sources[0x6b]	7318	1			T1	10		T5	6		T6	5
valid_sources[0x6c]	7137	1			T1	8		T2	1		T5	10
valid_sources[0x6d]	7803	1			T1	21		T5	16		T6	13
valid_sources[0x6e]	17203	1			T1	18		T2	11		T5	9
valid_sources[0x6f]	7336	1			T1	18		T3	6		T5	11
valid_sources[0x70]	7548	1			T1	17		T2	3		T5	5
valid_sources[0x71]	14142	1			T1	3		T5	12		T6	9
valid_sources[0x72]	8376	1			T1	38		T5	11		T6	5
valid_sources[0x73]	7576	1			T1	11		T2	9		T5	8
valid_sources[0x74]	7196	1			T1	25		T2	3		T5	11
valid_sources[0x75]	12747	1			T1	32		T2	8		T3	2
valid_sources[0x76]	15176	1			T1	17		T2	5		T5	12
valid_sources[0x77]	7423	1			T1	9		T3	2		T5	13
valid_sources[0x78]	20060	1			T1	16		T5	11		T6	5
valid_sources[0x79]	11830	1			T1	7		T5	12		T6	15
valid_sources[0x7a]	7081	1			T1	4		T2	2		T5	16
valid_sources[0x7b]	7328	1			T1	23		T5	7		T6	4
valid_sources[0x7c]	7482	1			T1	21		T2	2		T5	8
valid_sources[0x7d]	8029	1			T1	9		T2	7		T3	1
valid_sources[0x7e]	8203	1			T1	23		T2	2		T5	6
valid_sources[0x7f]	12151	1			T1	19		T2	10		T5	20
valid_sources[0x80]	7629	1			T1	24		T5	9		T6	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1048805

1

T1

1993

T4

1

T3

35

values[0x0]

all_enables

biggest_size

81583

1

T1

59

T4

4

T2

184

values[0x1]

all_enables

biggest_size

58665

1

T1

39

T4

1

T2

164