Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
84.44	84.44	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	84.44	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	7	38	84.44

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	6	10	62.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	29782	1			T1	7		T2	168		T5	26
auto[PWRUP]	120	1			T2	2		T54	1		T57	2
auto[ONEST_0]	74	1			T56	1		T57	1		T55	2
auto[ONEST_021]	18	1			T54	1		T39	1		T196	2
auto[ONEST_1]	84	1			T2	2		T56	2		T58	3
auto[ONEST_DONE]	10	1			T17	2		T159	1		T95	1
auto[LP_0]	122	1			T2	2		T54	3		T56	4
auto[LP_021]	37	1			T39	1		T17	2		T42	1
auto[LP_1]	136	1			T2	2		T56	1		T57	1
auto[LP_EVAL]	74	1			T54	1		T56	1		T58	1
auto[LP_SLP]	547	1			T2	2		T54	2		T56	5
auto[LP_PWRUP]	25	1			T57	1		T58	1		T17	1
auto[NP_0]	142	1			T54	1		T57	1		T58	3
auto[NP_021]	41	1			T2	1		T54	3		T56	1
auto[NP_1]	184	1			T2	4		T56	2		T57	5
auto[NP_EVAL]	34	1			T58	1		T17	2		T197	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T58

1

T95

1

T198

1

min

29188

1

T1

7

T2

162

T5

26

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29201	1			T1	7		T2	162		T5	26
pow[0x1]	16	1			T2	1		T39	1		T199	1
pow[0x2]	21	1			T39	1		T200	2		T42	1
pow[0x3]	34	1			T54	1		T57	1		T39	1
pow[0x4]	68	1			T57	2		T39	1		T17	2
pow[0x5]	150	1			T2	3		T54	1		T56	2
pow[0x6]	267	1			T2	3		T54	4		T56	5
pow[0x7]	580	1			T2	4		T54	7		T56	8

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

216

1

T2

4

T56

2

T58

5

min

28680

1

T1

7

T2

160

T5

26

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	6	10	62.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28680	1			T1	7		T2	160		T5	26
pow[0x7]	4	1			T58	1		T18	1		T201	1
pow[0x8]	2	1			T58	1		T202	1		-	-
pow[0x9]	8	1			T56	1		T31	1		T163	1
pow[0xa]	18	1			T57	1		T55	1		T39	1
pow[0xb]	38	1			T54	1		T56	1		T57	1
pow[0xc]	84	1			T2	2		T56	2		T57	1
pow[0xd]	162	1			T2	1		T54	2		T56	3
pow[0xe]	307	1			T54	6		T56	3		T57	2
pow[0xf]	628	1			T2	10		T54	8		T56	7