Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2413	1			T2	18		T12	11		T54	9
auto[PWRUP]	149	1			T54	2		T56	1		T57	3
auto[ONEST_0]	87	1			T2	1		T56	1		T57	2
auto[ONEST_021]	24	1			T12	1		T55	1		T39	1
auto[ONEST_1]	90	1			T54	1		T57	1		T55	1
auto[ONEST_DONE]	3	1			T334	1		T102	1		T335	1
auto[LP_0]	140	1			T2	2		T54	1		T56	1
auto[LP_021]	30	1			T2	1		T54	1		T39	1
auto[LP_1]	149	1			T2	1		T54	3		T56	1
auto[LP_EVAL]	74	1			T12	1		T54	1		T56	1
auto[LP_SLP]	580	1			T2	7		T12	1		T54	4
auto[LP_PWRUP]	35	1			T2	1		T17	4		T197	1
auto[NP_0]	225	1			T2	2		T12	1		T54	2
auto[NP_021]	46	1			T2	1		T56	2		T57	1
auto[NP_1]	257	1			T12	4		T54	1		T56	3
auto[NP_EVAL]	34	1			T12	1		T39	1		T17	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

15

1

T17

1

T218

1

T95

1

min

2019

1

T2

11

T12

17

T54

6

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2031	1			T2	12		T12	18		T54	6
pow[0x1]	14	1			T56	1		T58	1		T197	1
pow[0x2]	30	1			T57	1		T58	2		T199	1
pow[0x3]	34	1			T39	2		T197	2		T18	1
pow[0x4]	63	1			T54	2		T31	1		T197	1
pow[0x5]	141	1			T56	2		T58	1		T55	3
pow[0x6]	282	1			T54	3		T56	4		T57	3
pow[0x7]	614	1			T2	9		T54	8		T56	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

189

1

T2

3

T54

1

T56

2

min

1357

1

T2

2

T12

12

T54

1

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1365	1			T2	2		T12	13		T54	1
pow[0x1]	13	1			T40	3		T17	1		T36	1
pow[0x2]	22	1			T17	1		T47	1		T20	1
pow[0x3]	33	1			T12	5		T48	3		T50	1
pow[0x4]	62	1			T39	1		T17	1		T42	2
pow[0x5]	1	1			T21	1		-	-		-	-
pow[0x6]	2	1			T336	1		T317	1		-	-
pow[0x7]	1	1			T337	1		-	-		-	-
pow[0x8]	5	1			T200	1		T338	1		T262	1
pow[0x9]	6	1			T58	1		T197	1		T199	1
pow[0xa]	19	1			T54	1		T58	1		T55	1
pow[0xb]	42	1			T2	1		T39	1		T200	1
pow[0xc]	85	1			T56	3		T55	2		T39	1
pow[0xd]	175	1			T2	3		T56	1		T57	2
pow[0xe]	350	1			T2	2		T54	3		T56	5
pow[0xf]	684	1			T2	6		T12	2		T54	4