Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	100.00	99.76		100.00	99.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	99.75	100.00	100.00		100.00	98.73	100.00
u_adc_ctrl_intr	99.00	100.00	96.00			100.00	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	213	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	8	8
63	8	8
72	1	1
73	1	1
74	1	1
75	1	1
83	1	1
86	1	1
87	1	1
88	1	1
89	1	1
104	8	8
107	8	8
117	8	8
121	8	8
137	1	1
138	1	1
140	1	1
141	1	1
145	1	1
213	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	293	293	100.00
Logical	293	293	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T3,T9

 LINE       83
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T5

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T10,T12,T13
1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T14
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T12,T13

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T1,T10,T12
1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T10
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T13
0	1	Covered	T1,T10,T13
1	0	Covered	T1,T10,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T1,T10,T12
1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T10
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T13
0	1	Covered	T1,T10,T13
1	0	Covered	T1,T10,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T1,T6,T10
1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T12
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T10
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T6,T10

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T1,T6,T10
1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T13
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T10
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T6,T10

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T1,T13,T14
1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T10
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T13,T14
0	1	Covered	T1,T13,T14
1	0	Covered	T1,T13,T14

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T10,T12,T13
1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T13
0	1	Covered	T10,T12,T13
1	0	Covered	T10,T13,T41

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T5,T6,T13
1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T13
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T13
0	1	Covered	T5,T6,T13
1	0	Covered	T5,T6,T13

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T10,T12,T13
1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T14
0	1	Covered	T10,T13,T14
1	0	Covered	T10,T12,T13

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T10,T12,T13
1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T41
0	1	Covered	T10,T13,T41
1	0	Covered	T10,T12,T13

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T1,T10,T12
1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T10
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T13
0	1	Covered	T1,T10,T13
1	0	Covered	T1,T10,T12

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T1,T6,T10
1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T12
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T10
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T6,T10

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T1,T6,T10
1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T13
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T10
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T6,T10

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T1,T13,T14
1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T10
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T13,T14
0	1	Covered	T1,T13,T14
1	0	Covered	T1,T13,T14

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T10,T12,T13
1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T13
0	1	Covered	T10,T12,T13
1	0	Covered	T10,T12,T13

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T5,T13,T14
1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T13,T14
0	1	Covered	T5,T13,T14
1	0	Covered	T5,T13,T14

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T1,T5,T10
1	1	0	Covered	T1,T5,T10
1	1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T10
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T10
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T10
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T10
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T2,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T1,T5,T6
1	1	0	Covered	T1,T5,T6
1	1	1	Covered	T5,T6,T12

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T5,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T5,T10,T13
1	1	0	Covered	T5,T10,T13
1	1	1	Covered	T5,T10,T12

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T13
0	1	Covered	T5,T10,T12
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T13
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T10,T12

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T13
0	1	Covered	T5,T10,T12
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T13
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T10,T12

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T5,T6,T10
1	1	0	Covered	T5,T6,T10
1	1	1	Covered	T5,T6,T10

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T10
0	1	Covered	T5,T6,T10
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T10
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T6,T10

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T10
0	1	Covered	T5,T6,T10
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T10
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T6,T10

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T5,T10,T13
1	1	0	Covered	T5,T10,T13
1	1	1	Covered	T5,T10,T13

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T13
0	1	Covered	T5,T10,T13
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T13
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T10,T13

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T13
0	1	Covered	T5,T10,T13
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T13
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T10,T13

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T5,T10,T14
1	1	0	Covered	T5,T10,T14
1	1	1	Covered	T5,T10,T14

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T12
0	1	Covered	T5,T10,T14
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T12
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T10,T14

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T12
0	1	Covered	T5,T10,T14
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T12
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T10,T14

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T5,T6,T10
1	1	0	Covered	T1,T5,T6
1	1	1	Covered	T1,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T5,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T5,T6,T10
1	1	0	Covered	T5,T6,T10
1	1	1	Covered	T5,T6,T10

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T10
0	1	Covered	T5,T6,T10
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T10
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T6,T10

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T10
0	1	Covered	T5,T6,T10
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T10
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T6,T10

 LINE       121
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T2,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T12
1	0	Covered	T1,T2,T5
1	1	Covered	T5,T6,T12

 LINE       121
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T12
1	0	Covered	T1,T2,T5
1	1	Covered	T5,T10,T12

 LINE       121
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T10
1	0	Covered	T1,T2,T5
1	1	Covered	T5,T6,T10

 LINE       121
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T13
1	0	Covered	T1,T2,T5
1	1	Covered	T5,T10,T13

 LINE       121
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T14
1	0	Covered	T1,T2,T5
1	1	Covered	T5,T10,T14

 LINE       121
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T5,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T10
1	0	Covered	T1,T2,T5
1	1	Covered	T5,T6,T10

 LINE       140
 EXPRESSION (aon_fsm_trans | reg2hw_i.filter_status.trans.q)
             ------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T5,T6,T10
1	0	Covered	T5,T6,T10

 LINE       145
 EXPRESSION (((|(reg2hw_i.filter_status.match.q & reg2hw_i.adc_wakeup_ctl.match_en.q))) || (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q))
             -------------------------------------1------------------------------------    ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T5,T10,T12
1	0	Covered	T5,T6,T10

 LINE       145
 SUB-EXPRESSION (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q)
                 ---------------1--------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T12
1	0	Covered	T5,T6,T12
1	1	Covered	T5,T10,T12

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	83	3	3	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	83	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T9
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T10,T12,T13

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T10,T12,T13

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T10,T12

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T10,T12,T13

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T10,T12

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T10,T12

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T6,T10

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T6,T10

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T6,T10

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T6,T10

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T13,T14

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T13,T14

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T10,T12,T13

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T10,T12,T13

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T5,T6,T13

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T5,T13,T14

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	35903631	35569388	0	0
gen_filter_match[0].MatchCheck00_A	35903631	10564428	0	0
gen_filter_match[0].MatchCheck01_A	35903631	2453928	0	0
gen_filter_match[0].MatchCheck10_A	35903631	2462971	0	0
gen_filter_match[0].MatchCheck11_A	35903631	20088061	0	0
gen_filter_match[1].MatchCheck00_A	35903631	12251495	0	0
gen_filter_match[1].MatchCheck01_A	35903631	1162402	0	0
gen_filter_match[1].MatchCheck10_A	35903631	1219041	0	0
gen_filter_match[1].MatchCheck11_A	35903631	20936450	0	0
gen_filter_match[2].MatchCheck00_A	35903631	14053094	0	0
gen_filter_match[2].MatchCheck01_A	35903631	870394	0	0
gen_filter_match[2].MatchCheck10_A	35903631	724652	0	0
gen_filter_match[2].MatchCheck11_A	35903631	19921248	0	0
gen_filter_match[3].MatchCheck00_A	35903631	14208645	0	0
gen_filter_match[3].MatchCheck01_A	35903631	668648	0	0
gen_filter_match[3].MatchCheck10_A	35903631	378143	0	0
gen_filter_match[3].MatchCheck11_A	35903631	20313952	0	0
gen_filter_match[4].MatchCheck00_A	35903631	14703848	0	0
gen_filter_match[4].MatchCheck01_A	35903631	14	0	0
gen_filter_match[4].MatchCheck10_A	35903631	109	0	0
gen_filter_match[4].MatchCheck11_A	35903631	20865417	0	0
gen_filter_match[5].MatchCheck00_A	35903631	13426723	0	0
gen_filter_match[5].MatchCheck01_A	35903631	32269	0	0
gen_filter_match[5].MatchCheck10_A	35903631	99674	0	0
gen_filter_match[5].MatchCheck11_A	35903631	22010722	0	0
gen_filter_match[6].MatchCheck00_A	35903631	13625598	0	0
gen_filter_match[6].MatchCheck01_A	35903631	260109	0	0
gen_filter_match[6].MatchCheck10_A	35903631	70932	0	0
gen_filter_match[6].MatchCheck11_A	35903631	21612749	0	0
gen_filter_match[7].MatchCheck00_A	35903631	13140087	0	0
gen_filter_match[7].MatchCheck01_A	35903631	174543	0	0
gen_filter_match[7].MatchCheck10_A	35903631	236685	0	0
gen_filter_match[7].MatchCheck11_A	35903631	22018073	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	35569388	0	0
T1	32397	32313	0	0
T2	19302	16604	0	0
T3	1159	1073	0	0
T4	74	6	0	0
T5	122212	122116	0	0
T6	36991	36925	0	0
T7	4849	4784	0	0
T8	4455	4366	0	0
T9	1013	937	0	0
T10	124864	124775	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	10564428	0	0
T1	32397	4	0	0
T2	19302	15949	0	0
T3	1159	1073	0	0
T4	74	6	0	0
T5	122212	3	0	0
T6	36991	36925	0	0
T7	4849	4784	0	0
T8	4455	4366	0	0
T9	1013	937	0	0
T10	124864	50268	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	2453928	0	0
T10	124864	34574	0	0
T11	1170	0	0	0
T12	36319	0	0	0
T13	111949	0	0	0
T14	87617	0	0	0
T15	40804	0	0	0
T16	123822	0	0	0
T39	0	6242	0	0
T41	64513	0	0	0
T43	1157	0	0	0
T44	65069	0	0	0
T46	0	40489	0	0
T147	0	32196	0	0
T148	0	32338	0	0
T149	0	33641	0	0
T150	0	33108	0	0
T151	0	35880	0	0
T152	0	33349	0	0
T153	0	33646	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	2462971	0	0
T10	124864	39933	0	0
T11	1170	0	0	0
T12	36319	0	0	0
T13	111949	0	0	0
T14	87617	33356	0	0
T15	40804	1	0	0
T16	123822	0	0	0
T41	64513	31992	0	0
T43	1157	0	0	0
T44	65069	0	0	0
T53	0	36102	0	0
T90	0	32730	0	0
T154	0	2	0	0
T155	0	36330	0	0
T156	0	35740	0	0
T157	0	73953	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	20088061	0	0
T1	32397	32309	0	0
T2	19302	655	0	0
T3	1159	0	0	0
T4	74	0	0	0
T5	122212	122113	0	0
T6	36991	0	0	0
T7	4849	0	0	0
T8	4455	0	0	0
T9	1013	0	0	0
T10	124864	0	0	0
T12	0	207	0	0
T13	0	73917	0	0
T15	0	40746	0	0
T16	0	123747	0	0
T41	0	32429	0	0
T44	0	64986	0	0
T148	0	64522	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	12251495	0	0
T1	32397	4	0	0
T2	19302	16604	0	0
T3	1159	1073	0	0
T4	74	6	0	0
T5	122212	3	0	0
T6	36991	4	0	0
T7	4849	4784	0	0
T8	4455	4366	0	0
T9	1013	937	0	0
T10	124864	124775	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	1162402	0	0
T44	65069	32569	0	0
T45	33161	0	0	0
T46	74692	0	0	0
T50	0	5659	0	0
T53	73489	0	0	0
T54	16051	0	0	0
T100	0	50358	0	0
T108	0	2	0	0
T145	66826	0	0	0
T147	32287	0	0	0
T148	96921	0	0	0
T158	0	32599	0	0
T159	0	32498	0	0
T160	0	31924	0	0
T161	0	33450	0	0
T162	0	34311	0	0
T163	0	33330	0	0
T164	33063	0	0	0
T165	98315	0	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	1219041	0	0
T14	87617	54203	0	0
T15	40804	1	0	0
T16	123822	0	0	0
T17	0	12	0	0
T41	64513	0	0	0
T44	65069	0	0	0
T45	33161	0	0	0
T46	74692	0	0	0
T53	73489	0	0	0
T108	0	2	0	0
T147	32287	0	0	0
T154	0	2	0	0
T164	33063	0	0	0
T166	0	1	0	0
T167	0	32363	0	0
T168	0	32817	0	0
T169	0	32293	0	0
T170	0	31634	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	20936450	0	0
T1	32397	32309	0	0
T2	19302	0	0	0
T3	1159	0	0	0
T4	74	0	0	0
T5	122212	122113	0	0
T6	36991	36921	0	0
T7	4849	0	0	0
T8	4455	0	0	0
T9	1013	0	0	0
T10	124864	0	0	0
T12	0	34761	0	0
T15	0	40746	0	0
T16	0	123747	0	0
T41	0	64421	0	0
T44	0	32417	0	0
T46	0	74628	0	0
T53	0	37306	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	14053094	0	0
T1	32397	32313	0	0
T2	19302	16604	0	0
T3	1159	1073	0	0
T4	74	6	0	0
T5	122212	3	0	0
T6	36991	36925	0	0
T7	4849	4784	0	0
T8	4455	4366	0	0
T9	1013	937	0	0
T10	124864	74511	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	870394	0	0
T33	0	1	0	0
T54	16051	0	0	0
T98	0	1	0	0
T108	0	2	0	0
T145	66826	0	0	0
T146	1150	0	0	0
T148	96921	32135	0	0
T149	100204	0	0	0
T150	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T160	0	4	0	0
T165	98315	0	0	0
T171	0	37538	0	0
T172	0	32011	0	0
T173	66532	0	0	0
T174	40436	0	0	0
T175	124358	0	0	0
T176	33357	0	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	724652	0	0
T13	111949	1	0	0
T14	87617	0	0	0
T15	40804	1	0	0
T16	123822	0	0	0
T41	64513	0	0	0
T44	65069	0	0	0
T45	33161	0	0	0
T46	74692	34139	0	0
T53	73489	0	0	0
T74	0	33955	0	0
T84	0	1	0	0
T147	32287	0	0	0
T151	0	1	0	0
T154	0	33416	0	0
T166	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	19921248	0	0
T5	122212	122113	0	0
T6	36991	0	0	0
T7	4849	0	0	0
T8	4455	0	0	0
T9	1013	0	0	0
T10	124864	50264	0	0
T11	1170	0	0	0
T12	36319	34761	0	0
T13	111949	73916	0	0
T15	0	40746	0	0
T16	0	123747	0	0
T41	0	64421	0	0
T43	1157	0	0	0
T44	0	32417	0	0
T46	0	40489	0	0
T53	0	36102	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	14208645	0	0
T1	32397	32313	0	0
T2	19302	16604	0	0
T3	1159	1073	0	0
T4	74	6	0	0
T5	122212	3	0	0
T6	36991	4	0	0
T7	4849	4784	0	0
T8	4455	4366	0	0
T9	1013	937	0	0
T10	124864	74511	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	668648	0	0
T13	111949	1	0	0
T14	87617	0	0	0
T15	40804	0	0	0
T16	123822	0	0	0
T33	0	1	0	0
T41	64513	0	0	0
T44	65069	0	0	0
T45	33161	0	0	0
T46	74692	0	0	0
T53	73489	0	0	0
T84	0	1	0	0
T147	32287	0	0	0
T160	0	33457	0	0
T165	0	32964	0	0
T177	0	1	0	0
T179	0	32713	0	0
T180	0	34625	0	0
T181	0	34146	0	0
T182	0	1	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	378143	0	0
T13	111949	1	0	0
T14	87617	0	0	0
T15	40804	1	0	0
T16	123822	0	0	0
T17	0	25	0	0
T33	0	1	0	0
T41	64513	0	0	0
T44	65069	0	0	0
T45	33161	0	0	0
T46	74692	0	0	0
T53	73489	0	0	0
T147	32287	0	0	0
T151	0	1	0	0
T156	0	1	0	0
T166	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T183	0	31867	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	20313952	0	0
T5	122212	122113	0	0
T6	36991	36921	0	0
T7	4849	0	0	0
T8	4455	0	0	0
T9	1013	0	0	0
T10	124864	50264	0	0
T11	1170	0	0	0
T12	36319	0	0	0
T13	111949	37973	0	0
T15	0	40746	0	0
T16	0	123747	0	0
T43	1157	0	0	0
T44	0	32417	0	0
T46	0	34139	0	0
T53	0	37306	0	0
T147	0	32196	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	14703848	0	0
T1	32397	32313	0	0
T2	19302	16604	0	0
T3	1159	1073	0	0
T4	74	6	0	0
T5	122212	3	0	0
T6	36991	36925	0	0
T7	4849	4784	0	0
T8	4455	4366	0	0
T9	1013	937	0	0
T10	124864	50268	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	14	0	0
T13	111949	1	0	0
T14	87617	0	0	0
T15	40804	0	0	0
T16	123822	0	0	0
T41	64513	0	0	0
T44	65069	0	0	0
T45	33161	0	0	0
T46	74692	0	0	0
T53	73489	0	0	0
T108	0	1	0	0
T147	32287	0	0	0
T150	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	0	2	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	109	0	0
T13	111949	1	0	0
T14	87617	0	0	0
T15	40804	1	0	0
T16	123822	0	0	0
T17	0	30	0	0
T41	64513	0	0	0
T44	65069	0	0	0
T45	33161	0	0	0
T46	74692	0	0	0
T53	73489	0	0	0
T84	0	1	0	0
T147	32287	0	0	0
T150	0	2	0	0
T156	0	1	0	0
T166	0	1	0	0
T168	0	1	0	0
T175	0	1	0	0
T178	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	20865417	0	0
T5	122212	122113	0	0
T6	36991	0	0	0
T7	4849	0	0	0
T8	4455	0	0	0
T9	1013	0	0	0
T10	124864	74507	0	0
T11	1170	0	0	0
T12	36319	0	0	0
T13	111949	37973	0	0
T14	0	87559	0	0
T15	0	40746	0	0
T16	0	123747	0	0
T43	1157	0	0	0
T44	0	64986	0	0
T46	0	74628	0	0
T53	0	36102	0	0
T164	0	32988	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	13426723	0	0
T1	32397	32313	0	0
T2	19302	16604	0	0
T3	1159	1073	0	0
T4	74	6	0	0
T5	122212	3	0	0
T6	36991	36925	0	0
T7	4849	4784	0	0
T8	4455	4366	0	0
T9	1013	937	0	0
T10	124864	34578	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	32269	0	0
T33	0	1	0	0
T44	65069	1	0	0
T45	33161	0	0	0
T46	74692	0	0	0
T53	73489	0	0	0
T54	16051	0	0	0
T98	0	1	0	0
T145	66826	0	0	0
T147	32287	0	0	0
T148	96921	0	0	0
T151	0	1	0	0
T156	0	1	0	0
T162	0	1	0	0
T164	33063	0	0	0
T165	98315	0	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T191	0	32247	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	99674	0	0
T15	40804	1	0	0
T16	123822	0	0	0
T41	64513	0	0	0
T44	65069	0	0	0
T45	33161	0	0	0
T46	74692	0	0	0
T53	73489	0	0	0
T84	0	1	0	0
T147	32287	0	0	0
T148	96921	0	0	0
T150	0	33401	0	0
T151	0	1	0	0
T154	0	3	0	0
T156	0	1	0	0
T164	33063	0	0	0
T166	0	1	0	0
T175	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	22010722	0	0
T5	122212	122113	0	0
T6	36991	0	0	0
T7	4849	0	0	0
T8	4455	0	0	0
T9	1013	0	0	0
T10	124864	90197	0	0
T11	1170	0	0	0
T12	36319	34761	0	0
T13	111949	0	0	0
T14	0	87559	0	0
T15	0	40746	0	0
T16	0	123747	0	0
T41	0	64421	0	0
T43	1157	0	0	0
T44	0	32569	0	0
T46	0	34139	0	0
T53	0	37306	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	13625598	0	0
T1	32397	4	0	0
T2	19302	16604	0	0
T3	1159	1073	0	0
T4	74	6	0	0
T5	122212	3	0	0
T6	36991	4	0	0
T7	4849	4784	0	0
T8	4455	4366	0	0
T9	1013	937	0	0
T10	124864	74511	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	260109	0	0
T13	111949	1	0	0
T14	87617	0	0	0
T15	40804	0	0	0
T16	123822	0	0	0
T17	0	39361	0	0
T41	64513	0	0	0
T44	65069	0	0	0
T45	33161	0	0	0
T46	74692	0	0	0
T53	73489	0	0	0
T104	0	54088	0	0
T107	0	1	0	0
T108	0	2	0	0
T147	32287	0	0	0
T150	0	1	0	0
T153	0	1	0	0
T156	0	1	0	0
T160	0	3	0	0
T169	0	33135	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	70932	0	0
T13	111949	2	0	0
T14	87617	0	0	0
T15	40804	2	0	0
T16	123822	0	0	0
T41	64513	0	0	0
T44	65069	1	0	0
T45	33161	0	0	0
T46	74692	0	0	0
T53	73489	0	0	0
T147	32287	0	0	0
T150	0	2	0	0
T151	0	1	0	0
T166	0	1	0	0
T175	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T192	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	21612749	0	0
T1	32397	32309	0	0
T2	19302	0	0	0
T3	1159	0	0	0
T4	74	0	0	0
T5	122212	122113	0	0
T6	36991	36921	0	0
T7	4849	0	0	0
T8	4455	0	0	0
T9	1013	0	0	0
T10	124864	50264	0	0
T13	0	73915	0	0
T14	0	54203	0	0
T15	0	40745	0	0
T16	0	123747	0	0
T41	0	64421	0	0
T44	0	32416	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	13140087	0	0
T1	32397	32313	0	0
T2	19302	16604	0	0
T3	1159	1073	0	0
T4	74	6	0	0
T5	122212	3	0	0
T6	36991	4	0	0
T7	4849	4784	0	0
T8	4455	4366	0	0
T9	1013	937	0	0
T10	124864	74511	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	174543	0	0
T12	36319	34761	0	0
T13	111949	0	0	0
T14	87617	0	0	0
T15	40804	0	0	0
T16	123822	0	0	0
T33	0	1	0	0
T41	64513	0	0	0
T43	1157	0	0	0
T44	65069	0	0	0
T45	33161	0	0	0
T46	74692	0	0	0
T98	0	1	0	0
T108	0	31743	0	0
T160	0	3	0	0
T161	0	39475	0	0
T188	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	236685	0	0
T13	111949	1	0	0
T14	87617	0	0	0
T15	40804	1	0	0
T16	123822	0	0	0
T41	64513	0	0	0
T44	65069	0	0	0
T45	33161	0	0	0
T46	74692	0	0	0
T53	73489	0	0	0
T84	0	1	0	0
T147	32287	0	0	0
T150	0	1	0	0
T154	0	2	0	0
T166	0	1	0	0
T173	0	33492	0	0
T175	0	1	0	0
T178	0	1	0	0
T192	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35903631	22018073	0	0
T5	122212	122113	0	0
T6	36991	36921	0	0
T7	4849	0	0	0
T8	4455	0	0	0
T9	1013	0	0	0
T10	124864	50264	0	0
T11	1170	0	0	0
T12	36319	0	0	0
T13	111949	74131	0	0
T15	0	40745	0	0
T16	0	123747	0	0
T43	1157	0	0	0
T45	0	33103	0	0
T46	0	34139	0	0
T148	0	32135	0	0
T164	0	32988	0	0