Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1733	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1764	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1900	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1881	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1737	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1769	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1665	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1804	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1692	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1741	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1765	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1882	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1720	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1917	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2012	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1868	0	0
adc_en_ctl_rd_A	2147483647	1350	0	0
adc_fsm_rst_rd_A	2147483647	1182	0	0
adc_intr_ctl_rd_A	2147483647	1548	0	0
adc_lp_sample_ctl_rd_A	2147483647	1199	0	0
adc_pd_ctl_rd_A	2147483647	1610	0	0
adc_sample_ctl_rd_A	2147483647	1208	0	0
adc_wakeup_ctl_rd_A	2147483647	1449	0	0
intr_enable_rd_A	2147483647	1548	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1733	0	0
T17	110740	36	0	0
T18	0	20	0	0
T19	0	32	0	0
T20	0	4	0	0
T21	0	33	0	0
T22	0	21	0	0
T23	0	9	0	0
T24	0	22	0	0
T25	0	23	0	0
T26	0	37	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1764	0	0
T17	110740	34	0	0
T18	0	17	0	0
T19	0	46	0	0
T20	0	15	0	0
T21	0	19	0	0
T22	0	43	0	0
T23	0	7	0	0
T24	0	30	0	0
T25	0	26	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0
T36	0	6	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1900	0	0
T17	110740	26	0	0
T18	0	14	0	0
T19	0	50	0	0
T20	0	17	0	0
T21	0	13	0	0
T22	0	29	0	0
T23	0	33	0	0
T24	0	42	0	0
T25	0	31	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0
T36	0	20	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1881	0	0
T17	110740	35	0	0
T18	0	15	0	0
T19	0	36	0	0
T20	0	19	0	0
T21	0	13	0	0
T22	0	36	0	0
T23	0	12	0	0
T24	0	32	0	0
T25	0	8	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0
T36	0	4	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1737	0	0
T17	110740	9	0	0
T18	0	27	0	0
T19	0	53	0	0
T20	0	11	0	0
T21	0	25	0	0
T22	0	23	0	0
T23	0	17	0	0
T24	0	27	0	0
T25	0	16	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0
T36	0	11	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1769	0	0
T17	110740	29	0	0
T18	0	13	0	0
T19	0	39	0	0
T20	0	17	0	0
T21	0	19	0	0
T22	0	27	0	0
T23	0	16	0	0
T24	0	29	0	0
T25	0	26	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0
T36	0	16	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1665	0	0
T17	110740	29	0	0
T18	0	18	0	0
T19	0	34	0	0
T21	0	18	0	0
T22	0	36	0	0
T23	0	17	0	0
T24	0	28	0	0
T25	0	17	0	0
T26	0	40	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0
T36	0	10	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1804	0	0
T17	110740	32	0	0
T18	0	8	0	0
T19	0	26	0	0
T20	0	12	0	0
T21	0	33	0	0
T22	0	27	0	0
T23	0	22	0	0
T24	0	43	0	0
T25	0	25	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0
T36	0	16	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1692	0	0
T17	110740	18	0	0
T18	0	14	0	0
T19	0	30	0	0
T20	0	18	0	0
T21	0	19	0	0
T22	0	35	0	0
T23	0	11	0	0
T24	0	38	0	0
T25	0	18	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0
T36	0	6	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1741	0	0
T17	110740	37	0	0
T18	0	10	0	0
T19	0	34	0	0
T20	0	12	0	0
T21	0	15	0	0
T22	0	37	0	0
T23	0	11	0	0
T24	0	45	0	0
T25	0	9	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0
T36	0	10	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1765	0	0
T17	110740	30	0	0
T18	0	8	0	0
T19	0	33	0	0
T20	0	1	0	0
T21	0	14	0	0
T22	0	33	0	0
T23	0	13	0	0
T24	0	23	0	0
T25	0	14	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0
T36	0	8	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1882	0	0
T17	110740	25	0	0
T18	0	17	0	0
T19	0	44	0	0
T20	0	14	0	0
T21	0	16	0	0
T22	0	40	0	0
T23	0	12	0	0
T24	0	23	0	0
T25	0	18	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0
T36	0	10	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1720	0	0
T17	110740	27	0	0
T18	0	14	0	0
T19	0	40	0	0
T20	0	9	0	0
T21	0	28	0	0
T22	0	31	0	0
T23	0	15	0	0
T24	0	32	0	0
T25	0	26	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0
T36	0	7	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1917	0	0
T17	110740	34	0	0
T18	0	12	0	0
T19	0	37	0	0
T20	0	8	0	0
T21	0	12	0	0
T22	0	39	0	0
T23	0	16	0	0
T24	0	17	0	0
T25	0	2	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0
T36	0	10	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2012	0	0
T17	110740	22	0	0
T18	0	27	0	0
T19	0	46	0	0
T20	0	16	0	0
T21	0	27	0	0
T22	0	32	0	0
T23	0	8	0	0
T24	0	19	0	0
T25	0	26	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0
T36	0	6	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1868	0	0
T17	110740	41	0	0
T18	0	6	0	0
T19	0	47	0	0
T20	0	6	0	0
T21	0	25	0	0
T22	0	36	0	0
T23	0	19	0	0
T24	0	24	0	0
T25	0	17	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0
T36	0	11	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1350	0	0
T17	110740	36	0	0
T18	0	17	0	0
T19	0	39	0	0
T21	0	35	0	0
T22	0	22	0	0
T23	0	21	0	0
T24	0	23	0	0
T25	0	19	0	0
T26	0	40	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0
T36	0	13	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1182	0	0
T17	110740	24	0	0
T18	0	16	0	0
T19	0	32	0	0
T20	0	17	0	0
T21	0	20	0	0
T22	0	31	0	0
T23	0	10	0	0
T24	0	30	0	0
T25	0	13	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0
T36	0	8	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1548	0	0
T17	110740	22	0	0
T18	0	10	0	0
T19	0	55	0	0
T20	0	12	0	0
T21	0	9	0	0
T22	0	29	0	0
T23	0	11	0	0
T24	0	26	0	0
T25	0	15	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0
T36	0	5	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1199	0	0
T17	110740	27	0	0
T18	0	17	0	0
T19	0	45	0	0
T20	0	2	0	0
T21	0	28	0	0
T22	0	32	0	0
T23	0	15	0	0
T24	0	42	0	0
T25	0	17	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0
T36	0	8	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1610	0	0
T17	110740	41	0	0
T18	0	23	0	0
T19	0	37	0	0
T20	0	12	0	0
T21	0	20	0	0
T22	0	23	0	0
T23	0	19	0	0
T24	0	25	0	0
T25	0	29	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0
T36	0	4	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1208	0	0
T17	110740	28	0	0
T18	0	3	0	0
T19	0	55	0	0
T20	0	1	0	0
T21	0	35	0	0
T22	0	32	0	0
T23	0	18	0	0
T24	0	16	0	0
T25	0	18	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0
T36	0	1	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1449	0	0
T17	110740	34	0	0
T18	0	22	0	0
T19	0	36	0	0
T20	0	3	0	0
T21	0	25	0	0
T22	0	46	0	0
T23	0	13	0	0
T24	0	19	0	0
T25	0	8	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0
T36	0	22	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1548	0	0
T17	110740	47	0	0
T18	0	7	0	0
T19	0	33	0	0
T20	0	5	0	0
T21	0	25	0	0
T22	0	81	0	0
T23	0	32	0	0
T27	299322	0	0	0
T28	41032	0	0	0
T29	10981	0	0	0
T30	15575	0	0	0
T31	947240	0	0	0
T32	171627	0	0	0
T33	115813	0	0	0
T34	261526	0	0	0
T35	9261	0	0	0
T36	0	14	0	0
T37	0	12	0	0
T38	0	18	0	0