Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1241148	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1215513

1

T1

929

T2

1445

T3

923

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2153084	1			T1	1665		T2	2551		T3	943
values[0x0]	151622	1			T1	99		T2	177		T3	522
values[0x1]	151955	1			T1	105		T2	148		T3	520

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	993853	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1462808

1

T1

1123

T2

1720

T3

1115

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7169	1			T1	7		T2	8		T3	6
valid_sources[0x01]	8893	1			T1	10		T2	10		T3	13
valid_sources[0x02]	15038	1			T1	2		T2	2		T3	9
valid_sources[0x03]	13593	1			T1	6		T2	1		T3	12
valid_sources[0x04]	13130	1			T1	3		T2	3		T4	55
valid_sources[0x05]	7042	1			T1	3		T2	5		T3	7
valid_sources[0x06]	7961	1			T1	10		T2	6		T3	17
valid_sources[0x07]	8259	1			T1	5		T2	3		T3	7
valid_sources[0x08]	6837	1			T1	12		T2	6		T3	5
valid_sources[0x09]	6961	1			T1	6		T3	10		T4	40
valid_sources[0x0a]	8217	1			T1	12		T2	6		T3	9
valid_sources[0x0b]	10597	1			T1	9		T2	4		T3	10
valid_sources[0x0c]	11445	1			T1	6		T2	6		T3	11
valid_sources[0x0d]	7932	1			T1	2		T2	2		T3	8
valid_sources[0x0e]	7129	1			T1	13		T3	7		T4	31
valid_sources[0x0f]	11291	1			T1	10		T2	9		T3	1
valid_sources[0x10]	13887	1			T1	12		T3	11		T4	37
valid_sources[0x11]	9813	1			T1	4		T2	11		T3	10
valid_sources[0x12]	6955	1			T1	12		T2	2		T3	3
valid_sources[0x13]	17550	1			T1	4		T2	9		T3	21
valid_sources[0x14]	6881	1			T1	6		T3	10		T4	50
valid_sources[0x15]	6908	1			T1	5		T2	12		T3	2
valid_sources[0x16]	24300	1			T1	14		T2	1		T3	7
valid_sources[0x17]	11518	1			T1	4		T2	2		T3	4
valid_sources[0x18]	7402	1			T1	12		T3	18		T4	69
valid_sources[0x19]	7208	1			T1	11		T3	3		T4	99
valid_sources[0x1a]	7197	1			T1	14		T2	4		T3	11
valid_sources[0x1b]	6740	1			T1	10		T2	2		T4	35
valid_sources[0x1c]	11344	1			T1	3		T3	24		T4	74
valid_sources[0x1d]	7086	1			T1	8		T3	12		T4	56
valid_sources[0x1e]	6978	1			T1	3		T2	1		T3	18
valid_sources[0x1f]	8144	1			T1	7		T2	8		T3	9
valid_sources[0x20]	6807	1			T1	9		T2	2		T3	5
valid_sources[0x21]	12319	1			T1	7		T2	8		T3	4
valid_sources[0x22]	11786	1			T1	8		T2	3		T3	4
valid_sources[0x23]	7008	1			T1	12		T2	2		T3	2
valid_sources[0x24]	7912	1			T1	8		T2	2		T3	13
valid_sources[0x25]	9659	1			T1	12		T3	6		T4	52
valid_sources[0x26]	9610	1			T1	4		T2	5		T3	3
valid_sources[0x27]	7520	1			T1	12		T2	11		T3	3
valid_sources[0x28]	7477	1			T1	6		T2	6		T3	14
valid_sources[0x29]	9149	1			T1	13		T2	10		T3	6
valid_sources[0x2a]	6670	1			T1	8		T2	3		T3	4
valid_sources[0x2b]	13728	1			T1	9		T2	2		T3	1
valid_sources[0x2c]	7404	1			T1	9		T2	2		T3	5
valid_sources[0x2d]	11328	1			T1	13		T3	6		T4	68
valid_sources[0x2e]	11490	1			T1	9		T3	23		T4	57
valid_sources[0x2f]	7537	1			T1	9		T2	4		T3	11
valid_sources[0x30]	9078	1			T1	9		T2	3		T3	7
valid_sources[0x31]	11072	1			T1	7		T2	6		T3	10
valid_sources[0x32]	10880	1			T1	2		T2	8		T3	6
valid_sources[0x33]	7102	1			T1	2		T2	1		T3	1
valid_sources[0x34]	10226	1			T1	5		T2	1		T3	3
valid_sources[0x35]	8099	1			T1	11		T2	5		T4	63
valid_sources[0x36]	8236	1			T1	5		T3	5		T4	30
valid_sources[0x37]	6923	1			T1	13		T2	9		T3	1
valid_sources[0x38]	11588	1			T1	7		T2	3		T4	73
valid_sources[0x39]	7216	1			T1	5		T2	12		T3	9
valid_sources[0x3a]	12229	1			T1	7		T2	2		T3	9
valid_sources[0x3b]	6934	1			T1	10		T3	3		T4	77
valid_sources[0x3c]	6924	1			T1	8		T3	7		T4	53
valid_sources[0x3d]	7392	1			T1	3		T2	15		T3	2
valid_sources[0x3e]	7964	1			T1	4		T2	2		T3	22
valid_sources[0x3f]	7906	1			T1	7		T2	4		T3	12
valid_sources[0x40]	6962	1			T1	6		T3	3		T4	26
valid_sources[0x41]	7961	1			T1	14		T2	946		T3	6
valid_sources[0x42]	11468	1			T1	10		T2	3		T3	2
valid_sources[0x43]	7826	1			T1	8		T2	3		T3	5
valid_sources[0x44]	6817	1			T1	7		T2	7		T3	2
valid_sources[0x45]	15688	1			T1	6		T2	5		T3	15
valid_sources[0x46]	7280	1			T1	9		T2	8		T3	10
valid_sources[0x47]	7404	1			T1	10		T2	2		T3	8
valid_sources[0x48]	7719	1			T1	5		T2	1		T3	12
valid_sources[0x49]	8317	1			T1	4		T2	1		T3	13
valid_sources[0x4a]	10894	1			T1	5		T2	2		T3	25
valid_sources[0x4b]	11420	1			T1	5		T2	1		T3	7
valid_sources[0x4c]	7229	1			T1	13		T2	4		T3	20
valid_sources[0x4d]	7143	1			T1	21		T2	9		T3	13
valid_sources[0x4e]	11612	1			T3	7		T4	58		T5	24
valid_sources[0x4f]	7659	1			T1	4		T2	2		T3	6
valid_sources[0x50]	7080	1			T1	5		T2	2		T3	17
valid_sources[0x51]	6847	1			T2	6		T3	5		T4	65
valid_sources[0x52]	6841	1			T1	3		T2	5		T3	10
valid_sources[0x53]	12505	1			T1	6		T2	7		T3	12
valid_sources[0x54]	11034	1			T1	3		T2	7		T3	6
valid_sources[0x55]	6930	1			T1	17		T2	4		T3	21
valid_sources[0x56]	6530	1			T1	8		T3	2		T4	47
valid_sources[0x57]	12257	1			T1	3		T2	7		T3	7
valid_sources[0x58]	7959	1			T1	8		T2	4		T4	61
valid_sources[0x59]	12110	1			T1	5		T3	8		T4	48
valid_sources[0x5a]	10786	1			T1	8		T2	2		T3	8
valid_sources[0x5b]	6850	1			T1	12		T2	7		T3	11
valid_sources[0x5c]	7018	1			T1	14		T3	5		T4	28
valid_sources[0x5d]	11385	1			T1	7		T2	13		T3	3
valid_sources[0x5e]	7698	1			T1	7		T2	8		T3	12
valid_sources[0x5f]	13246	1			T1	10		T2	1		T3	3
valid_sources[0x60]	6922	1			T1	4		T2	1		T3	9
valid_sources[0x61]	6939	1			T1	9		T2	5		T3	7
valid_sources[0x62]	7030	1			T1	3		T2	6		T3	9
valid_sources[0x63]	7261	1			T1	8		T2	6		T3	5
valid_sources[0x64]	12707	1			T1	6		T3	2		T4	34
valid_sources[0x65]	7339	1			T1	4		T2	5		T3	8
valid_sources[0x66]	11164	1			T1	13		T2	14		T3	10
valid_sources[0x67]	21162	1			T1	6		T2	1		T3	11
valid_sources[0x68]	8190	1			T1	13		T2	2		T3	6
valid_sources[0x69]	6980	1			T1	2		T2	3		T3	12
valid_sources[0x6a]	12738	1			T1	7		T2	4		T3	9
valid_sources[0x6b]	7937	1			T1	7		T2	2		T3	5
valid_sources[0x6c]	7392	1			T1	5		T2	1		T3	2
valid_sources[0x6d]	9741	1			T1	9		T2	3		T3	13
valid_sources[0x6e]	7292	1			T1	8		T3	8		T4	90
valid_sources[0x6f]	7299	1			T1	6		T2	4		T3	6
valid_sources[0x70]	15160	1			T1	10		T3	9		T4	28
valid_sources[0x71]	7804	1			T1	7		T3	3		T4	35
valid_sources[0x72]	11540	1			T1	7		T2	9		T3	15
valid_sources[0x73]	12626	1			T1	6		T2	4		T3	4
valid_sources[0x74]	7334	1			T1	12		T2	3		T3	9
valid_sources[0x75]	7296	1			T1	21		T2	3		T3	12
valid_sources[0x76]	7212	1			T1	12		T2	6		T3	6
valid_sources[0x77]	28429	1			T1	15		T3	9		T4	34
valid_sources[0x78]	7943	1			T1	6		T2	3		T3	18
valid_sources[0x79]	7083	1			T1	8		T2	7		T3	8
valid_sources[0x7a]	8005	1			T1	9		T2	965		T3	7
valid_sources[0x7b]	17704	1			T1	12		T2	2		T3	9
valid_sources[0x7c]	13040	1			T1	6		T3	4		T4	57
valid_sources[0x7d]	7087	1			T1	4		T2	2		T3	17
valid_sources[0x7e]	6668	1			T1	3		T2	7		T3	8
valid_sources[0x7f]	7112	1			T1	2		T3	3		T4	55
valid_sources[0x80]	12388	1			T1	10		T2	7		T3	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1071767

1

T1

834

T2

1266

T3

486

values[0x0]

all_enables

biggest_size

83405

1

T1

49

T2

113

T3

247

values[0x1]

all_enables

biggest_size

60341

1

T1

46

T2

66

T3

190