Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30285	1			T1	13		T2	24		T3	204
auto[PWRUP]	129	1			T36	2		T52	2		T50	1
auto[ONEST_0]	69	1			T3	1		T7	1		T36	1
auto[ONEST_021]	20	1			T50	1		T182	1		T183	1
auto[ONEST_1]	68	1			T3	4		T7	1		T35	1
auto[ONEST_DONE]	5	1			T184	1		T185	1		T186	1
auto[LP_0]	126	1			T36	2		T52	2		T50	1
auto[LP_021]	27	1			T36	1		T51	1		T187	1
auto[LP_1]	127	1			T36	2		T52	2		T50	3
auto[LP_EVAL]	65	1			T3	1		T7	1		T35	1
auto[LP_SLP]	516	1			T3	4		T7	1		T36	6
auto[LP_PWRUP]	22	1			T28	1		T51	1		T39	1
auto[NP_0]	182	1			T3	4		T7	3		T36	3
auto[NP_021]	39	1			T52	1		T153	1		T26	1
auto[NP_1]	162	1			T3	1		T36	3		T52	3
auto[NP_EVAL]	24	1			T3	1		T37	1		T51	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T51

1

T188

1

T189

1

min

29704

1

T1

13

T2

24

T3

194

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29709	1			T1	13		T2	24		T3	195
pow[0x1]	8	1			T35	1		T188	1		T190	1
pow[0x2]	18	1			T52	1		T188	1		T183	1
pow[0x3]	35	1			T28	1		T188	1		T191	1
pow[0x4]	65	1			T3	1		T52	1		T26	2
pow[0x5]	147	1			T3	1		T36	1		T52	3
pow[0x6]	255	1			T3	5		T7	3		T36	6
pow[0x7]	530	1			T3	3		T7	6		T36	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

228

1

T3

4

T7

3

T36

2

min

29258

1

T1

13

T2

24

T3

194

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29258	1			T1	13		T2	24		T3	194
pow[0x4]	1	1			T192	1		-	-		-	-
pow[0x5]	1	1			T28	1		-	-		-	-
pow[0x6]	1	1			T193	1		-	-		-	-
pow[0x7]	1	1			T194	1		-	-		-	-
pow[0x8]	9	1			T51	1		T195	1		T191	1
pow[0x9]	10	1			T50	1		T28	1		T51	1
pow[0xa]	22	1			T36	1		T153	2		T14	1
pow[0xb]	28	1			T50	1		T51	1		T182	2
pow[0xc]	68	1			T50	1		T26	1		T39	2
pow[0xd]	158	1			T3	2		T7	2		T36	2
pow[0xe]	299	1			T3	4		T7	3		T36	2
pow[0xf]	591	1			T3	3		T7	3		T36	8