Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	100.00	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	0	45	100.00

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2359	1			T3	18		T7	17		T8	15
auto[PWRUP]	122	1			T3	2		T7	1		T36	2
auto[ONEST_0]	75	1			T3	1		T7	1		T8	1
auto[ONEST_021]	21	1			T3	1		T52	1		T50	1
auto[ONEST_1]	95	1			T3	1		T7	3		T35	1
auto[ONEST_DONE]	3	1			T191	1		T185	1		T300	1
auto[LP_0]	141	1			T3	2		T35	1		T52	1
auto[LP_021]	29	1			T36	1		T50	1		T51	4
auto[LP_1]	149	1			T8	3		T36	4		T52	1
auto[LP_EVAL]	69	1			T8	1		T36	1		T35	1
auto[LP_SLP]	548	1			T3	6		T7	3		T8	1
auto[LP_PWRUP]	28	1			T50	1		T188	3		T182	1
auto[NP_0]	241	1			T3	5		T7	2		T8	4
auto[NP_021]	49	1			T3	1		T36	1		T153	1
auto[NP_1]	249	1			T3	3		T7	5		T8	2
auto[NP_EVAL]	37	1			T35	1		T52	1		T50	1
auto[NP_DONE]	1	1			T28	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T52

1

T50

1

T301

1

min

1973

1

T3

10

T7

8

T8

23

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1993	1			T3	10		T7	8		T8	23
pow[0x1]	10	1			T3	1		T50	1		T37	1
pow[0x2]	25	1			T7	1		T35	1		T183	1
pow[0x3]	38	1			T3	1		T50	1		T28	1
pow[0x4]	71	1			T3	1		T8	1		T52	1
pow[0x5]	148	1			T3	1		T7	3		T35	1
pow[0x6]	284	1			T3	4		T7	4		T36	2
pow[0x7]	552	1			T3	8		T7	4		T36	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

215

1

T3

2

T7

3

T36

1

min

1407

1

T3

8

T7

8

T8

21

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1414	1			T3	8		T7	8		T8	21
pow[0x1]	8	1			T13	1		T14	1		T41	1
pow[0x2]	16	1			T39	1		T14	1		T15	6
pow[0x3]	32	1			T37	3		T39	1		T149	4
pow[0x4]	63	1			T8	1		T35	2		T13	2
pow[0x5]	1	1			T274	1		-	-		-	-
pow[0x6]	1	1			T302	1		-	-		-	-
pow[0x7]	2	1			T187	1		T303	1		-	-
pow[0x8]	4	1			T52	1		T28	1		T187	1
pow[0x9]	11	1			T188	1		T185	1		T304	1
pow[0xa]	26	1			T39	1		T183	1		T33	1
pow[0xb]	29	1			T7	1		T36	1		T52	1
pow[0xc]	82	1			T3	3		T7	1		T36	3
pow[0xd]	174	1			T36	3		T52	4		T50	1
pow[0xe]	312	1			T3	4		T7	4		T36	3
pow[0xf]	600	1			T3	8		T7	5		T8	1