Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	3078	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2912	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	3076	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2906	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2837	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2781	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2863	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2936	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2856	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2783	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2883	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2766	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2915	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	3097	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2901	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2885	0	0
adc_en_ctl_rd_A	2147483647	2527	0	0
adc_fsm_rst_rd_A	2147483647	2505	0	0
adc_intr_ctl_rd_A	2147483647	3009	0	0
adc_lp_sample_ctl_rd_A	2147483647	2516	0	0
adc_pd_ctl_rd_A	2147483647	2772	0	0
adc_sample_ctl_rd_A	2147483647	2350	0	0
adc_wakeup_ctl_rd_A	2147483647	2436	0	0
intr_enable_rd_A	2147483647	2971	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3078	0	0
T13	418587	17	0	0
T14	0	12	0	0
T15	0	50	0	0
T16	0	19	0	0
T17	0	10	0	0
T18	0	7	0	0
T19	0	31	0	0
T20	0	44	0	0
T21	0	26	0	0
T22	0	16	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2912	0	0
T13	418587	19	0	0
T14	0	26	0	0
T15	0	40	0	0
T16	0	15	0	0
T17	0	21	0	0
T18	0	16	0	0
T19	0	32	0	0
T20	0	43	0	0
T21	0	41	0	0
T22	0	12	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3076	0	0
T13	418587	15	0	0
T14	0	18	0	0
T15	0	36	0	0
T16	0	9	0	0
T17	0	19	0	0
T18	0	26	0	0
T19	0	20	0	0
T20	0	27	0	0
T21	0	49	0	0
T22	0	9	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2906	0	0
T13	418587	11	0	0
T14	0	9	0	0
T15	0	50	0	0
T16	0	6	0	0
T17	0	12	0	0
T18	0	12	0	0
T19	0	32	0	0
T20	0	39	0	0
T21	0	54	0	0
T22	0	20	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2837	0	0
T13	418587	14	0	0
T14	0	16	0	0
T15	0	35	0	0
T16	0	19	0	0
T17	0	10	0	0
T18	0	27	0	0
T19	0	35	0	0
T20	0	41	0	0
T21	0	32	0	0
T22	0	10	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2781	0	0
T13	418587	12	0	0
T14	0	7	0	0
T15	0	30	0	0
T16	0	10	0	0
T17	0	10	0	0
T18	0	16	0	0
T19	0	15	0	0
T20	0	43	0	0
T21	0	27	0	0
T22	0	18	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2863	0	0
T13	418587	19	0	0
T14	0	20	0	0
T15	0	35	0	0
T16	0	11	0	0
T17	0	8	0	0
T18	0	33	0	0
T19	0	45	0	0
T20	0	20	0	0
T21	0	41	0	0
T22	0	24	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2936	0	0
T13	418587	12	0	0
T14	0	18	0	0
T15	0	54	0	0
T16	0	3	0	0
T17	0	14	0	0
T18	0	13	0	0
T19	0	21	0	0
T20	0	32	0	0
T21	0	38	0	0
T22	0	22	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2856	0	0
T13	418587	24	0	0
T14	0	18	0	0
T15	0	38	0	0
T16	0	5	0	0
T17	0	16	0	0
T18	0	13	0	0
T19	0	31	0	0
T20	0	28	0	0
T21	0	35	0	0
T22	0	22	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2783	0	0
T13	418587	19	0	0
T14	0	22	0	0
T15	0	36	0	0
T16	0	3	0	0
T17	0	22	0	0
T18	0	25	0	0
T19	0	30	0	0
T20	0	42	0	0
T21	0	43	0	0
T22	0	7	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2883	0	0
T13	418587	13	0	0
T14	0	8	0	0
T15	0	30	0	0
T16	0	5	0	0
T17	0	10	0	0
T18	0	23	0	0
T19	0	48	0	0
T20	0	44	0	0
T21	0	24	0	0
T22	0	8	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2766	0	0
T13	418587	20	0	0
T14	0	8	0	0
T15	0	27	0	0
T16	0	11	0	0
T17	0	8	0	0
T18	0	15	0	0
T19	0	29	0	0
T20	0	47	0	0
T21	0	40	0	0
T22	0	12	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2915	0	0
T13	418587	34	0	0
T14	0	20	0	0
T15	0	25	0	0
T16	0	4	0	0
T17	0	20	0	0
T18	0	14	0	0
T19	0	27	0	0
T20	0	43	0	0
T21	0	42	0	0
T22	0	26	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3097	0	0
T13	418587	18	0	0
T14	0	8	0	0
T15	0	39	0	0
T16	0	1	0	0
T17	0	7	0	0
T18	0	36	0	0
T19	0	34	0	0
T20	0	40	0	0
T21	0	48	0	0
T22	0	3	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2901	0	0
T13	418587	11	0	0
T14	0	19	0	0
T15	0	28	0	0
T16	0	8	0	0
T17	0	15	0	0
T18	0	18	0	0
T19	0	24	0	0
T20	0	35	0	0
T21	0	39	0	0
T22	0	8	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2885	0	0
T13	418587	21	0	0
T14	0	19	0	0
T15	0	29	0	0
T16	0	16	0	0
T17	0	18	0	0
T18	0	20	0	0
T19	0	27	0	0
T20	0	41	0	0
T21	0	31	0	0
T22	0	26	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2527	0	0
T13	418587	14	0	0
T14	0	18	0	0
T15	0	42	0	0
T16	0	8	0	0
T17	0	21	0	0
T18	0	30	0	0
T19	0	30	0	0
T20	0	22	0	0
T21	0	48	0	0
T22	0	13	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2505	0	0
T13	418587	21	0	0
T14	0	11	0	0
T15	0	47	0	0
T16	0	3	0	0
T17	0	12	0	0
T18	0	26	0	0
T19	0	28	0	0
T20	0	39	0	0
T21	0	42	0	0
T22	0	8	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3009	0	0
T13	418587	22	0	0
T14	0	12	0	0
T15	0	57	0	0
T16	0	11	0	0
T17	0	1	0	0
T18	0	24	0	0
T19	0	28	0	0
T20	0	51	0	0
T21	0	42	0	0
T22	0	11	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2516	0	0
T13	418587	24	0	0
T14	0	22	0	0
T15	0	45	0	0
T16	0	18	0	0
T17	0	14	0	0
T18	0	11	0	0
T19	0	49	0	0
T20	0	33	0	0
T21	0	29	0	0
T22	0	6	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2772	0	0
T13	418587	22	0	0
T14	0	20	0	0
T15	0	39	0	0
T16	0	11	0	0
T17	0	7	0	0
T18	0	12	0	0
T19	0	24	0	0
T20	0	41	0	0
T21	0	29	0	0
T22	0	13	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2350	0	0
T13	418587	21	0	0
T14	0	21	0	0
T15	0	20	0	0
T16	0	16	0	0
T17	0	18	0	0
T18	0	18	0	0
T19	0	43	0	0
T20	0	40	0	0
T21	0	36	0	0
T22	0	8	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2436	0	0
T13	418587	21	0	0
T14	0	10	0	0
T15	0	31	0	0
T16	0	16	0	0
T17	0	15	0	0
T18	0	27	0	0
T19	0	43	0	0
T20	0	36	0	0
T21	0	28	0	0
T22	0	13	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2971	0	0
T13	418587	18	0	0
T14	0	18	0	0
T15	0	83	0	0
T16	0	33	0	0
T17	0	6	0	0
T18	0	30	0	0
T19	0	77	0	0
T23	551170	0	0	0
T24	988074	0	0	0
T25	608124	0	0	0
T26	242017	0	0	0
T27	173991	0	0	0
T28	108161	0	0	0
T29	123644	0	0	0
T30	160581	0	0	0
T31	106642	0	0	0
T32	0	9	0	0
T33	0	15	0	0
T34	0	22	0	0