Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1187557	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1163461

1

T1

1422

T2

440

T3

2680

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2062308	1			T1	2530		T3	5035		T6	2543
values[0x0]	143804	1			T1	145		T2	519		T3	286
values[0x1]	144906	1			T1	165		T2	556		T3	254

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	951716	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1399302

1

T1

1706

T2

532

T3

3276

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8850	1			T1	6		T2	4		T3	13
valid_sources[0x01]	7263	1			T2	4		T3	11		T5	6
valid_sources[0x02]	13517	1			T1	2		T2	5		T3	2
valid_sources[0x03]	15134	1			T1	16		T2	1		T3	15
valid_sources[0x04]	8996	1			T1	12		T2	5		T3	25
valid_sources[0x05]	7880	1			T1	3		T2	1		T3	11
valid_sources[0x06]	8268	1			T1	16		T2	3		T3	3
valid_sources[0x07]	8096	1			T1	1		T2	1		T3	15
valid_sources[0x08]	7819	1			T1	6		T2	7		T3	13
valid_sources[0x09]	7605	1			T1	1		T2	3		T3	11
valid_sources[0x0a]	6873	1			T1	2		T2	11		T3	13
valid_sources[0x0b]	15504	1			T1	2		T2	1		T3	4
valid_sources[0x0c]	7325	1			T1	9		T2	5		T3	5
valid_sources[0x0d]	28185	1			T1	1		T2	2		T3	5
valid_sources[0x0e]	6810	1			T1	12		T2	2		T3	26
valid_sources[0x0f]	11313	1			T1	7		T2	6		T3	19
valid_sources[0x10]	7773	1			T1	8		T2	8		T3	7
valid_sources[0x11]	8391	1			T1	4		T3	10		T5	1
valid_sources[0x12]	6709	1			T1	2		T2	1		T3	25
valid_sources[0x13]	6880	1			T1	5		T2	7		T3	13
valid_sources[0x14]	6880	1			T1	5		T2	4		T3	19
valid_sources[0x15]	7082	1			T1	2		T2	2		T3	3
valid_sources[0x16]	6726	1			T1	5		T2	5		T3	21
valid_sources[0x17]	15671	1			T1	11		T2	1		T3	13
valid_sources[0x18]	8167	1			T1	14		T2	8		T3	20
valid_sources[0x19]	7769	1			T1	6		T2	3		T3	10
valid_sources[0x1a]	7592	1			T1	4		T2	4		T3	29
valid_sources[0x1b]	11088	1			T1	15		T2	4		T7	7
valid_sources[0x1c]	7470	1			T1	2		T2	7		T3	7
valid_sources[0x1d]	7699	1			T1	6		T2	7		T3	34
valid_sources[0x1e]	11635	1			T1	4		T2	2		T3	12
valid_sources[0x1f]	7303	1			T1	3		T2	3		T3	19
valid_sources[0x20]	6930	1			T1	6		T2	6		T3	15
valid_sources[0x21]	15696	1			T1	5		T2	4		T3	9
valid_sources[0x22]	8385	1			T1	14		T2	4		T3	2
valid_sources[0x23]	7680	1			T1	4		T2	5		T3	12
valid_sources[0x24]	9724	1			T1	3		T2	5		T3	14
valid_sources[0x25]	6581	1			T1	9		T2	5		T3	12
valid_sources[0x26]	7907	1			T1	8		T2	4		T3	9
valid_sources[0x27]	8295	1			T1	4		T2	3		T3	7
valid_sources[0x28]	6991	1			T1	5		T2	4		T3	18
valid_sources[0x29]	7292	1			T1	8		T2	10		T3	14
valid_sources[0x2a]	11487	1			T1	7		T2	6		T3	9
valid_sources[0x2b]	6872	1			T1	5		T2	7		T3	13
valid_sources[0x2c]	15655	1			T1	1		T2	3		T3	4
valid_sources[0x2d]	6920	1			T1	6		T2	6		T3	7
valid_sources[0x2e]	14930	1			T1	1		T2	4		T3	16
valid_sources[0x2f]	6903	1			T1	3		T2	4		T3	14
valid_sources[0x30]	7157	1			T1	3		T2	7		T3	12
valid_sources[0x31]	6793	1			T1	1		T2	1		T3	19
valid_sources[0x32]	8085	1			T1	15		T2	3		T3	17
valid_sources[0x33]	6752	1			T1	19		T2	8		T3	12
valid_sources[0x34]	6910	1			T1	5		T2	5		T3	8
valid_sources[0x35]	6876	1			T1	6		T2	5		T3	9
valid_sources[0x36]	6782	1			T1	8		T2	4		T3	12
valid_sources[0x37]	11284	1			T1	3		T2	3		T3	6
valid_sources[0x38]	8901	1			T1	3		T2	3		T3	14
valid_sources[0x39]	7079	1			T1	2		T2	3		T3	4
valid_sources[0x3a]	9855	1			T2	5		T3	6		T7	3
valid_sources[0x3b]	11817	1			T2	4		T3	13		T5	2
valid_sources[0x3c]	7819	1			T1	6		T2	4		T3	7
valid_sources[0x3d]	6990	1			T1	31		T2	5		T3	9
valid_sources[0x3e]	7131	1			T1	3		T2	7		T3	5
valid_sources[0x3f]	11228	1			T1	3		T2	6		T3	10
valid_sources[0x40]	10318	1			T1	10		T2	2		T3	3
valid_sources[0x41]	6789	1			T1	27		T2	1		T3	5
valid_sources[0x42]	8589	1			T1	4		T2	1		T3	6
valid_sources[0x43]	8116	1			T1	12		T2	5		T3	7
valid_sources[0x44]	11300	1			T1	1		T2	4		T3	13
valid_sources[0x45]	8779	1			T1	18		T2	5		T3	11
valid_sources[0x46]	15389	1			T1	6		T2	3		T3	8
valid_sources[0x47]	9721	1			T1	8		T2	9		T3	15
valid_sources[0x48]	9631	1			T2	4		T3	7		T5	1
valid_sources[0x49]	7153	1			T1	16		T2	3		T3	7
valid_sources[0x4a]	7118	1			T1	1		T2	5		T3	17
valid_sources[0x4b]	10201	1			T1	8		T2	3		T3	16
valid_sources[0x4c]	6962	1			T1	2		T2	7		T3	17
valid_sources[0x4d]	11689	1			T2	5		T3	8		T7	5
valid_sources[0x4e]	15955	1			T1	5		T2	6		T3	3
valid_sources[0x4f]	6685	1			T1	1		T2	3		T3	15
valid_sources[0x50]	13871	1			T1	4		T2	4		T3	16
valid_sources[0x51]	11126	1			T1	10		T2	2		T3	17
valid_sources[0x52]	13961	1			T1	3		T2	1		T3	3
valid_sources[0x53]	7003	1			T1	21		T2	5		T3	2
valid_sources[0x54]	8121	1			T1	24		T2	4		T3	6
valid_sources[0x55]	7168	1			T1	6		T2	6		T3	12
valid_sources[0x56]	8146	1			T1	4		T2	7		T3	7
valid_sources[0x57]	7090	1			T1	10		T2	5		T3	5
valid_sources[0x58]	7843	1			T1	5		T2	6		T3	10
valid_sources[0x59]	7594	1			T1	1		T2	2		T3	7
valid_sources[0x5a]	6759	1			T1	2		T2	3		T3	2
valid_sources[0x5b]	12245	1			T1	9		T2	1		T3	9
valid_sources[0x5c]	12715	1			T1	935		T2	3		T3	10
valid_sources[0x5d]	7292	1			T1	3		T2	2		T3	3
valid_sources[0x5e]	11267	1			T1	4		T2	9		T3	7
valid_sources[0x5f]	7176	1			T2	7		T3	15		T5	2
valid_sources[0x60]	7904	1			T1	17		T2	3		T3	1
valid_sources[0x61]	10892	1			T1	4		T2	4		T3	8
valid_sources[0x62]	6951	1			T1	11		T2	11		T3	12
valid_sources[0x63]	11191	1			T1	8		T2	3		T3	6
valid_sources[0x64]	6743	1			T1	6		T2	5		T3	9
valid_sources[0x65]	11191	1			T1	6		T2	7		T3	15
valid_sources[0x66]	19734	1			T1	3		T2	6		T3	9
valid_sources[0x67]	7228	1			T1	7		T2	5		T3	14
valid_sources[0x68]	19292	1			T1	1		T2	3		T3	17
valid_sources[0x69]	12699	1			T1	6		T2	2		T3	13
valid_sources[0x6a]	6910	1			T1	23		T2	8		T3	19
valid_sources[0x6b]	7252	1			T1	3		T2	2		T3	10
valid_sources[0x6c]	7452	1			T1	1		T2	4		T3	6
valid_sources[0x6d]	6903	1			T1	1		T2	1		T3	3
valid_sources[0x6e]	11200	1			T1	2		T2	2		T3	12
valid_sources[0x6f]	8669	1			T1	4		T2	7		T5	1
valid_sources[0x70]	7895	1			T1	13		T2	4		T3	6
valid_sources[0x71]	6752	1			T1	8		T2	1		T3	15
valid_sources[0x72]	9807	1			T1	5		T2	3		T3	18
valid_sources[0x73]	9962	1			T1	42		T2	6		T3	12
valid_sources[0x74]	7155	1			T1	3		T2	4		T3	15
valid_sources[0x75]	7289	1			T1	8		T2	5		T3	7
valid_sources[0x76]	15651	1			T1	5		T2	5		T3	9
valid_sources[0x77]	8541	1			T1	7		T2	6		T3	16
valid_sources[0x78]	6782	1			T1	3		T2	5		T3	5
valid_sources[0x79]	7756	1			T1	30		T2	3		T3	7
valid_sources[0x7a]	7730	1			T1	4		T2	3		T3	13
valid_sources[0x7b]	11154	1			T1	4		T2	3		T3	11
valid_sources[0x7c]	19805	1			T1	17		T2	8		T3	11
valid_sources[0x7d]	12566	1			T1	1		T2	1		T3	20
valid_sources[0x7e]	7346	1			T1	5		T2	3		T3	7
valid_sources[0x7f]	6887	1			T1	10		T2	5		T3	7
valid_sources[0x80]	7261	1			T1	11		T2	4		T3	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1027969

1

T1

1286

T3

2457

T6

1235

values[0x0]

all_enables

biggest_size

78466

1

T1

76

T2

261

T3

144

values[0x1]

all_enables

biggest_size

57026

1

T1

60

T2

179

T3

79