Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28996	1			T1	25		T2	287		T3	24
auto[PWRUP]	116	1			T2	2		T5	1		T7	2
auto[ONEST_0]	66	1			T2	3		T7	1		T47	1
auto[ONEST_021]	10	1			T2	1		T56	1		T206	1
auto[ONEST_1]	72	1			T2	1		T53	1		T45	2
auto[ONEST_DONE]	3	1			T207	1		T208	1		T209	1
auto[LP_0]	95	1			T2	2		T53	1		T45	2
auto[LP_021]	30	1			T47	2		T210	1		T183	1
auto[LP_1]	102	1			T2	2		T5	3		T7	1
auto[LP_EVAL]	72	1			T2	1		T7	4		T53	1
auto[LP_SLP]	422	1			T2	8		T5	4		T7	10
auto[LP_PWRUP]	29	1			T2	1		T7	2		T53	1
auto[NP_0]	168	1			T2	2		T5	3		T7	3
auto[NP_021]	26	1			T7	1		T211	2		T54	1
auto[NP_1]	160	1			T2	2		T5	1		T7	3
auto[NP_EVAL]	18	1			T45	1		T47	1		T212	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T47

1

T207

1

T206

1

min

28447

1

T1

25

T2

281

T3

24

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28460	1			T1	25		T2	281		T3	24
pow[0x1]	6	1			T206	1		T213	1		T214	1
pow[0x2]	16	1			T47	1		T211	1		T215	1
pow[0x3]	27	1			T47	1		T41	1		T216	1
pow[0x4]	64	1			T2	1		T7	1		T45	1
pow[0x5]	107	1			T2	3		T7	2		T53	2
pow[0x6]	253	1			T2	3		T5	3		T7	3
pow[0x7]	464	1			T2	6		T5	4		T7	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

204

1

T2

6

T5

2

T7

7

min

28076

1

T1

25

T2

273

T3

24

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28076	1			T1	25		T2	273		T3	24
pow[0x5]	3	1			T217	1		T203	1		T214	1
pow[0x6]	1	1			T47	1		-	-		-	-
pow[0x7]	2	1			T218	1		T219	1		-	-
pow[0x8]	5	1			T220	1		T206	1		T103	1
pow[0x9]	5	1			T221	1		T222	1		T223	1
pow[0xa]	12	1			T5	1		T212	1		T220	1
pow[0xb]	23	1			T2	1		T53	2		T47	2
pow[0xc]	67	1			T2	1		T5	1		T7	1
pow[0xd]	119	1			T5	2		T53	4		T47	4
pow[0xe]	268	1			T2	5		T5	2		T7	4
pow[0xf]	532	1			T2	11		T5	6		T7	10