Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2252	1			T2	17		T5	16		T7	17
auto[PWRUP]	122	1			T2	2		T5	1		T7	1
auto[ONEST_0]	64	1			T2	1		T5	1		T7	1
auto[ONEST_021]	18	1			T47	1		T51	1		T55	1
auto[ONEST_1]	81	1			T2	1		T53	3		T47	5
auto[ONEST_DONE]	5	1			T2	1		T5	1		T47	1
auto[LP_0]	108	1			T5	1		T7	1		T53	2
auto[LP_021]	33	1			T2	2		T7	2		T40	1
auto[LP_1]	151	1			T2	2		T53	4		T45	4
auto[LP_EVAL]	47	1			T5	1		T45	1		T47	3
auto[LP_SLP]	535	1			T2	13		T5	3		T7	7
auto[LP_PWRUP]	18	1			T2	1		T53	1		T47	1
auto[NP_0]	250	1			T2	4		T5	3		T53	1
auto[NP_021]	39	1			T53	1		T45	1		T47	2
auto[NP_1]	219	1			T2	1		T5	2		T7	3
auto[NP_EVAL]	29	1			T5	1		T53	2		T47	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T208

1

T213

1

T203

1

min

1959

1

T2

16

T5

3

T7

8

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1968	1			T2	16		T5	3		T7	8
pow[0x1]	16	1			T5	1		T47	1		T54	1
pow[0x2]	20	1			T40	1		T41	1		T216	1
pow[0x3]	35	1			T2	2		T5	1		T53	1
pow[0x4]	68	1			T2	2		T5	1		T7	1
pow[0x5]	117	1			T2	2		T5	1		T7	1
pow[0x6]	249	1			T2	2		T5	4		T7	3
pow[0x7]	532	1			T2	4		T5	7		T7	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

178

1

T2

2

T5

2

T7

1

min

1391

1

T2

2

T5

3

T7

3

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1393	1			T2	2		T5	3		T7	3
pow[0x1]	8	1			T40	1		T16	1		T194	1
pow[0x2]	33	1			T39	4		T40	2		T15	4
pow[0x3]	44	1			T38	2		T40	2		T15	2
pow[0x4]	56	1			T40	1		T16	2		T41	1
pow[0x5]	1	1			T347	1		-	-		-	-
pow[0x7]	2	1			T37	1		T214	1		-	-
pow[0x8]	8	1			T7	1		T212	1		T286	1
pow[0x9]	9	1			T54	1		T232	1		T348	1
pow[0xa]	21	1			T2	1		T5	1		T47	1
pow[0xb]	43	1			T5	1		T7	1		T53	1
pow[0xc]	84	1			T2	1		T5	2		T7	1
pow[0xd]	146	1			T2	3		T5	2		T53	1
pow[0xe]	248	1			T2	5		T5	4		T7	4
pow[0xf]	576	1			T2	11		T5	6		T7	7