Line Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Module :
prim_reg_cdc ( parameter DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal,BitMask,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal=4,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=16,ResetVal=155,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=28,ResetVal=0,BitMask=268374015,DstWrReq=1,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=0,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=1,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 15 | 13 | 86.67 |
Logical | 15 | 13 | 86.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T38,T39,T40 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 13 | 12 | 92.31 |
Logical | 13 | 12 | 92.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T3 |
1 | - | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_reg_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
180975154 |
0 |
0 |
T1 |
2487240 |
24151 |
0 |
0 |
T2 |
2283204 |
944372 |
0 |
0 |
T3 |
18651710 |
22201 |
0 |
0 |
T4 |
1837616 |
11050 |
0 |
0 |
T5 |
17310150 |
59978 |
0 |
0 |
T6 |
2515414 |
23365 |
0 |
0 |
T7 |
13493656 |
548531 |
0 |
0 |
T8 |
3176118 |
20605 |
0 |
0 |
T9 |
2928354 |
25272 |
0 |
0 |
T10 |
150368 |
31124 |
0 |
0 |
T11 |
0 |
26145 |
0 |
0 |
T12 |
0 |
19062 |
0 |
0 |
T13 |
0 |
32004 |
0 |
0 |
T14 |
140140 |
0 |
0 |
0 |
T15 |
0 |
634 |
0 |
0 |
T16 |
0 |
916 |
0 |
0 |
T32 |
0 |
818 |
0 |
0 |
T38 |
376832 |
64236 |
0 |
0 |
T39 |
766187 |
2109 |
0 |
0 |
T40 |
0 |
585 |
0 |
0 |
T41 |
0 |
1347 |
0 |
0 |
T42 |
0 |
428 |
0 |
0 |
T43 |
155771 |
0 |
0 |
0 |
T44 |
173751 |
0 |
0 |
0 |
T45 |
396824 |
0 |
0 |
0 |
T46 |
343468 |
0 |
0 |
0 |
T47 |
174574 |
0 |
0 |
0 |
T48 |
166137 |
0 |
0 |
0 |
T49 |
100455 |
0 |
0 |
0 |
T50 |
421080 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
889579938 |
880733802 |
0 |
0 |
T1 |
2566174 |
2564796 |
0 |
0 |
T2 |
601406 |
517998 |
0 |
0 |
T3 |
2640118 |
2638324 |
0 |
0 |
T4 |
27118 |
25480 |
0 |
0 |
T5 |
409110 |
347776 |
0 |
0 |
T6 |
2584972 |
2583048 |
0 |
0 |
T7 |
637858 |
574782 |
0 |
0 |
T8 |
3127982 |
3126188 |
0 |
0 |
T9 |
3511950 |
3509454 |
0 |
0 |
T14 |
2028 |
260 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
199131 |
0 |
0 |
T1 |
2487240 |
63 |
0 |
0 |
T2 |
2283204 |
580 |
0 |
0 |
T3 |
18651710 |
63 |
0 |
0 |
T4 |
1837616 |
41 |
0 |
0 |
T5 |
17310150 |
355 |
0 |
0 |
T6 |
2515414 |
63 |
0 |
0 |
T7 |
13493656 |
630 |
0 |
0 |
T8 |
3176118 |
63 |
0 |
0 |
T9 |
2928354 |
63 |
0 |
0 |
T10 |
150368 |
42 |
0 |
0 |
T11 |
0 |
36 |
0 |
0 |
T12 |
0 |
14 |
0 |
0 |
T13 |
0 |
42 |
0 |
0 |
T14 |
140140 |
0 |
0 |
0 |
T15 |
0 |
8 |
0 |
0 |
T16 |
0 |
1 |
0 |
0 |
T32 |
0 |
1 |
0 |
0 |
T38 |
376832 |
43 |
0 |
0 |
T39 |
766187 |
1 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
155771 |
0 |
0 |
0 |
T44 |
173751 |
0 |
0 |
0 |
T45 |
396824 |
0 |
0 |
0 |
T46 |
343468 |
0 |
0 |
0 |
T47 |
174574 |
0 |
0 |
0 |
T48 |
166137 |
0 |
0 |
0 |
T49 |
100455 |
0 |
0 |
0 |
T50 |
421080 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
3079440 |
3079414 |
0 |
0 |
T2 |
2826824 |
2825940 |
0 |
0 |
T3 |
22042930 |
22042696 |
0 |
0 |
T4 |
2171728 |
2170142 |
0 |
0 |
T5 |
20457450 |
20397572 |
0 |
0 |
T6 |
2972762 |
2972736 |
0 |
0 |
T7 |
15947048 |
15940652 |
0 |
0 |
T8 |
3753594 |
3753568 |
0 |
0 |
T9 |
3460782 |
3460756 |
0 |
0 |
T14 |
165620 |
163670 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 17 | 16 | 94.12 |
CONT_ASSIGN | 65 | 0 | 0 | |
ALWAYS | 71 | 5 | 4 | 80.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 7 | 7 | 100.00 |
CONT_ASSIGN | 150 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
|
unreachable |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
|
unreachable |
75 |
1 |
1 |
76 |
0 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
|
unreachable |
124 |
|
unreachable |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
|
unreachable |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc
| Total | Covered | Percent |
Conditions | 7 | 6 | 85.71 |
Logical | 7 | 6 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Excluded | |
VC_COV_UNR |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Excluded | |
VC_COV_UNR |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Not Covered | |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Excluded | |
VC_COV_UNR |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
5 |
83.33 |
IF |
71 |
3 |
2 |
66.67 |
IF |
115 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Unreachable |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Unreachable |
|
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 17 | 16 | 94.12 |
CONT_ASSIGN | 65 | 0 | 0 | |
ALWAYS | 71 | 5 | 4 | 80.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 7 | 7 | 100.00 |
CONT_ASSIGN | 150 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
|
unreachable |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
|
unreachable |
75 |
1 |
1 |
76 |
0 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
|
unreachable |
124 |
|
unreachable |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
|
unreachable |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc
| Total | Covered | Percent |
Conditions | 7 | 6 | 85.71 |
Logical | 7 | 6 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Excluded | |
VC_COV_UNR |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Excluded | |
VC_COV_UNR |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Not Covered | |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Excluded | |
VC_COV_UNR |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
5 |
83.33 |
IF |
71 |
3 |
2 |
66.67 |
IF |
115 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Unreachable |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Unreachable |
|
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
62183461 |
0 |
0 |
T1 |
118440 |
98424 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
64487 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
97547 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
84504 |
0 |
0 |
T9 |
133107 |
74819 |
0 |
0 |
T10 |
0 |
110170 |
0 |
0 |
T11 |
0 |
105195 |
0 |
0 |
T12 |
0 |
113901 |
0 |
0 |
T13 |
0 |
193468 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
14934 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
67319 |
0 |
0 |
T1 |
118440 |
232 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
151 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
248 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
211 |
0 |
0 |
T9 |
133107 |
183 |
0 |
0 |
T10 |
0 |
159 |
0 |
0 |
T11 |
0 |
145 |
0 |
0 |
T12 |
0 |
69 |
0 |
0 |
T13 |
0 |
225 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
9 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 21 | 21 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
|
unreachable |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T38,T39,T40 |
1 | 0 | Unreachable | |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T38,T39,T40 |
1 | 1 | Covered | T38,T39,T40 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T38,T39,T40 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T38,T39,T40 |
1 | 1 | Covered | T38,T39,T40 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T38,T39,T40 |
0 |
0 |
1 |
Covered |
T38,T39,T40 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T38,T39,T40 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
82738 |
0 |
0 |
T15 |
0 |
634 |
0 |
0 |
T16 |
0 |
916 |
0 |
0 |
T17 |
0 |
2109 |
0 |
0 |
T32 |
0 |
818 |
0 |
0 |
T38 |
376832 |
1992 |
0 |
0 |
T39 |
766187 |
2109 |
0 |
0 |
T40 |
0 |
585 |
0 |
0 |
T41 |
0 |
1347 |
0 |
0 |
T42 |
0 |
428 |
0 |
0 |
T43 |
155771 |
0 |
0 |
0 |
T44 |
173751 |
0 |
0 |
0 |
T45 |
396824 |
0 |
0 |
0 |
T46 |
343468 |
0 |
0 |
0 |
T47 |
174574 |
0 |
0 |
0 |
T48 |
166137 |
0 |
0 |
0 |
T49 |
100455 |
0 |
0 |
0 |
T50 |
421080 |
0 |
0 |
0 |
T51 |
0 |
1759 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
88 |
0 |
0 |
T15 |
0 |
8 |
0 |
0 |
T16 |
0 |
1 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T32 |
0 |
1 |
0 |
0 |
T38 |
376832 |
1 |
0 |
0 |
T39 |
766187 |
1 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
155771 |
0 |
0 |
0 |
T44 |
173751 |
0 |
0 |
0 |
T45 |
396824 |
0 |
0 |
0 |
T46 |
343468 |
0 |
0 |
0 |
T47 |
174574 |
0 |
0 |
0 |
T48 |
166137 |
0 |
0 |
0 |
T49 |
100455 |
0 |
0 |
0 |
T50 |
421080 |
0 |
0 |
0 |
T51 |
0 |
1 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
34001910 |
0 |
0 |
T1 |
118440 |
3470 |
0 |
0 |
T2 |
108724 |
539761 |
0 |
0 |
T3 |
847805 |
2387 |
0 |
0 |
T4 |
83528 |
11050 |
0 |
0 |
T5 |
786825 |
34617 |
0 |
0 |
T6 |
114337 |
3507 |
0 |
0 |
T7 |
613348 |
315963 |
0 |
0 |
T8 |
144369 |
3424 |
0 |
0 |
T9 |
133107 |
2413 |
0 |
0 |
T10 |
0 |
4555 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
37799 |
0 |
0 |
T1 |
118440 |
9 |
0 |
0 |
T2 |
108724 |
331 |
0 |
0 |
T3 |
847805 |
9 |
0 |
0 |
T4 |
83528 |
41 |
0 |
0 |
T5 |
786825 |
206 |
0 |
0 |
T6 |
114337 |
9 |
0 |
0 |
T7 |
613348 |
363 |
0 |
0 |
T8 |
144369 |
9 |
0 |
0 |
T9 |
133107 |
9 |
0 |
0 |
T10 |
0 |
6 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
15429721 |
0 |
0 |
T1 |
118440 |
2161 |
0 |
0 |
T2 |
108724 |
265879 |
0 |
0 |
T3 |
847805 |
1153 |
0 |
0 |
T4 |
83528 |
5138 |
0 |
0 |
T5 |
786825 |
14950 |
0 |
0 |
T6 |
114337 |
2250 |
0 |
0 |
T7 |
613348 |
149766 |
0 |
0 |
T8 |
144369 |
2189 |
0 |
0 |
T9 |
133107 |
1224 |
0 |
0 |
T10 |
0 |
2718 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
17426 |
0 |
0 |
T1 |
118440 |
6 |
0 |
0 |
T2 |
108724 |
165 |
0 |
0 |
T3 |
847805 |
6 |
0 |
0 |
T4 |
83528 |
20 |
0 |
0 |
T5 |
786825 |
103 |
0 |
0 |
T6 |
114337 |
6 |
0 |
0 |
T7 |
613348 |
181 |
0 |
0 |
T8 |
144369 |
6 |
0 |
0 |
T9 |
133107 |
6 |
0 |
0 |
T10 |
0 |
4 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
11779736 |
0 |
0 |
T1 |
118440 |
1093 |
0 |
0 |
T2 |
108724 |
267050 |
0 |
0 |
T3 |
847805 |
1025 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
15619 |
0 |
0 |
T6 |
114337 |
1119 |
0 |
0 |
T7 |
613348 |
151376 |
0 |
0 |
T8 |
144369 |
900 |
0 |
0 |
T9 |
133107 |
1214 |
0 |
0 |
T10 |
0 |
1334 |
0 |
0 |
T14 |
6370 |
268 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
13226 |
0 |
0 |
T1 |
118440 |
3 |
0 |
0 |
T2 |
108724 |
165 |
0 |
0 |
T3 |
847805 |
3 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
103 |
0 |
0 |
T6 |
114337 |
3 |
0 |
0 |
T7 |
613348 |
181 |
0 |
0 |
T8 |
144369 |
3 |
0 |
0 |
T9 |
133107 |
3 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T14 |
6370 |
1 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
11895666 |
0 |
0 |
T1 |
118440 |
1099 |
0 |
0 |
T2 |
108724 |
268158 |
0 |
0 |
T3 |
847805 |
1031 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
16353 |
0 |
0 |
T6 |
114337 |
1144 |
0 |
0 |
T7 |
613348 |
153047 |
0 |
0 |
T8 |
144369 |
917 |
0 |
0 |
T9 |
133107 |
1220 |
0 |
0 |
T10 |
0 |
1350 |
0 |
0 |
T14 |
6370 |
277 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
13258 |
0 |
0 |
T1 |
118440 |
3 |
0 |
0 |
T2 |
108724 |
165 |
0 |
0 |
T3 |
847805 |
3 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
103 |
0 |
0 |
T6 |
114337 |
3 |
0 |
0 |
T7 |
613348 |
181 |
0 |
0 |
T8 |
144369 |
3 |
0 |
0 |
T9 |
133107 |
3 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T14 |
6370 |
1 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1843556 |
0 |
0 |
T1 |
118440 |
1195 |
0 |
0 |
T2 |
108724 |
1871 |
0 |
0 |
T3 |
847805 |
1127 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
186 |
0 |
0 |
T6 |
114337 |
1235 |
0 |
0 |
T7 |
613348 |
989 |
0 |
0 |
T8 |
144369 |
1029 |
0 |
0 |
T9 |
133107 |
1316 |
0 |
0 |
T10 |
0 |
1582 |
0 |
0 |
T11 |
0 |
1467 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1993 |
0 |
0 |
T1 |
118440 |
3 |
0 |
0 |
T2 |
108724 |
1 |
0 |
0 |
T3 |
847805 |
3 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
1 |
0 |
0 |
T6 |
114337 |
3 |
0 |
0 |
T7 |
613348 |
1 |
0 |
0 |
T8 |
144369 |
3 |
0 |
0 |
T9 |
133107 |
3 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1732664 |
0 |
0 |
T1 |
118440 |
1189 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
1121 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
1210 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
997 |
0 |
0 |
T9 |
133107 |
1310 |
0 |
0 |
T10 |
0 |
1571 |
0 |
0 |
T11 |
0 |
1463 |
0 |
0 |
T12 |
0 |
1416 |
0 |
0 |
T13 |
0 |
2432 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
4488 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1868 |
0 |
0 |
T1 |
118440 |
3 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
3 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
3 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
3 |
0 |
0 |
T9 |
133107 |
3 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
3 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1714246 |
0 |
0 |
T1 |
118440 |
1183 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
1115 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
1189 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
963 |
0 |
0 |
T9 |
133107 |
1304 |
0 |
0 |
T10 |
0 |
1557 |
0 |
0 |
T11 |
0 |
1459 |
0 |
0 |
T12 |
0 |
1409 |
0 |
0 |
T13 |
0 |
2416 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
4482 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1887 |
0 |
0 |
T1 |
118440 |
3 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
3 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
3 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
3 |
0 |
0 |
T9 |
133107 |
3 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
3 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1720355 |
0 |
0 |
T1 |
118440 |
1177 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
1109 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
1173 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
930 |
0 |
0 |
T9 |
133107 |
1298 |
0 |
0 |
T10 |
0 |
1545 |
0 |
0 |
T11 |
0 |
1455 |
0 |
0 |
T12 |
0 |
1401 |
0 |
0 |
T13 |
0 |
2394 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
4476 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1876 |
0 |
0 |
T1 |
118440 |
3 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
3 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
3 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
3 |
0 |
0 |
T9 |
133107 |
3 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
3 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1747455 |
0 |
0 |
T1 |
118440 |
1171 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
1103 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
1148 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
907 |
0 |
0 |
T9 |
133107 |
1292 |
0 |
0 |
T10 |
0 |
1524 |
0 |
0 |
T11 |
0 |
1451 |
0 |
0 |
T12 |
0 |
1392 |
0 |
0 |
T13 |
0 |
2367 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
4470 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1913 |
0 |
0 |
T1 |
118440 |
3 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
3 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
3 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
3 |
0 |
0 |
T9 |
133107 |
3 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
3 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1690997 |
0 |
0 |
T1 |
118440 |
1165 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
1097 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
1119 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
875 |
0 |
0 |
T9 |
133107 |
1286 |
0 |
0 |
T10 |
0 |
1510 |
0 |
0 |
T11 |
0 |
1447 |
0 |
0 |
T12 |
0 |
1387 |
0 |
0 |
T13 |
0 |
2340 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
4464 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1875 |
0 |
0 |
T1 |
118440 |
3 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
3 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
3 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
3 |
0 |
0 |
T9 |
133107 |
3 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
3 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1670548 |
0 |
0 |
T1 |
118440 |
1159 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
1091 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
1097 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
850 |
0 |
0 |
T9 |
133107 |
1280 |
0 |
0 |
T10 |
0 |
1492 |
0 |
0 |
T11 |
0 |
1443 |
0 |
0 |
T12 |
0 |
1378 |
0 |
0 |
T13 |
0 |
2320 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
4458 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1822 |
0 |
0 |
T1 |
118440 |
3 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
3 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
3 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
3 |
0 |
0 |
T9 |
133107 |
3 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
3 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1735178 |
0 |
0 |
T1 |
118440 |
1153 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
1085 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
1083 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
811 |
0 |
0 |
T9 |
133107 |
1274 |
0 |
0 |
T10 |
0 |
1474 |
0 |
0 |
T11 |
0 |
1439 |
0 |
0 |
T12 |
0 |
1366 |
0 |
0 |
T13 |
0 |
2299 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
4452 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1890 |
0 |
0 |
T1 |
118440 |
3 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
3 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
3 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
3 |
0 |
0 |
T9 |
133107 |
3 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
3 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1806796 |
0 |
0 |
T1 |
118440 |
1147 |
0 |
0 |
T2 |
108724 |
1864 |
0 |
0 |
T3 |
847805 |
1079 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
181 |
0 |
0 |
T6 |
114337 |
1066 |
0 |
0 |
T7 |
613348 |
981 |
0 |
0 |
T8 |
144369 |
782 |
0 |
0 |
T9 |
133107 |
1268 |
0 |
0 |
T10 |
0 |
1462 |
0 |
0 |
T11 |
0 |
1435 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1997 |
0 |
0 |
T1 |
118440 |
3 |
0 |
0 |
T2 |
108724 |
1 |
0 |
0 |
T3 |
847805 |
3 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
1 |
0 |
0 |
T6 |
114337 |
3 |
0 |
0 |
T7 |
613348 |
1 |
0 |
0 |
T8 |
144369 |
3 |
0 |
0 |
T9 |
133107 |
3 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1664578 |
0 |
0 |
T1 |
118440 |
1141 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
1073 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
1048 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
749 |
0 |
0 |
T9 |
133107 |
1262 |
0 |
0 |
T10 |
0 |
1453 |
0 |
0 |
T11 |
0 |
1431 |
0 |
0 |
T12 |
0 |
1357 |
0 |
0 |
T13 |
0 |
2258 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
4440 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1859 |
0 |
0 |
T1 |
118440 |
3 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
3 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
3 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
3 |
0 |
0 |
T9 |
133107 |
3 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
3 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1692668 |
0 |
0 |
T1 |
118440 |
1135 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
1067 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
1031 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
959 |
0 |
0 |
T9 |
133107 |
1256 |
0 |
0 |
T10 |
0 |
1437 |
0 |
0 |
T11 |
0 |
1427 |
0 |
0 |
T12 |
0 |
1347 |
0 |
0 |
T13 |
0 |
2240 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
4434 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1875 |
0 |
0 |
T1 |
118440 |
3 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
3 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
3 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
3 |
0 |
0 |
T9 |
133107 |
3 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
3 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1683024 |
0 |
0 |
T1 |
118440 |
1129 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
1061 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
1010 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
1044 |
0 |
0 |
T9 |
133107 |
1250 |
0 |
0 |
T10 |
0 |
1422 |
0 |
0 |
T11 |
0 |
1423 |
0 |
0 |
T12 |
0 |
1337 |
0 |
0 |
T13 |
0 |
2224 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
4428 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1865 |
0 |
0 |
T1 |
118440 |
3 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
3 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
3 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
3 |
0 |
0 |
T9 |
133107 |
3 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
3 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1666452 |
0 |
0 |
T1 |
118440 |
1123 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
1055 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
985 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
1027 |
0 |
0 |
T9 |
133107 |
1244 |
0 |
0 |
T10 |
0 |
1409 |
0 |
0 |
T11 |
0 |
1419 |
0 |
0 |
T12 |
0 |
1330 |
0 |
0 |
T13 |
0 |
2205 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
4422 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1861 |
0 |
0 |
T1 |
118440 |
3 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
3 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
3 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
3 |
0 |
0 |
T9 |
133107 |
3 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
3 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1672031 |
0 |
0 |
T1 |
118440 |
1117 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
1049 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
960 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
982 |
0 |
0 |
T9 |
133107 |
1238 |
0 |
0 |
T10 |
0 |
1393 |
0 |
0 |
T11 |
0 |
1415 |
0 |
0 |
T12 |
0 |
1322 |
0 |
0 |
T13 |
0 |
2187 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
4416 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1860 |
0 |
0 |
T1 |
118440 |
3 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
3 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
3 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
3 |
0 |
0 |
T9 |
133107 |
3 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
3 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1660364 |
0 |
0 |
T1 |
118440 |
1111 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
1043 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
1060 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
962 |
0 |
0 |
T9 |
133107 |
1232 |
0 |
0 |
T10 |
0 |
1381 |
0 |
0 |
T11 |
0 |
1411 |
0 |
0 |
T12 |
0 |
1314 |
0 |
0 |
T13 |
0 |
2170 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
4410 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1860 |
0 |
0 |
T1 |
118440 |
3 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
3 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
3 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
3 |
0 |
0 |
T9 |
133107 |
3 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
3 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1688349 |
0 |
0 |
T1 |
118440 |
1105 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
1037 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
1048 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
945 |
0 |
0 |
T9 |
133107 |
1226 |
0 |
0 |
T10 |
0 |
1367 |
0 |
0 |
T11 |
0 |
1407 |
0 |
0 |
T12 |
0 |
1306 |
0 |
0 |
T13 |
0 |
2152 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
4404 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1881 |
0 |
0 |
T1 |
118440 |
3 |
0 |
0 |
T2 |
108724 |
0 |
0 |
0 |
T3 |
847805 |
3 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
3 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
3 |
0 |
0 |
T9 |
133107 |
3 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
3 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T8,T9 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T8,T9 |
1 | 1 | Covered | T3,T8,T9 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T8,T9 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T3,T8,T9 |
1 | 1 | Covered | T3,T8,T9 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T3,T8,T9 |
0 |
0 |
1 |
Covered |
T3,T8,T9 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T3,T8,T9 |
0 |
0 |
1 |
Covered |
T3,T8,T9 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1214359 |
0 |
0 |
T3 |
847805 |
1013 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
0 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
841 |
0 |
0 |
T9 |
133107 |
1202 |
0 |
0 |
T10 |
150368 |
1310 |
0 |
0 |
T12 |
0 |
1277 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
1460 |
0 |
0 |
T39 |
0 |
6166 |
0 |
0 |
T44 |
0 |
1246 |
0 |
0 |
T46 |
0 |
2628 |
0 |
0 |
T48 |
0 |
1330 |
0 |
0 |
T52 |
107450 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1309 |
0 |
0 |
T3 |
847805 |
3 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
0 |
0 |
0 |
T6 |
114337 |
0 |
0 |
0 |
T7 |
613348 |
0 |
0 |
0 |
T8 |
144369 |
3 |
0 |
0 |
T9 |
133107 |
3 |
0 |
0 |
T10 |
150368 |
2 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
4 |
0 |
0 |
T44 |
0 |
1 |
0 |
0 |
T46 |
0 |
2 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
T52 |
107450 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc
| Total | Covered | Percent |
Conditions | 13 | 12 | 92.31 |
Logical | 13 | 12 | 92.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T3 |
1 | - | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
16998302 |
0 |
0 |
T1 |
118440 |
2281 |
0 |
0 |
T2 |
108724 |
400876 |
0 |
0 |
T3 |
847805 |
2502 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
24994 |
0 |
0 |
T6 |
114337 |
2396 |
0 |
0 |
T7 |
613348 |
230598 |
0 |
0 |
T8 |
144369 |
2369 |
0 |
0 |
T9 |
133107 |
2523 |
0 |
0 |
T10 |
0 |
2990 |
0 |
0 |
T11 |
0 |
3153 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34214613 |
33874377 |
0 |
0 |
T1 |
98699 |
98646 |
0 |
0 |
T2 |
23131 |
19923 |
0 |
0 |
T3 |
101543 |
101474 |
0 |
0 |
T4 |
1043 |
980 |
0 |
0 |
T5 |
15735 |
13376 |
0 |
0 |
T6 |
99422 |
99348 |
0 |
0 |
T7 |
24533 |
22107 |
0 |
0 |
T8 |
120307 |
120238 |
0 |
0 |
T9 |
135075 |
134979 |
0 |
0 |
T14 |
78 |
10 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
18524 |
0 |
0 |
T1 |
118440 |
6 |
0 |
0 |
T2 |
108724 |
247 |
0 |
0 |
T3 |
847805 |
6 |
0 |
0 |
T4 |
83528 |
0 |
0 |
0 |
T5 |
786825 |
147 |
0 |
0 |
T6 |
114337 |
6 |
0 |
0 |
T7 |
613348 |
265 |
0 |
0 |
T8 |
144369 |
6 |
0 |
0 |
T9 |
133107 |
6 |
0 |
0 |
T10 |
0 |
4 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T14 |
6370 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
118440 |
118439 |
0 |
0 |
T2 |
108724 |
108690 |
0 |
0 |
T3 |
847805 |
847796 |
0 |
0 |
T4 |
83528 |
83467 |
0 |
0 |
T5 |
786825 |
784522 |
0 |
0 |
T6 |
114337 |
114336 |
0 |
0 |
T7 |
613348 |
613102 |
0 |
0 |
T8 |
144369 |
144368 |
0 |
0 |
T9 |
133107 |
133106 |
0 |
0 |
T14 |
6370 |
6295 |
0 |
0 |