Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1259783	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1231752

1

T1

2180

T2

2088

T3

4274

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2182898	1			T1	4114		T2	3973		T3	8120
values[0x0]	153762	1			T1	126		T2	102		T3	258
values[0x1]	154875	1			T1	110		T2	127		T3	260

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1009560	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1481975

1

T1

2607

T2

2477

T3

5143

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6945	1			T2	18		T4	15		T7	13
valid_sources[0x01]	9757	1			T2	16		T7	17		T8	25
valid_sources[0x02]	9100	1			T2	14		T7	3		T8	18
valid_sources[0x03]	7679	1			T2	20		T7	9		T8	43
valid_sources[0x04]	6869	1			T2	17		T5	1		T7	16
valid_sources[0x05]	12568	1			T2	12		T7	12		T8	33
valid_sources[0x06]	6487	1			T2	13		T5	1		T7	13
valid_sources[0x07]	8394	1			T2	21		T7	2		T8	12
valid_sources[0x08]	8064	1			T2	17		T5	1		T7	3
valid_sources[0x09]	9760	1			T2	20		T7	6		T8	9
valid_sources[0x0a]	6840	1			T2	8		T5	1		T7	12
valid_sources[0x0b]	7537	1			T2	12		T7	11		T8	30
valid_sources[0x0c]	11100	1			T2	15		T7	10		T8	31
valid_sources[0x0d]	15535	1			T2	8		T7	6		T8	28
valid_sources[0x0e]	15783	1			T2	25		T7	8		T8	34
valid_sources[0x0f]	7213	1			T2	15		T7	12		T8	17
valid_sources[0x10]	6587	1			T2	11		T7	14		T8	32
valid_sources[0x11]	8051	1			T2	23		T7	13		T8	14
valid_sources[0x12]	7471	1			T2	15		T6	1		T7	10
valid_sources[0x13]	7911	1			T2	12		T7	11		T8	32
valid_sources[0x14]	8125	1			T2	17		T6	1		T7	13
valid_sources[0x15]	9791	1			T2	28		T7	7		T8	45
valid_sources[0x16]	11465	1			T2	14		T5	4		T7	8
valid_sources[0x17]	7990	1			T2	11		T7	7		T8	27
valid_sources[0x18]	10317	1			T2	24		T5	1		T7	7
valid_sources[0x19]	11325	1			T2	19		T7	11		T8	51
valid_sources[0x1a]	8269	1			T2	9		T7	13		T8	29
valid_sources[0x1b]	9835	1			T2	9		T7	12		T8	32
valid_sources[0x1c]	17084	1			T2	15		T7	8		T8	22
valid_sources[0x1d]	11193	1			T2	8		T7	16		T8	24
valid_sources[0x1e]	6647	1			T2	19		T7	10		T8	15
valid_sources[0x1f]	6967	1			T2	21		T7	15		T8	10
valid_sources[0x20]	7203	1			T2	6		T4	18		T7	10
valid_sources[0x21]	6992	1			T2	17		T7	10		T8	18
valid_sources[0x22]	11456	1			T2	19		T7	10		T8	21
valid_sources[0x23]	9840	1			T2	13		T7	19		T8	32
valid_sources[0x24]	7409	1			T2	20		T5	1		T7	13
valid_sources[0x25]	15445	1			T1	4349		T2	13		T7	12
valid_sources[0x26]	10444	1			T2	17		T7	13		T8	39
valid_sources[0x27]	13225	1			T2	13		T7	13		T8	26
valid_sources[0x28]	7437	1			T2	14		T7	12		T8	36
valid_sources[0x29]	29071	1			T2	14		T7	13		T8	36
valid_sources[0x2a]	7011	1			T2	24		T4	15		T7	11
valid_sources[0x2b]	7224	1			T2	18		T5	1		T7	9
valid_sources[0x2c]	7257	1			T2	25		T7	21		T8	40
valid_sources[0x2d]	8194	1			T2	18		T7	13		T8	32
valid_sources[0x2e]	13758	1			T2	7		T7	13		T8	40
valid_sources[0x2f]	6721	1			T2	14		T5	1		T7	12
valid_sources[0x30]	10591	1			T2	11		T4	15		T7	11
valid_sources[0x31]	6680	1			T2	31		T7	7		T8	35
valid_sources[0x32]	6853	1			T2	14		T7	11		T8	17
valid_sources[0x33]	11215	1			T2	19		T7	8		T8	21
valid_sources[0x34]	6741	1			T2	13		T5	1		T7	10
valid_sources[0x35]	7217	1			T2	14		T5	3		T7	11
valid_sources[0x36]	11239	1			T2	21		T6	3		T7	12
valid_sources[0x37]	9849	1			T2	12		T7	12		T8	12
valid_sources[0x38]	17383	1			T2	21		T7	8		T8	15
valid_sources[0x39]	7653	1			T2	14		T6	2		T7	9
valid_sources[0x3a]	11657	1			T2	20		T7	15		T8	29
valid_sources[0x3b]	11521	1			T2	18		T7	6		T8	18
valid_sources[0x3c]	7273	1			T2	18		T5	1		T7	10
valid_sources[0x3d]	21528	1			T2	9		T5	1		T7	11
valid_sources[0x3e]	8461	1			T2	13		T6	1		T7	13
valid_sources[0x3f]	7314	1			T2	18		T7	13		T8	13
valid_sources[0x40]	6825	1			T2	24		T7	16		T8	10
valid_sources[0x41]	7345	1			T2	26		T7	23		T8	13
valid_sources[0x42]	7489	1			T2	11		T5	1		T7	8
valid_sources[0x43]	7062	1			T2	12		T7	8		T8	21
valid_sources[0x44]	7234	1			T2	22		T7	11		T8	18
valid_sources[0x45]	7230	1			T2	20		T7	7		T8	5
valid_sources[0x46]	7004	1			T2	17		T7	13		T8	26
valid_sources[0x47]	11470	1			T2	25		T7	13		T8	33
valid_sources[0x48]	7707	1			T2	8		T7	8		T8	13
valid_sources[0x49]	7586	1			T2	13		T7	15		T8	28
valid_sources[0x4a]	11969	1			T2	22		T7	15		T8	31
valid_sources[0x4b]	11692	1			T2	25		T7	6		T8	26
valid_sources[0x4c]	8830	1			T2	14		T7	7		T8	25
valid_sources[0x4d]	24101	1			T2	14		T7	7		T8	21
valid_sources[0x4e]	7585	1			T2	22		T7	8		T8	19
valid_sources[0x4f]	10577	1			T2	22		T7	11		T8	11
valid_sources[0x50]	9540	1			T2	20		T7	5		T8	22
valid_sources[0x51]	11146	1			T2	11		T7	7		T8	21
valid_sources[0x52]	7777	1			T2	12		T7	13		T8	23
valid_sources[0x53]	7274	1			T2	19		T5	2		T7	16
valid_sources[0x54]	8562	1			T2	16		T6	4		T7	6
valid_sources[0x55]	7199	1			T2	16		T7	15		T8	11
valid_sources[0x56]	12210	1			T2	11		T7	12		T8	31
valid_sources[0x57]	33329	1			T2	27		T7	16		T8	24
valid_sources[0x58]	10626	1			T2	14		T7	6		T8	37
valid_sources[0x59]	6707	1			T2	15		T7	14		T8	20
valid_sources[0x5a]	11800	1			T2	20		T7	6		T8	20
valid_sources[0x5b]	7621	1			T2	23		T7	17		T8	26
valid_sources[0x5c]	7414	1			T2	13		T7	11		T8	18
valid_sources[0x5d]	6956	1			T2	16		T7	13		T8	18
valid_sources[0x5e]	7056	1			T2	23		T7	11		T8	19
valid_sources[0x5f]	6673	1			T2	16		T7	13		T8	23
valid_sources[0x60]	10055	1			T2	18		T7	13		T8	12
valid_sources[0x61]	9669	1			T2	14		T7	8		T8	15
valid_sources[0x62]	7004	1			T2	10		T7	10		T8	36
valid_sources[0x63]	9396	1			T2	19		T7	14		T8	25
valid_sources[0x64]	9081	1			T2	13		T7	11		T8	53
valid_sources[0x65]	8013	1			T2	14		T7	7		T8	35
valid_sources[0x66]	10383	1			T2	16		T7	15		T8	20
valid_sources[0x67]	11367	1			T2	21		T7	14		T8	17
valid_sources[0x68]	17768	1			T2	16		T7	6		T8	26
valid_sources[0x69]	15418	1			T2	16		T7	15		T8	22
valid_sources[0x6a]	6801	1			T2	13		T7	14		T8	12
valid_sources[0x6b]	10753	1			T2	13		T7	13		T8	15
valid_sources[0x6c]	6766	1			T2	10		T7	12		T8	12
valid_sources[0x6d]	7020	1			T2	21		T7	8		T8	18
valid_sources[0x6e]	7019	1			T2	10		T7	13		T8	1
valid_sources[0x6f]	7044	1			T2	17		T7	10		T8	20
valid_sources[0x70]	7200	1			T2	14		T7	9		T8	18
valid_sources[0x71]	9285	1			T2	19		T7	11		T8	9
valid_sources[0x72]	7213	1			T2	13		T7	10		T8	21
valid_sources[0x73]	7277	1			T2	15		T7	12		T8	26
valid_sources[0x74]	7326	1			T2	15		T7	7		T8	30
valid_sources[0x75]	9984	1			T2	8		T7	8		T8	17
valid_sources[0x76]	12216	1			T2	9		T7	12		T8	15
valid_sources[0x77]	8119	1			T2	24		T7	18		T8	27
valid_sources[0x78]	8073	1			T2	9		T7	10		T8	11
valid_sources[0x79]	9958	1			T2	22		T7	11		T8	5
valid_sources[0x7a]	11058	1			T1	1		T2	13		T7	13
valid_sources[0x7b]	7034	1			T2	18		T5	1		T6	3
valid_sources[0x7c]	7359	1			T2	18		T7	12		T8	37
valid_sources[0x7d]	8028	1			T2	12		T7	12		T8	14
valid_sources[0x7e]	7175	1			T2	18		T7	12		T8	44
valid_sources[0x7f]	6928	1			T2	10		T7	6		T8	21
valid_sources[0x80]	6752	1			T2	20		T7	18		T8	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1087003

1

T1

2085

T2

1999

T3

4080

values[0x0]

all_enables

biggest_size

83835

1

T1

63

T2

57

T3

119

values[0x1]

all_enables

biggest_size

60914

1

T1

32

T2

32

T3

75