Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30176	1			T1	5		T2	8		T3	15
auto[PWRUP]	133	1			T40	1		T41	1		T14	2
auto[ONEST_0]	75	1			T40	3		T44	1		T14	1
auto[ONEST_021]	17	1			T41	1		T42	1		T307	1
auto[ONEST_1]	82	1			T40	2		T41	2		T14	1
auto[ONEST_DONE]	6	1			T41	1		T14	1		T308	1
auto[LP_0]	133	1			T40	2		T44	1		T41	1
auto[LP_021]	33	1			T14	1		T42	1		T309	1
auto[LP_1]	134	1			T44	4		T41	2		T14	1
auto[LP_EVAL]	73	1			T40	2		T41	1		T14	1
auto[LP_SLP]	509	1			T40	7		T44	6		T41	8
auto[LP_PWRUP]	20	1			T44	2		T42	1		T33	1
auto[NP_0]	145	1			T44	6		T41	4		T45	2
auto[NP_021]	41	1			T44	3		T14	1		T45	1
auto[NP_1]	164	1			T40	3		T44	2		T41	4
auto[NP_EVAL]	33	1			T40	1		T45	1		T27	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T310

1

T96

1

T311

1

min

29564

1

T1

5

T2

8

T3

15

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29569	1			T1	5		T2	8		T3	15
pow[0x1]	5	1			T312	1		T313	1		T314	1
pow[0x2]	22	1			T40	1		T41	3		T14	1
pow[0x3]	37	1			T14	1		T45	2		T33	1
pow[0x4]	77	1			T40	3		T41	2		T45	1
pow[0x5]	144	1			T40	3		T44	2		T14	2
pow[0x6]	298	1			T40	1		T44	1		T41	3
pow[0x7]	565	1			T40	7		T44	7		T41	13

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

175

1

T40

1

T44

2

T41

4

min

29066

1

T1

5

T2

8

T3

15

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x2]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29066	1			T1	5		T2	8		T3	15
pow[0x1]	1	1			T251	1		-	-		-	-
pow[0x3]	1	1			T315	1		-	-		-	-
pow[0x5]	1	1			T316	1		-	-		-	-
pow[0x6]	1	1			T317	1		-	-		-	-
pow[0x7]	7	1			T31	1		T46	1		T96	1
pow[0x8]	5	1			T42	1		T311	1		T318	1
pow[0x9]	7	1			T85	1		T319	1		T22	1
pow[0xa]	14	1			T307	1		T27	1		T320	2
pow[0xb]	33	1			T27	1		T309	1		T308	2
pow[0xc]	75	1			T40	2		T41	1		T45	1
pow[0xd]	168	1			T40	6		T44	3		T41	2
pow[0xe]	289	1			T40	1		T44	2		T41	3
pow[0xf]	654	1			T40	5		T44	12		T41	11