Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2403	1			T4	6		T8	13		T43	3
auto[PWRUP]	138	1			T8	1		T40	1		T44	3
auto[ONEST_0]	70	1			T40	1		T44	1		T41	1
auto[ONEST_021]	15	1			T14	1		T31	1		T42	1
auto[ONEST_1]	93	1			T44	2		T45	4		T31	1
auto[ONEST_DONE]	4	1			T41	1		T272	1		T311	1
auto[LP_0]	129	1			T40	1		T44	1		T41	4
auto[LP_021]	27	1			T40	1		T46	1		T242	1
auto[LP_1]	145	1			T4	1		T40	2		T30	1
auto[LP_EVAL]	60	1			T40	1		T44	1		T41	1
auto[LP_SLP]	537	1			T8	1		T40	5		T29	2
auto[LP_PWRUP]	35	1			T14	1		T45	1		T307	2
auto[NP_0]	241	1			T4	1		T8	5		T40	3
auto[NP_021]	49	1			T8	1		T40	2		T44	1
auto[NP_1]	266	1			T4	2		T8	1		T40	2
auto[NP_EVAL]	30	1			T45	2		T32	1		T321	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

5

1

T128

1

T308

1

T82

1

min

1990

1

T4

9

T8

22

T43

3

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2003	1			T4	9		T8	22		T43	3
pow[0x1]	13	1			T42	1		T307	1		T15	1
pow[0x2]	23	1			T4	1		T40	1		T32	1
pow[0x3]	31	1			T40	1		T44	1		T321	1
pow[0x4]	77	1			T40	1		T44	1		T41	4
pow[0x5]	157	1			T40	4		T41	2		T14	1
pow[0x6]	267	1			T40	3		T44	4		T41	3
pow[0x7]	573	1			T40	6		T44	10		T41	9

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

214

1

T40

2

T44

4

T41

4

min

1369

1

T4

8

T8

16

T43

3

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1371	1			T4	8		T8	16		T43	3
pow[0x1]	10	1			T33	1		T35	2		T15	1
pow[0x2]	30	1			T8	6		T34	1		T36	2
pow[0x3]	40	1			T4	1		T29	5		T32	1
pow[0x4]	81	1			T4	1		T29	1		T30	1
pow[0x6]	1	1			T322	1		-	-		-	-
pow[0x7]	2	1			T40	1		T323	1		-	-
pow[0x8]	5	1			T312	1		T324	1		T325	1
pow[0x9]	8	1			T42	1		T320	1		T93	1
pow[0xa]	22	1			T44	1		T14	1		T45	1
pow[0xb]	42	1			T40	1		T44	1		T42	1
pow[0xc]	92	1			T40	2		T44	2		T41	3
pow[0xd]	161	1			T40	4		T44	1		T41	3
pow[0xe]	308	1			T40	5		T44	5		T41	3
pow[0xf]	622	1			T40	7		T44	10		T41	10