Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2315	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2273	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2097	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2142	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2042	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2082	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2098	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1917	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1984	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2227	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2124	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2010	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2174	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2021	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2218	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2221	0	0
adc_en_ctl_rd_A	2147483647	1712	0	0
adc_fsm_rst_rd_A	2147483647	1741	0	0
adc_intr_ctl_rd_A	2147483647	2179	0	0
adc_lp_sample_ctl_rd_A	2147483647	1665	0	0
adc_pd_ctl_rd_A	2147483647	1921	0	0
adc_sample_ctl_rd_A	2147483647	1613	0	0
adc_wakeup_ctl_rd_A	2147483647	1833	0	0
intr_enable_rd_A	2147483647	2472	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2315	0	0
T8	545767	41	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	19	0	0
T15	0	25	0	0
T16	0	32	0	0
T17	0	38	0	0
T18	0	21	0	0
T19	0	14	0	0
T20	0	17	0	0
T21	0	42	0	0
T22	0	39	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2273	0	0
T8	545767	43	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	13	0	0
T15	0	29	0	0
T16	0	25	0	0
T17	0	35	0	0
T18	0	23	0	0
T19	0	25	0	0
T20	0	12	0	0
T21	0	43	0	0
T22	0	30	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2097	0	0
T8	545767	27	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	15	0	0
T15	0	18	0	0
T16	0	28	0	0
T17	0	31	0	0
T18	0	15	0	0
T19	0	20	0	0
T20	0	7	0	0
T21	0	31	0	0
T22	0	35	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2142	0	0
T8	545767	37	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	17	0	0
T15	0	20	0	0
T16	0	37	0	0
T17	0	42	0	0
T18	0	15	0	0
T19	0	6	0	0
T20	0	14	0	0
T21	0	21	0	0
T22	0	21	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2042	0	0
T8	545767	33	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	16	0	0
T15	0	26	0	0
T16	0	17	0	0
T17	0	27	0	0
T18	0	21	0	0
T19	0	20	0	0
T20	0	18	0	0
T21	0	41	0	0
T22	0	31	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2082	0	0
T8	545767	23	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	22	0	0
T15	0	15	0	0
T16	0	32	0	0
T17	0	23	0	0
T18	0	18	0	0
T19	0	11	0	0
T20	0	9	0	0
T21	0	46	0	0
T22	0	39	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2098	0	0
T8	545767	30	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	16	0	0
T15	0	28	0	0
T16	0	17	0	0
T17	0	46	0	0
T18	0	20	0	0
T19	0	15	0	0
T20	0	10	0	0
T21	0	34	0	0
T22	0	35	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1917	0	0
T8	545767	28	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	29	0	0
T15	0	28	0	0
T16	0	29	0	0
T17	0	16	0	0
T18	0	22	0	0
T19	0	11	0	0
T20	0	18	0	0
T21	0	35	0	0
T22	0	51	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1984	0	0
T8	545767	32	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	23	0	0
T15	0	19	0	0
T16	0	28	0	0
T17	0	35	0	0
T18	0	29	0	0
T19	0	5	0	0
T20	0	17	0	0
T21	0	29	0	0
T22	0	33	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2227	0	0
T8	545767	32	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	11	0	0
T15	0	14	0	0
T16	0	28	0	0
T17	0	26	0	0
T18	0	18	0	0
T19	0	24	0	0
T20	0	14	0	0
T21	0	34	0	0
T22	0	36	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2124	0	0
T8	545767	42	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	17	0	0
T15	0	12	0	0
T16	0	19	0	0
T17	0	38	0	0
T18	0	21	0	0
T19	0	12	0	0
T20	0	17	0	0
T21	0	27	0	0
T22	0	50	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2010	0	0
T8	545767	34	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	13	0	0
T15	0	18	0	0
T16	0	33	0	0
T17	0	19	0	0
T18	0	11	0	0
T19	0	16	0	0
T20	0	1	0	0
T21	0	37	0	0
T22	0	30	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2174	0	0
T8	545767	41	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	8	0	0
T15	0	21	0	0
T16	0	25	0	0
T17	0	28	0	0
T18	0	21	0	0
T19	0	31	0	0
T20	0	8	0	0
T21	0	45	0	0
T22	0	40	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2021	0	0
T8	545767	22	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	15	0	0
T15	0	14	0	0
T16	0	30	0	0
T17	0	38	0	0
T18	0	24	0	0
T19	0	13	0	0
T20	0	9	0	0
T21	0	28	0	0
T22	0	35	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2218	0	0
T8	545767	42	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	19	0	0
T15	0	32	0	0
T16	0	27	0	0
T17	0	40	0	0
T18	0	21	0	0
T19	0	17	0	0
T20	0	17	0	0
T21	0	25	0	0
T22	0	30	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2221	0	0
T8	545767	41	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	16	0	0
T15	0	24	0	0
T16	0	10	0	0
T17	0	30	0	0
T18	0	30	0	0
T19	0	17	0	0
T20	0	19	0	0
T21	0	48	0	0
T22	0	49	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1712	0	0
T8	545767	42	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	17	0	0
T15	0	12	0	0
T16	0	31	0	0
T17	0	32	0	0
T18	0	11	0	0
T19	0	14	0	0
T20	0	26	0	0
T21	0	22	0	0
T22	0	30	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1741	0	0
T8	545767	21	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	21	0	0
T15	0	18	0	0
T16	0	18	0	0
T17	0	35	0	0
T18	0	16	0	0
T19	0	6	0	0
T20	0	22	0	0
T21	0	27	0	0
T22	0	31	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2179	0	0
T8	545767	30	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	15	0	0
T15	0	26	0	0
T16	0	26	0	0
T17	0	25	0	0
T18	0	24	0	0
T19	0	21	0	0
T20	0	8	0	0
T21	0	37	0	0
T22	0	28	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1665	0	0
T8	545767	47	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	25	0	0
T15	0	19	0	0
T16	0	26	0	0
T17	0	30	0	0
T18	0	17	0	0
T19	0	11	0	0
T20	0	19	0	0
T21	0	36	0	0
T22	0	45	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1921	0	0
T8	545767	27	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	25	0	0
T15	0	21	0	0
T16	0	41	0	0
T17	0	33	0	0
T18	0	28	0	0
T19	0	28	0	0
T20	0	10	0	0
T21	0	29	0	0
T22	0	44	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1613	0	0
T8	545767	25	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	16	0	0
T15	0	30	0	0
T16	0	19	0	0
T17	0	25	0	0
T18	0	24	0	0
T19	0	12	0	0
T20	0	20	0	0
T21	0	47	0	0
T22	0	31	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1833	0	0
T8	545767	38	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	18	0	0
T15	0	21	0	0
T16	0	20	0	0
T17	0	41	0	0
T18	0	22	0	0
T19	0	5	0	0
T20	0	8	0	0
T21	0	44	0	0
T22	0	42	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2472	0	0
T8	545767	45	0	0
T9	455048	0	0	0
T10	356037	0	0	0
T11	236721	0	0	0
T12	154330	0	0	0
T13	898851	0	0	0
T14	0	24	0	0
T15	0	44	0	0
T16	0	14	0	0
T17	0	43	0	0
T18	0	20	0	0
T19	0	6	0	0
T20	0	16	0	0
T23	304333	0	0	0
T24	777984	0	0	0
T25	793209	0	0	0
T26	688568	0	0	0
T27	0	13	0	0
T28	0	28	0	0