Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1214392	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1186442

1

T1

438

T2

2239

T3

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2103530	1			T1	828		T2	4250		T4	3981
values[0x0]	148439	1			T1	50		T2	144		T3	19
values[0x1]	148865	1			T1	33		T2	128		T3	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	973164	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1427670

1

T1

530

T2

2703

T3

23

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15512	1			T2	19		T4	12		T5	3
valid_sources[0x01]	7635	1			T2	18		T4	13		T5	8
valid_sources[0x02]	8455	1			T2	1		T4	17		T5	12
valid_sources[0x03]	7593	1			T2	9		T4	20		T5	12
valid_sources[0x04]	7019	1			T2	65		T4	10		T5	9
valid_sources[0x05]	7617	1			T2	5		T4	18		T5	7
valid_sources[0x06]	14371	1			T2	12		T4	18		T5	4
valid_sources[0x07]	8425	1			T2	21		T4	18		T5	12
valid_sources[0x08]	8222	1			T2	7		T4	30		T5	3
valid_sources[0x09]	9589	1			T2	12		T4	15		T5	3
valid_sources[0x0a]	7437	1			T2	26		T4	13		T5	3
valid_sources[0x0b]	10297	1			T2	8		T4	12		T5	7
valid_sources[0x0c]	7308	1			T2	19		T4	10		T5	12
valid_sources[0x0d]	7051	1			T2	1		T4	18		T5	11
valid_sources[0x0e]	11531	1			T2	10		T4	20		T5	5
valid_sources[0x0f]	7377	1			T2	10		T4	17		T5	8
valid_sources[0x10]	7553	1			T2	30		T4	17		T5	6
valid_sources[0x11]	7476	1			T2	6		T4	16		T5	5
valid_sources[0x12]	12649	1			T2	12		T4	18		T5	11
valid_sources[0x13]	7410	1			T4	10		T5	12		T6	12
valid_sources[0x14]	7090	1			T2	27		T4	19		T5	9
valid_sources[0x15]	6801	1			T2	33		T4	19		T5	12
valid_sources[0x16]	7065	1			T2	32		T4	17		T5	5
valid_sources[0x17]	8139	1			T2	29		T4	17		T5	2
valid_sources[0x18]	6962	1			T2	26		T4	18		T5	5
valid_sources[0x19]	8081	1			T2	5		T4	22		T5	4
valid_sources[0x1a]	12457	1			T2	9		T4	14		T5	4
valid_sources[0x1b]	7875	1			T2	8		T4	26		T5	5
valid_sources[0x1c]	7655	1			T2	9		T4	25		T5	7
valid_sources[0x1d]	12014	1			T2	32		T4	16		T5	4
valid_sources[0x1e]	11107	1			T2	11		T4	18		T5	2
valid_sources[0x1f]	7525	1			T1	17		T2	14		T4	12
valid_sources[0x20]	11433	1			T2	6		T4	20		T5	6
valid_sources[0x21]	14152	1			T2	23		T4	19		T5	12
valid_sources[0x22]	16133	1			T2	11		T4	22		T5	8
valid_sources[0x23]	9706	1			T1	12		T2	11		T4	12
valid_sources[0x24]	12857	1			T2	26		T4	15		T5	10
valid_sources[0x25]	7609	1			T2	12		T4	14		T6	31
valid_sources[0x26]	8306	1			T2	16		T4	11		T5	1
valid_sources[0x27]	12775	1			T1	20		T2	17		T4	20
valid_sources[0x28]	7412	1			T2	13		T4	13		T5	10
valid_sources[0x29]	9629	1			T2	7		T4	14		T5	6
valid_sources[0x2a]	7238	1			T2	4		T4	23		T5	5
valid_sources[0x2b]	7648	1			T2	24		T4	10		T5	6
valid_sources[0x2c]	7189	1			T2	18		T4	19		T5	7
valid_sources[0x2d]	8129	1			T4	28		T5	2		T6	13
valid_sources[0x2e]	9059	1			T2	5		T4	17		T5	979
valid_sources[0x2f]	7266	1			T2	6		T4	27		T5	4
valid_sources[0x30]	7952	1			T2	23		T4	18		T5	5
valid_sources[0x31]	12859	1			T2	5		T4	6		T5	4
valid_sources[0x32]	8208	1			T2	22		T4	24		T5	10
valid_sources[0x33]	11103	1			T2	9		T4	7		T5	7
valid_sources[0x34]	7721	1			T2	13		T4	11		T5	4
valid_sources[0x35]	8545	1			T2	7		T4	22		T5	5
valid_sources[0x36]	8754	1			T2	22		T4	9		T5	7
valid_sources[0x37]	7181	1			T2	3		T4	19		T5	12
valid_sources[0x38]	8737	1			T2	9		T4	16		T5	4
valid_sources[0x39]	12706	1			T1	46		T2	11		T4	16
valid_sources[0x3a]	7360	1			T2	14		T4	18		T5	2
valid_sources[0x3b]	7399	1			T1	12		T2	29		T4	15
valid_sources[0x3c]	7171	1			T1	18		T2	11		T4	21
valid_sources[0x3d]	8464	1			T2	22		T4	9		T5	3
valid_sources[0x3e]	7884	1			T2	24		T4	13		T5	2
valid_sources[0x3f]	7305	1			T2	12		T4	19		T5	9
valid_sources[0x40]	7175	1			T2	17		T4	21		T5	5
valid_sources[0x41]	7106	1			T2	4		T4	18		T5	6
valid_sources[0x42]	9198	1			T2	20		T4	17		T5	3
valid_sources[0x43]	7331	1			T1	31		T2	29		T4	26
valid_sources[0x44]	7897	1			T1	3		T2	34		T4	19
valid_sources[0x45]	7507	1			T2	11		T4	14		T5	7
valid_sources[0x46]	11782	1			T2	25		T4	31		T5	3
valid_sources[0x47]	7455	1			T2	26		T4	18		T5	9
valid_sources[0x48]	12366	1			T2	16		T4	14		T5	10
valid_sources[0x49]	7694	1			T2	2		T4	14		T5	13
valid_sources[0x4a]	8975	1			T2	36		T4	22		T5	3
valid_sources[0x4b]	8367	1			T2	22		T4	10		T5	7
valid_sources[0x4c]	7459	1			T2	14		T4	10		T5	17
valid_sources[0x4d]	12812	1			T2	30		T4	20		T5	8
valid_sources[0x4e]	8221	1			T2	36		T4	26		T5	13
valid_sources[0x4f]	18621	1			T2	42		T4	18		T5	32
valid_sources[0x50]	9710	1			T2	8		T4	12		T5	3
valid_sources[0x51]	8287	1			T1	6		T2	10		T4	18
valid_sources[0x52]	6890	1			T2	25		T4	26		T5	11
valid_sources[0x53]	7149	1			T2	24		T4	14		T5	10
valid_sources[0x54]	7912	1			T2	16		T4	7		T5	5
valid_sources[0x55]	10308	1			T2	10		T4	16		T5	2
valid_sources[0x56]	7378	1			T2	11		T4	9		T5	6
valid_sources[0x57]	12647	1			T1	4		T2	11		T4	19
valid_sources[0x58]	7756	1			T2	45		T4	22		T5	7
valid_sources[0x59]	7705	1			T1	12		T2	31		T4	7
valid_sources[0x5a]	8068	1			T2	6		T4	16		T5	5
valid_sources[0x5b]	7274	1			T2	3		T4	18		T5	3
valid_sources[0x5c]	10698	1			T2	18		T4	18		T5	2
valid_sources[0x5d]	7705	1			T2	65		T4	19		T5	5
valid_sources[0x5e]	11004	1			T2	20		T4	22		T5	5
valid_sources[0x5f]	11479	1			T1	26		T2	17		T4	18
valid_sources[0x60]	7646	1			T2	19		T4	8		T5	5
valid_sources[0x61]	9651	1			T2	12		T4	9		T5	2
valid_sources[0x62]	9280	1			T2	14		T4	15		T5	10
valid_sources[0x63]	7378	1			T2	16		T4	13		T5	6
valid_sources[0x64]	8000	1			T2	44		T4	11		T5	1
valid_sources[0x65]	7827	1			T2	29		T4	15		T5	7
valid_sources[0x66]	9856	1			T2	3		T4	18		T5	8
valid_sources[0x67]	9226	1			T2	24		T4	12		T5	7
valid_sources[0x68]	11816	1			T1	30		T2	5		T4	13
valid_sources[0x69]	7501	1			T2	25		T4	14		T5	3
valid_sources[0x6a]	11600	1			T2	37		T4	11		T5	7
valid_sources[0x6b]	10173	1			T2	9		T4	12		T5	6
valid_sources[0x6c]	11330	1			T1	74		T2	6		T4	24
valid_sources[0x6d]	10189	1			T2	3		T4	15		T5	5
valid_sources[0x6e]	8319	1			T2	16		T4	14		T5	6
valid_sources[0x6f]	7280	1			T2	86		T4	14		T5	7
valid_sources[0x70]	8168	1			T2	9		T4	23		T5	11
valid_sources[0x71]	7118	1			T2	20		T4	10		T5	5
valid_sources[0x72]	11709	1			T2	14		T4	13		T5	14
valid_sources[0x73]	10071	1			T1	68		T2	2		T4	20
valid_sources[0x74]	23259	1			T2	14		T4	20		T5	5
valid_sources[0x75]	7525	1			T2	55		T4	9		T5	9
valid_sources[0x76]	8556	1			T2	18		T4	12		T5	5
valid_sources[0x77]	7487	1			T2	43		T4	18		T5	5
valid_sources[0x78]	8076	1			T2	9		T4	17		T5	9
valid_sources[0x79]	9796	1			T1	22		T2	9		T4	17
valid_sources[0x7a]	15110	1			T2	4		T4	20		T5	5
valid_sources[0x7b]	8883	1			T2	7		T4	20		T5	3
valid_sources[0x7c]	16461	1			T1	5		T2	7		T4	14
valid_sources[0x7d]	8630	1			T2	12		T4	25		T5	11
valid_sources[0x7e]	8832	1			T2	18		T4	19		T5	10
valid_sources[0x7f]	7275	1			T2	15		T4	15		T5	16
valid_sources[0x80]	7267	1			T2	17		T4	10		T5	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1048539

1

T1

397

T2

2141

T4

2001

values[0x0]

all_enables

biggest_size

80132

1

T1

29

T2

64

T3

12

values[0x1]

all_enables

biggest_size

57771

1

T1

12

T2

34

T3

8