Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30430	1			T1	4		T2	6		T4	5
auto[PWRUP]	124	1			T5	1		T9	2		T10	1
auto[ONEST_0]	90	1			T9	1		T10	2		T192	2
auto[ONEST_021]	12	1			T50	1		T193	2		T194	1
auto[ONEST_1]	84	1			T10	1		T26	1		T28	1
auto[ONEST_DONE]	3	1			T195	1		T196	1		T197	1
auto[LP_0]	129	1			T9	2		T26	2		T28	2
auto[LP_021]	19	1			T9	1		T10	2		T28	1
auto[LP_1]	133	1			T5	1		T10	2		T26	4
auto[LP_EVAL]	52	1			T9	1		T10	1		T47	2
auto[LP_SLP]	483	1			T9	6		T10	6		T26	3
auto[LP_PWRUP]	23	1			T48	1		T49	1		T92	1
auto[NP_0]	177	1			T9	7		T10	1		T26	2
auto[NP_021]	32	1			T28	1		T47	1		T192	1
auto[NP_1]	173	1			T5	1		T10	2		T26	1
auto[NP_EVAL]	38	1			T9	1		T10	1		T26	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T191

1

T198

1

T199

1

min

29834

1

T1

4

T2

6

T4

5

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29844	1			T1	4		T2	6		T4	5
pow[0x1]	12	1			T200	1		T49	1		T90	1
pow[0x2]	13	1			T48	1		T201	1		T202	1
pow[0x3]	43	1			T9	1		T10	1		T26	2
pow[0x4]	66	1			T10	1		T47	1		T192	1
pow[0x5]	124	1			T5	1		T9	1		T10	4
pow[0x6]	277	1			T9	3		T10	4		T26	6
pow[0x7]	538	1			T9	8		T10	2		T12	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

205

1

T9

4

T10

2

T12

1

min

29403

1

T1

4

T2

6

T4

5

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29403	1			T1	4		T2	6		T4	5
pow[0x2]	1	1			T203	1		-	-		-	-
pow[0x6]	1	1			T90	1		-	-		-	-
pow[0x7]	2	1			T192	1		T152	1		-	-
pow[0x8]	7	1			T90	1		T191	1		T204	1
pow[0x9]	10	1			T26	1		T50	1		T195	1
pow[0xa]	17	1			T192	1		T48	1		T90	1
pow[0xb]	37	1			T10	1		T28	1		T47	1
pow[0xc]	84	1			T9	1		T26	1		T28	1
pow[0xd]	127	1			T9	1		T10	3		T12	1
pow[0xe]	275	1			T5	1		T9	1		T10	5
pow[0xf]	633	1			T5	4		T9	4		T10	7