Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2403	1			T5	17		T7	2		T9	19
auto[PWRUP]	143	1			T9	2		T26	3		T28	2
auto[ONEST_0]	83	1			T9	1		T10	1		T26	1
auto[ONEST_021]	16	1			T49	2		T51	1		T347	1
auto[ONEST_1]	111	1			T5	1		T9	1		T10	1
auto[ONEST_DONE]	2	1			T348	1		T347	1		-	-
auto[LP_0]	124	1			T5	1		T10	2		T26	2
auto[LP_021]	30	1			T26	1		T28	1		T47	1
auto[LP_1]	173	1			T5	1		T10	1		T38	1
auto[LP_EVAL]	59	1			T9	1		T28	1		T47	2
auto[LP_SLP]	557	1			T9	4		T10	7		T38	1
auto[LP_PWRUP]	31	1			T9	1		T47	1		T50	1
auto[NP_0]	234	1			T10	3		T38	1		T12	4
auto[NP_021]	54	1			T5	2		T48	1		T49	1
auto[NP_1]	213	1			T9	4		T10	4		T38	2
auto[NP_EVAL]	30	1			T26	2		T192	1		T92	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T192

1

T50

1

T349

1

min

1992

1

T5

12

T7

2

T9

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2006	1			T5	12		T7	2		T9	10
pow[0x1]	6	1			T15	1		T350	1		T201	1
pow[0x2]	29	1			T9	1		T10	1		T40	1
pow[0x3]	39	1			T5	1		T9	1		T10	2
pow[0x4]	64	1			T26	3		T28	1		T192	2
pow[0x5]	135	1			T9	1		T10	2		T26	3
pow[0x6]	306	1			T9	3		T10	2		T26	3
pow[0x7]	543	1			T5	3		T9	3		T10	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

198

1

T5

2

T10

1

T26

2

min

1393

1

T5

10

T7

2

T9

8

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1397	1			T5	10		T7	2		T9	8
pow[0x1]	18	1			T14	4		T18	3		T20	2
pow[0x2]	20	1			T12	2		T13	4		T209	1
pow[0x3]	40	1			T38	1		T16	2		T17	2
pow[0x4]	35	1			T5	1		T38	2		T40	3
pow[0x5]	1	1			T47	1		-	-		-	-
pow[0x6]	3	1			T20	1		T351	1		T352	1
pow[0x7]	1	1			T353	1		-	-		-	-
pow[0x8]	14	1			T48	1		T267	2		T354	1
pow[0x9]	10	1			T355	1		T356	1		T357	1
pow[0xa]	22	1			T12	1		T47	1		T92	1
pow[0xb]	41	1			T192	2		T49	1		T50	1
pow[0xc]	77	1			T9	1		T26	1		T28	1
pow[0xd]	165	1			T5	1		T9	1		T10	3
pow[0xe]	343	1			T5	2		T9	2		T10	8
pow[0xf]	623	1			T5	3		T9	4		T10	5