Unified Coverage Report :: Module :: prim_flop

Module : prim_flop

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_abstract_flop_0/prim_flop.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_adc_ctrl_core.u_oneshot_done_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_adc_ctrl_core.u_oneshot_done_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2

---

Module Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

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							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

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							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00