Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2196	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2323	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2105	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2187	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2171	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2299	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2127	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2254	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2074	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1980	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2126	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2065	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2144	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2142	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2070	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2033	0	0
adc_en_ctl_rd_A	2147483647	1937	0	0
adc_fsm_rst_rd_A	2147483647	1771	0	0
adc_intr_ctl_rd_A	2147483647	2283	0	0
adc_lp_sample_ctl_rd_A	2147483647	1753	0	0
adc_pd_ctl_rd_A	2147483647	1847	0	0
adc_sample_ctl_rd_A	2147483647	1630	0	0
adc_wakeup_ctl_rd_A	2147483647	1719	0	0
intr_enable_rd_A	2147483647	2579	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2196	0	0
T12	292327	18	0	0
T13	0	22	0	0
T14	0	48	0	0
T15	0	4	0	0
T16	0	51	0	0
T17	0	6	0	0
T18	0	43	0	0
T19	0	13	0	0
T20	0	16	0	0
T21	0	25	0	0
T22	897557	0	0	0
T23	519883	0	0	0
T24	194962	0	0	0
T25	586370	0	0	0
T26	112534	0	0	0
T27	282098	0	0	0
T28	129115	0	0	0
T29	408483	0	0	0
T30	189312	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2323	0	0
T12	292327	11	0	0
T13	0	17	0	0
T14	0	34	0	0
T15	0	10	0	0
T16	0	58	0	0
T17	0	15	0	0
T18	0	42	0	0
T19	0	15	0	0
T20	0	11	0	0
T21	0	25	0	0
T22	897557	0	0	0
T23	519883	0	0	0
T24	194962	0	0	0
T25	586370	0	0	0
T26	112534	0	0	0
T27	282098	0	0	0
T28	129115	0	0	0
T29	408483	0	0	0
T30	189312	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2105	0	0
T12	292327	6	0	0
T13	0	32	0	0
T14	0	47	0	0
T15	0	23	0	0
T16	0	41	0	0
T17	0	11	0	0
T18	0	39	0	0
T19	0	16	0	0
T20	0	14	0	0
T21	0	23	0	0
T22	897557	0	0	0
T23	519883	0	0	0
T24	194962	0	0	0
T25	586370	0	0	0
T26	112534	0	0	0
T27	282098	0	0	0
T28	129115	0	0	0
T29	408483	0	0	0
T30	189312	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2187	0	0
T12	292327	4	0	0
T13	0	10	0	0
T14	0	32	0	0
T15	0	9	0	0
T16	0	47	0	0
T17	0	19	0	0
T18	0	30	0	0
T19	0	15	0	0
T20	0	24	0	0
T21	0	36	0	0
T22	897557	0	0	0
T23	519883	0	0	0
T24	194962	0	0	0
T25	586370	0	0	0
T26	112534	0	0	0
T27	282098	0	0	0
T28	129115	0	0	0
T29	408483	0	0	0
T30	189312	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2171	0	0
T12	292327	12	0	0
T13	0	18	0	0
T14	0	49	0	0
T15	0	10	0	0
T16	0	36	0	0
T17	0	13	0	0
T18	0	25	0	0
T19	0	12	0	0
T20	0	10	0	0
T21	0	32	0	0
T22	897557	0	0	0
T23	519883	0	0	0
T24	194962	0	0	0
T25	586370	0	0	0
T26	112534	0	0	0
T27	282098	0	0	0
T28	129115	0	0	0
T29	408483	0	0	0
T30	189312	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2299	0	0
T12	292327	18	0	0
T13	0	16	0	0
T14	0	52	0	0
T15	0	13	0	0
T16	0	31	0	0
T17	0	11	0	0
T18	0	32	0	0
T19	0	21	0	0
T20	0	14	0	0
T21	0	17	0	0
T22	897557	0	0	0
T23	519883	0	0	0
T24	194962	0	0	0
T25	586370	0	0	0
T26	112534	0	0	0
T27	282098	0	0	0
T28	129115	0	0	0
T29	408483	0	0	0
T30	189312	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2127	0	0
T12	292327	5	0	0
T13	0	18	0	0
T14	0	41	0	0
T15	0	15	0	0
T16	0	21	0	0
T17	0	10	0	0
T18	0	49	0	0
T19	0	10	0	0
T20	0	8	0	0
T21	0	22	0	0
T22	897557	0	0	0
T23	519883	0	0	0
T24	194962	0	0	0
T25	586370	0	0	0
T26	112534	0	0	0
T27	282098	0	0	0
T28	129115	0	0	0
T29	408483	0	0	0
T30	189312	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2254	0	0
T12	292327	9	0	0
T13	0	21	0	0
T14	0	48	0	0
T15	0	11	0	0
T16	0	31	0	0
T17	0	7	0	0
T18	0	38	0	0
T19	0	14	0	0
T20	0	12	0	0
T21	0	29	0	0
T22	897557	0	0	0
T23	519883	0	0	0
T24	194962	0	0	0
T25	586370	0	0	0
T26	112534	0	0	0
T27	282098	0	0	0
T28	129115	0	0	0
T29	408483	0	0	0
T30	189312	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2074	0	0
T12	292327	8	0	0
T13	0	19	0	0
T14	0	34	0	0
T15	0	10	0	0
T16	0	46	0	0
T17	0	7	0	0
T18	0	31	0	0
T19	0	18	0	0
T20	0	12	0	0
T21	0	10	0	0
T22	897557	0	0	0
T23	519883	0	0	0
T24	194962	0	0	0
T25	586370	0	0	0
T26	112534	0	0	0
T27	282098	0	0	0
T28	129115	0	0	0
T29	408483	0	0	0
T30	189312	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1980	0	0
T12	292327	5	0	0
T13	0	16	0	0
T14	0	47	0	0
T15	0	9	0	0
T16	0	41	0	0
T17	0	6	0	0
T18	0	35	0	0
T19	0	6	0	0
T20	0	11	0	0
T21	0	27	0	0
T22	897557	0	0	0
T23	519883	0	0	0
T24	194962	0	0	0
T25	586370	0	0	0
T26	112534	0	0	0
T27	282098	0	0	0
T28	129115	0	0	0
T29	408483	0	0	0
T30	189312	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2126	0	0
T12	292327	19	0	0
T13	0	31	0	0
T14	0	43	0	0
T15	0	10	0	0
T16	0	22	0	0
T17	0	14	0	0
T18	0	25	0	0
T19	0	14	0	0
T20	0	3	0	0
T21	0	32	0	0
T22	897557	0	0	0
T23	519883	0	0	0
T24	194962	0	0	0
T25	586370	0	0	0
T26	112534	0	0	0
T27	282098	0	0	0
T28	129115	0	0	0
T29	408483	0	0	0
T30	189312	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2065	0	0
T12	292327	7	0	0
T13	0	25	0	0
T14	0	30	0	0
T15	0	18	0	0
T16	0	41	0	0
T17	0	12	0	0
T18	0	54	0	0
T19	0	20	0	0
T20	0	17	0	0
T21	0	14	0	0
T22	897557	0	0	0
T23	519883	0	0	0
T24	194962	0	0	0
T25	586370	0	0	0
T26	112534	0	0	0
T27	282098	0	0	0
T28	129115	0	0	0
T29	408483	0	0	0
T30	189312	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2144	0	0
T12	292327	12	0	0
T13	0	8	0	0
T14	0	43	0	0
T15	0	17	0	0
T16	0	34	0	0
T17	0	24	0	0
T18	0	30	0	0
T19	0	16	0	0
T20	0	11	0	0
T21	0	24	0	0
T22	897557	0	0	0
T23	519883	0	0	0
T24	194962	0	0	0
T25	586370	0	0	0
T26	112534	0	0	0
T27	282098	0	0	0
T28	129115	0	0	0
T29	408483	0	0	0
T30	189312	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2142	0	0
T12	292327	16	0	0
T13	0	13	0	0
T14	0	44	0	0
T15	0	6	0	0
T16	0	27	0	0
T17	0	22	0	0
T18	0	38	0	0
T19	0	11	0	0
T20	0	17	0	0
T21	0	31	0	0
T22	897557	0	0	0
T23	519883	0	0	0
T24	194962	0	0	0
T25	586370	0	0	0
T26	112534	0	0	0
T27	282098	0	0	0
T28	129115	0	0	0
T29	408483	0	0	0
T30	189312	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2070	0	0
T12	292327	21	0	0
T13	0	13	0	0
T14	0	38	0	0
T15	0	5	0	0
T16	0	45	0	0
T17	0	14	0	0
T18	0	35	0	0
T19	0	15	0	0
T20	0	20	0	0
T21	0	22	0	0
T22	897557	0	0	0
T23	519883	0	0	0
T24	194962	0	0	0
T25	586370	0	0	0
T26	112534	0	0	0
T27	282098	0	0	0
T28	129115	0	0	0
T29	408483	0	0	0
T30	189312	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2033	0	0
T12	292327	12	0	0
T13	0	18	0	0
T14	0	37	0	0
T15	0	8	0	0
T16	0	32	0	0
T17	0	19	0	0
T18	0	50	0	0
T19	0	13	0	0
T20	0	6	0	0
T21	0	24	0	0
T22	897557	0	0	0
T23	519883	0	0	0
T24	194962	0	0	0
T25	586370	0	0	0
T26	112534	0	0	0
T27	282098	0	0	0
T28	129115	0	0	0
T29	408483	0	0	0
T30	189312	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1937	0	0
T12	292327	10	0	0
T13	0	20	0	0
T14	0	52	0	0
T15	0	2	0	0
T16	0	28	0	0
T17	0	15	0	0
T18	0	33	0	0
T19	0	15	0	0
T20	0	20	0	0
T21	0	24	0	0
T22	897557	0	0	0
T23	519883	0	0	0
T24	194962	0	0	0
T25	586370	0	0	0
T26	112534	0	0	0
T27	282098	0	0	0
T28	129115	0	0	0
T29	408483	0	0	0
T30	189312	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1771	0	0
T12	292327	7	0	0
T13	0	12	0	0
T14	0	28	0	0
T15	0	10	0	0
T16	0	41	0	0
T17	0	14	0	0
T18	0	24	0	0
T19	0	18	0	0
T20	0	12	0	0
T21	0	30	0	0
T22	897557	0	0	0
T23	519883	0	0	0
T24	194962	0	0	0
T25	586370	0	0	0
T26	112534	0	0	0
T27	282098	0	0	0
T28	129115	0	0	0
T29	408483	0	0	0
T30	189312	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2283	0	0
T12	292327	9	0	0
T13	0	26	0	0
T14	0	38	0	0
T15	0	10	0	0
T16	0	47	0	0
T17	0	17	0	0
T18	0	39	0	0
T19	0	15	0	0
T20	0	8	0	0
T21	0	38	0	0
T22	897557	0	0	0
T23	519883	0	0	0
T24	194962	0	0	0
T25	586370	0	0	0
T26	112534	0	0	0
T27	282098	0	0	0
T28	129115	0	0	0
T29	408483	0	0	0
T30	189312	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1753	0	0
T12	292327	23	0	0
T13	0	22	0	0
T14	0	52	0	0
T15	0	10	0	0
T16	0	18	0	0
T17	0	5	0	0
T18	0	40	0	0
T19	0	9	0	0
T20	0	13	0	0
T21	0	23	0	0
T22	897557	0	0	0
T23	519883	0	0	0
T24	194962	0	0	0
T25	586370	0	0	0
T26	112534	0	0	0
T27	282098	0	0	0
T28	129115	0	0	0
T29	408483	0	0	0
T30	189312	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1847	0	0
T12	292327	11	0	0
T13	0	22	0	0
T14	0	42	0	0
T15	0	20	0	0
T16	0	23	0	0
T17	0	7	0	0
T18	0	58	0	0
T19	0	19	0	0
T20	0	5	0	0
T21	0	21	0	0
T22	897557	0	0	0
T23	519883	0	0	0
T24	194962	0	0	0
T25	586370	0	0	0
T26	112534	0	0	0
T27	282098	0	0	0
T28	129115	0	0	0
T29	408483	0	0	0
T30	189312	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1630	0	0
T12	292327	16	0	0
T13	0	16	0	0
T14	0	42	0	0
T15	0	4	0	0
T16	0	22	0	0
T17	0	11	0	0
T18	0	40	0	0
T19	0	14	0	0
T20	0	14	0	0
T21	0	16	0	0
T22	897557	0	0	0
T23	519883	0	0	0
T24	194962	0	0	0
T25	586370	0	0	0
T26	112534	0	0	0
T27	282098	0	0	0
T28	129115	0	0	0
T29	408483	0	0	0
T30	189312	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1719	0	0
T12	292327	9	0	0
T13	0	20	0	0
T14	0	49	0	0
T15	0	10	0	0
T16	0	35	0	0
T17	0	16	0	0
T18	0	41	0	0
T19	0	13	0	0
T20	0	9	0	0
T21	0	18	0	0
T22	897557	0	0	0
T23	519883	0	0	0
T24	194962	0	0	0
T25	586370	0	0	0
T26	112534	0	0	0
T27	282098	0	0	0
T28	129115	0	0	0
T29	408483	0	0	0
T30	189312	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2579	0	0
T7	457376	7	0	0
T8	703407	0	0	0
T9	405342	0	0	0
T10	101111	0	0	0
T11	330899	0	0	0
T12	0	14	0	0
T13	0	14	0	0
T14	0	56	0	0
T15	0	23	0	0
T16	0	49	0	0
T17	0	50	0	0
T18	0	55	0	0
T31	0	5	0	0
T32	0	15	0	0
T33	43275	0	0	0
T34	147680	0	0	0
T35	171805	0	0	0
T36	443427	0	0	0
T37	144754	0	0	0