Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1291171	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1262923

1

T1

16

T2

2071

T3

2027

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2246704	1			T2	3982		T3	3261		T4	81
values[0x0]	152967	1			T1	17		T2	149		T3	416
values[0x1]	154423	1			T1	17		T2	135		T3	463

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1034312	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1519782

1

T1

16

T2

2523

T3

2445

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7797	1			T2	21		T3	1		T5	10
valid_sources[0x01]	9489	1			T2	23		T3	5		T5	7
valid_sources[0x02]	7725	1			T2	17		T3	29		T5	8
valid_sources[0x03]	12967	1			T2	15		T3	2		T5	8
valid_sources[0x04]	7721	1			T2	11		T3	17		T5	8
valid_sources[0x05]	8976	1			T2	12		T3	21		T5	10
valid_sources[0x06]	8926	1			T2	21		T3	33		T4	1
valid_sources[0x07]	9962	1			T2	17		T3	11		T5	12
valid_sources[0x08]	7803	1			T2	32		T3	2		T5	8
valid_sources[0x09]	7470	1			T2	21		T3	14		T4	3
valid_sources[0x0a]	7609	1			T2	16		T3	9		T5	7
valid_sources[0x0b]	7971	1			T1	1		T2	28		T3	38
valid_sources[0x0c]	7587	1			T2	20		T3	31		T4	1
valid_sources[0x0d]	13189	1			T2	16		T3	1		T5	9
valid_sources[0x0e]	7596	1			T2	19		T3	11		T5	5
valid_sources[0x0f]	7450	1			T1	2		T2	5		T3	25
valid_sources[0x10]	7723	1			T2	11		T3	27		T5	13
valid_sources[0x11]	8581	1			T2	17		T3	1		T5	8
valid_sources[0x12]	9363	1			T2	24		T3	2		T5	7
valid_sources[0x13]	12741	1			T1	1		T2	15		T3	39
valid_sources[0x14]	7738	1			T2	12		T3	47		T5	9
valid_sources[0x15]	13219	1			T2	15		T3	3		T5	5
valid_sources[0x16]	8259	1			T2	7		T3	38		T5	6
valid_sources[0x17]	7491	1			T2	6		T3	30		T5	3
valid_sources[0x18]	12680	1			T2	23		T3	1		T5	11
valid_sources[0x19]	12113	1			T2	12		T3	8		T4	8
valid_sources[0x1a]	7803	1			T2	22		T3	24		T5	9
valid_sources[0x1b]	7899	1			T2	13		T3	91		T5	11
valid_sources[0x1c]	8632	1			T2	15		T3	4		T4	2
valid_sources[0x1d]	8033	1			T2	24		T3	31		T4	1
valid_sources[0x1e]	7510	1			T2	8		T3	36		T4	2
valid_sources[0x1f]	7529	1			T2	9		T3	4		T5	6
valid_sources[0x20]	11881	1			T2	13		T3	12		T4	4
valid_sources[0x21]	7946	1			T2	13		T3	33		T5	7
valid_sources[0x22]	9801	1			T2	21		T3	26		T5	8
valid_sources[0x23]	7390	1			T1	1		T2	6		T5	9
valid_sources[0x24]	7281	1			T2	22		T3	20		T4	2
valid_sources[0x25]	16537	1			T2	4		T3	41		T5	4
valid_sources[0x26]	7423	1			T2	19		T3	6		T5	6
valid_sources[0x27]	9209	1			T2	12		T3	18		T5	4
valid_sources[0x28]	8342	1			T2	15		T3	5		T5	7
valid_sources[0x29]	16547	1			T2	20		T3	11		T5	6
valid_sources[0x2a]	12235	1			T2	19		T3	39		T5	9
valid_sources[0x2b]	11298	1			T2	9		T3	9		T5	7
valid_sources[0x2c]	7541	1			T2	29		T3	44		T5	11
valid_sources[0x2d]	10213	1			T2	17		T3	28		T5	6
valid_sources[0x2e]	10485	1			T2	19		T3	16		T5	8
valid_sources[0x2f]	13822	1			T2	12		T3	30		T4	1
valid_sources[0x30]	9446	1			T2	11		T3	5		T5	9
valid_sources[0x31]	7352	1			T2	14		T3	39		T5	6
valid_sources[0x32]	13223	1			T2	13		T3	26		T5	7
valid_sources[0x33]	10117	1			T2	9		T3	10		T5	14
valid_sources[0x34]	7517	1			T2	8		T3	24		T5	5
valid_sources[0x35]	17507	1			T2	21		T3	33		T5	10
valid_sources[0x36]	11526	1			T2	13		T3	1		T5	5
valid_sources[0x37]	8120	1			T2	18		T3	7		T5	4
valid_sources[0x38]	7569	1			T2	4		T4	1		T5	4
valid_sources[0x39]	12715	1			T1	1		T2	14		T3	3
valid_sources[0x3a]	11671	1			T2	23		T3	1		T4	1
valid_sources[0x3b]	12608	1			T2	23		T3	11		T5	8
valid_sources[0x3c]	7824	1			T2	11		T3	13		T5	7
valid_sources[0x3d]	8460	1			T2	5		T3	5		T5	7
valid_sources[0x3e]	10131	1			T1	1		T2	13		T3	4
valid_sources[0x3f]	9674	1			T2	10		T3	14		T4	1
valid_sources[0x40]	12191	1			T2	12		T3	7		T4	4
valid_sources[0x41]	7627	1			T2	9		T3	17		T5	3
valid_sources[0x42]	7811	1			T2	32		T3	3		T5	8
valid_sources[0x43]	7492	1			T2	25		T3	41		T5	8
valid_sources[0x44]	11042	1			T2	29		T3	1		T4	2
valid_sources[0x45]	7767	1			T2	24		T3	3		T5	8
valid_sources[0x46]	8737	1			T2	32		T5	8		T9	2
valid_sources[0x47]	8659	1			T2	20		T3	16		T5	3
valid_sources[0x48]	8356	1			T1	1		T2	19		T3	3
valid_sources[0x49]	8481	1			T2	15		T3	1		T5	3
valid_sources[0x4a]	8694	1			T2	14		T3	2		T4	10
valid_sources[0x4b]	9415	1			T1	2		T2	13		T3	30
valid_sources[0x4c]	7598	1			T2	14		T3	22		T4	1
valid_sources[0x4d]	8077	1			T2	7		T3	22		T5	5
valid_sources[0x4e]	7338	1			T1	1		T2	16		T3	1
valid_sources[0x4f]	8660	1			T2	19		T3	10		T5	8
valid_sources[0x50]	8833	1			T2	21		T3	34		T4	4
valid_sources[0x51]	12836	1			T1	1		T2	8		T3	25
valid_sources[0x52]	7739	1			T1	1		T2	32		T3	42
valid_sources[0x53]	8953	1			T2	6		T3	11		T5	4
valid_sources[0x54]	8787	1			T2	10		T3	2		T5	7
valid_sources[0x55]	8086	1			T2	17		T3	26		T5	11
valid_sources[0x56]	7753	1			T1	1		T2	20		T3	34
valid_sources[0x57]	7571	1			T2	18		T3	5		T5	10
valid_sources[0x58]	7800	1			T2	22		T3	1		T5	8
valid_sources[0x59]	7640	1			T2	7		T3	44		T5	7
valid_sources[0x5a]	7464	1			T2	23		T3	1		T5	13
valid_sources[0x5b]	11658	1			T2	14		T3	17		T4	2
valid_sources[0x5c]	7718	1			T2	18		T3	17		T5	7
valid_sources[0x5d]	10670	1			T2	6		T3	27		T4	2
valid_sources[0x5e]	7539	1			T2	16		T3	1		T5	2
valid_sources[0x5f]	7714	1			T2	23		T3	4		T5	2
valid_sources[0x60]	8603	1			T1	1		T2	19		T5	5
valid_sources[0x61]	8650	1			T2	17		T3	1		T5	7
valid_sources[0x62]	16178	1			T2	23		T3	9		T5	5
valid_sources[0x63]	7453	1			T2	12		T3	6		T4	9
valid_sources[0x64]	7610	1			T2	9		T3	22		T5	4
valid_sources[0x65]	7847	1			T2	38		T3	40		T5	6
valid_sources[0x66]	12391	1			T2	20		T3	14		T4	1
valid_sources[0x67]	7970	1			T2	23		T3	4		T4	3
valid_sources[0x68]	7656	1			T2	24		T3	6		T5	12
valid_sources[0x69]	7760	1			T2	16		T3	16		T5	9
valid_sources[0x6a]	8479	1			T2	3		T3	22		T5	12
valid_sources[0x6b]	7410	1			T2	6		T3	10		T5	6
valid_sources[0x6c]	16060	1			T2	18		T3	45		T5	9
valid_sources[0x6d]	7056	1			T2	11		T3	14		T5	8
valid_sources[0x6e]	9742	1			T2	4		T3	3		T5	9
valid_sources[0x6f]	9561	1			T2	16		T3	10		T5	10
valid_sources[0x70]	10469	1			T2	10		T3	19		T5	4
valid_sources[0x71]	24490	1			T1	1		T2	13		T3	9
valid_sources[0x72]	21931	1			T2	21		T3	6		T4	3
valid_sources[0x73]	17023	1			T1	1		T2	15		T3	23
valid_sources[0x74]	8043	1			T2	24		T3	3		T4	1
valid_sources[0x75]	8039	1			T1	1		T2	22		T3	8
valid_sources[0x76]	11057	1			T2	15		T3	2		T4	3
valid_sources[0x77]	12045	1			T2	1		T3	24		T5	7
valid_sources[0x78]	11945	1			T2	18		T3	6		T5	7
valid_sources[0x79]	16004	1			T2	10		T3	1		T5	3
valid_sources[0x7a]	7656	1			T2	25		T3	20		T5	1
valid_sources[0x7b]	7498	1			T1	1		T2	14		T3	41
valid_sources[0x7c]	8432	1			T1	1		T2	16		T3	11
valid_sources[0x7d]	7448	1			T2	18		T3	17		T5	1
valid_sources[0x7e]	7523	1			T2	38		T3	21		T5	5
valid_sources[0x7f]	7476	1			T1	2		T2	21		T3	46
valid_sources[0x80]	7896	1			T2	15		T3	8		T4	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1118485

1

T2

1962

T3

1619

T4

46

values[0x0]

all_enables

biggest_size

83715

1

T1

9

T2

69

T3

225

values[0x1]

all_enables

biggest_size

60723

1

T1

7

T2

40

T3

183