Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28434	1			T2	7		T3	45		T5	17
auto[PWRUP]	112	1			T3	1		T38	1		T39	2
auto[ONEST_0]	57	1			T38	1		T43	1		T34	2
auto[ONEST_021]	18	1			T42	1		T45	1		T179	1
auto[ONEST_1]	76	1			T39	4		T43	1		T34	2
auto[ONEST_DONE]	7	1			T180	1		T15	1		T16	1
auto[LP_0]	114	1			T3	1		T38	4		T39	4
auto[LP_021]	25	1			T40	2		T41	1		T42	1
auto[LP_1]	112	1			T38	1		T39	3		T43	1
auto[LP_EVAL]	62	1			T3	1		T38	4		T43	1
auto[LP_SLP]	480	1			T3	2		T38	9		T39	4
auto[LP_PWRUP]	27	1			T34	1		T13	1		T42	1
auto[NP_0]	145	1			T38	1		T43	2		T34	3
auto[NP_021]	40	1			T39	1		T43	1		T34	1
auto[NP_1]	158	1			T38	2		T39	2		T43	1
auto[NP_EVAL]	37	1			T13	1		T40	1		T41	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T181

1

T182

1

T183

1

min

27897

1

T2

7

T3

45

T5

17

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27910	1			T2	7		T3	45		T5	17
pow[0x1]	3	1			T184	1		T185	1		T97	1
pow[0x2]	18	1			T13	1		T181	1		T179	1
pow[0x3]	29	1			T39	1		T92	1		T27	1
pow[0x4]	70	1			T38	2		T39	1		T43	1
pow[0x5]	128	1			T38	3		T39	1		T43	1
pow[0x6]	265	1			T3	1		T38	8		T39	2
pow[0x7]	529	1			T3	2		T38	6		T39	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

171

1

T38

4

T39

1

T43

1

min

27465

1

T2

7

T3

42

T5

17

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27465	1			T2	7		T3	42		T5	17
pow[0x3]	1	1			T186	1		-	-		-	-
pow[0x4]	1	1			T187	1		-	-		-	-
pow[0x5]	2	1			T188	1		T189	1		-	-
pow[0x7]	3	1			T190	1		T191	1		T192	1
pow[0x8]	1	1			T182	1		-	-		-	-
pow[0x9]	13	1			T38	1		T40	1		T193	1
pow[0xa]	14	1			T43	1		T40	2		T30	1
pow[0xb]	32	1			T39	1		T34	1		T42	2
pow[0xc]	80	1			T39	1		T34	1		T92	1
pow[0xd]	155	1			T38	4		T34	3		T13	3
pow[0xe]	295	1			T3	3		T38	5		T39	2
pow[0xf]	528	1			T3	1		T38	5		T39	13