Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2268	1			T3	19		T38	22		T39	15
auto[PWRUP]	140	1			T38	1		T39	1		T43	1
auto[ONEST_0]	64	1			T3	1		T38	2		T34	2
auto[ONEST_021]	14	1			T3	1		T39	1		T41	1
auto[ONEST_1]	88	1			T39	1		T43	2		T34	2
auto[ONEST_DONE]	5	1			T43	1		T15	1		T326	1
auto[LP_0]	113	1			T38	2		T43	1		T34	5
auto[LP_021]	30	1			T41	2		T29	1		T30	1
auto[LP_1]	121	1			T38	4		T39	1		T34	2
auto[LP_EVAL]	52	1			T38	1		T43	2		T34	2
auto[LP_SLP]	493	1			T3	1		T38	4		T39	4
auto[LP_PWRUP]	29	1			T38	1		T34	1		T42	1
auto[NP_0]	209	1			T3	7		T38	2		T39	2
auto[NP_021]	44	1			T43	1		T34	1		T92	1
auto[NP_1]	247	1			T3	2		T38	4		T39	3
auto[NP_EVAL]	38	1			T13	1		T26	2		T92	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

11

1

T30

1

T327

1

T83

1

min

2005

1

T3

23

T38

7

T39

4

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2017	1			T3	23		T38	7		T39	4
pow[0x1]	12	1			T13	1		T40	1		T42	1
pow[0x2]	19	1			T43	1		T41	2		T181	1
pow[0x3]	34	1			T38	1		T34	2		T40	1
pow[0x4]	74	1			T3	1		T34	1		T41	1
pow[0x5]	136	1			T38	1		T39	1		T34	6
pow[0x6]	242	1			T3	2		T38	7		T39	2
pow[0x7]	474	1			T38	6		T39	8		T43	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

200

1

T3

1

T38

7

T39

1

min

1431

1

T3

17

T38

3

T39

1

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1440	1			T3	17		T38	3		T39	1
pow[0x1]	16	1			T3	1		T27	3		T32	1
pow[0x2]	31	1			T29	2		T30	1		T15	4
pow[0x3]	62	1			T3	2		T13	2		T26	1
pow[0x4]	52	1			T3	2		T13	3		T25	3
pow[0x5]	1	1			T34	1		-	-		-	-
pow[0x6]	1	1			T83	1		-	-		-	-
pow[0x8]	5	1			T42	1		T45	1		T83	1
pow[0x9]	15	1			T43	1		T34	1		T40	1
pow[0xa]	17	1			T92	1		T29	1		T30	1
pow[0xb]	35	1			T38	1		T34	2		T42	2
pow[0xc]	62	1			T39	1		T43	1		T34	3
pow[0xd]	132	1			T3	2		T38	2		T39	2
pow[0xe]	294	1			T3	1		T38	6		T39	3
pow[0xf]	547	1			T38	7		T39	8		T43	4