Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2843	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2631	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2556	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2921	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2592	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2699	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2858	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2565	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2623	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2910	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2650	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2831	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2665	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2687	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2546	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2810	0	0
adc_en_ctl_rd_A	2147483647	2305	0	0
adc_fsm_rst_rd_A	2147483647	2389	0	0
adc_intr_ctl_rd_A	2147483647	2777	0	0
adc_lp_sample_ctl_rd_A	2147483647	2130	0	0
adc_pd_ctl_rd_A	2147483647	2519	0	0
adc_sample_ctl_rd_A	2147483647	2502	0	0
adc_wakeup_ctl_rd_A	2147483647	2195	0	0
intr_enable_rd_A	2147483647	2839	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2843	0	0
T3	291951	24	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	50	0	0
T14	0	22	0	0
T15	0	40	0	0
T16	0	37	0	0
T17	0	14	0	0
T18	0	25	0	0
T19	0	51	0	0
T20	0	34	0	0
T21	0	20	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2631	0	0
T3	291951	38	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	22	0	0
T14	0	4	0	0
T15	0	35	0	0
T16	0	27	0	0
T17	0	13	0	0
T18	0	22	0	0
T19	0	27	0	0
T20	0	23	0	0
T21	0	7	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2556	0	0
T3	291951	19	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	24	0	0
T14	0	8	0	0
T15	0	40	0	0
T16	0	25	0	0
T17	0	2	0	0
T18	0	15	0	0
T19	0	19	0	0
T20	0	24	0	0
T21	0	9	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2921	0	0
T3	291951	25	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	38	0	0
T14	0	19	0	0
T15	0	32	0	0
T16	0	22	0	0
T17	0	10	0	0
T18	0	16	0	0
T19	0	32	0	0
T20	0	25	0	0
T21	0	4	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2592	0	0
T3	291951	19	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	19	0	0
T14	0	13	0	0
T15	0	28	0	0
T16	0	23	0	0
T17	0	16	0	0
T18	0	9	0	0
T19	0	45	0	0
T20	0	24	0	0
T21	0	2	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2699	0	0
T3	291951	27	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	24	0	0
T14	0	6	0	0
T15	0	38	0	0
T16	0	5	0	0
T17	0	15	0	0
T18	0	22	0	0
T19	0	34	0	0
T20	0	19	0	0
T21	0	15	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2858	0	0
T3	291951	33	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	40	0	0
T14	0	37	0	0
T15	0	46	0	0
T16	0	17	0	0
T17	0	17	0	0
T18	0	16	0	0
T19	0	37	0	0
T20	0	15	0	0
T21	0	18	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2565	0	0
T3	291951	38	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	26	0	0
T14	0	25	0	0
T15	0	32	0	0
T16	0	13	0	0
T17	0	14	0	0
T18	0	16	0	0
T19	0	30	0	0
T20	0	16	0	0
T22	0	29	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2623	0	0
T3	291951	15	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	35	0	0
T14	0	10	0	0
T15	0	39	0	0
T16	0	24	0	0
T17	0	8	0	0
T18	0	19	0	0
T19	0	42	0	0
T20	0	32	0	0
T21	0	17	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2910	0	0
T3	291951	44	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	41	0	0
T14	0	18	0	0
T15	0	49	0	0
T16	0	9	0	0
T17	0	6	0	0
T18	0	25	0	0
T19	0	43	0	0
T20	0	29	0	0
T21	0	5	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2650	0	0
T3	291951	32	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	15	0	0
T14	0	17	0	0
T15	0	42	0	0
T16	0	15	0	0
T17	0	5	0	0
T18	0	8	0	0
T19	0	18	0	0
T20	0	30	0	0
T22	0	50	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2831	0	0
T3	291951	38	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	27	0	0
T14	0	24	0	0
T15	0	36	0	0
T16	0	22	0	0
T17	0	12	0	0
T18	0	8	0	0
T19	0	29	0	0
T20	0	12	0	0
T21	0	2	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2665	0	0
T3	291951	18	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	29	0	0
T14	0	17	0	0
T15	0	38	0	0
T16	0	11	0	0
T17	0	3	0	0
T18	0	25	0	0
T19	0	45	0	0
T20	0	18	0	0
T21	0	11	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2687	0	0
T3	291951	23	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	22	0	0
T14	0	11	0	0
T15	0	31	0	0
T16	0	33	0	0
T17	0	8	0	0
T18	0	17	0	0
T19	0	32	0	0
T20	0	28	0	0
T22	0	44	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2546	0	0
T3	291951	29	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	26	0	0
T14	0	11	0	0
T15	0	30	0	0
T16	0	10	0	0
T17	0	2	0	0
T18	0	25	0	0
T19	0	38	0	0
T20	0	15	0	0
T21	0	9	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2810	0	0
T3	291951	26	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	21	0	0
T14	0	27	0	0
T15	0	47	0	0
T16	0	12	0	0
T17	0	2	0	0
T18	0	18	0	0
T19	0	38	0	0
T20	0	20	0	0
T21	0	13	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2305	0	0
T3	291951	29	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	24	0	0
T14	0	31	0	0
T15	0	33	0	0
T16	0	20	0	0
T17	0	9	0	0
T18	0	15	0	0
T19	0	34	0	0
T20	0	27	0	0
T21	0	5	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2389	0	0
T3	291951	38	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	33	0	0
T14	0	26	0	0
T15	0	25	0	0
T16	0	17	0	0
T17	0	13	0	0
T18	0	27	0	0
T19	0	39	0	0
T20	0	29	0	0
T21	0	4	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2777	0	0
T3	291951	36	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	32	0	0
T14	0	14	0	0
T15	0	34	0	0
T16	0	28	0	0
T17	0	14	0	0
T18	0	15	0	0
T19	0	48	0	0
T20	0	15	0	0
T21	0	22	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2130	0	0
T3	291951	36	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	36	0	0
T14	0	4	0	0
T15	0	42	0	0
T16	0	24	0	0
T17	0	11	0	0
T18	0	17	0	0
T19	0	44	0	0
T20	0	14	0	0
T22	0	27	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2519	0	0
T3	291951	26	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	42	0	0
T14	0	16	0	0
T15	0	56	0	0
T16	0	24	0	0
T18	0	18	0	0
T19	0	31	0	0
T20	0	25	0	0
T21	0	9	0	0
T22	0	34	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2502	0	0
T3	291951	39	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	26	0	0
T14	0	21	0	0
T15	0	58	0	0
T16	0	26	0	0
T17	0	4	0	0
T18	0	18	0	0
T19	0	32	0	0
T20	0	28	0	0
T21	0	2	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2195	0	0
T3	291951	38	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	31	0	0
T14	0	23	0	0
T15	0	31	0	0
T16	0	13	0	0
T17	0	5	0	0
T18	0	32	0	0
T19	0	44	0	0
T20	0	30	0	0
T22	0	33	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2839	0	0
T3	291951	60	0	0
T4	364386	0	0	0
T5	319565	0	0	0
T6	787530	0	0	0
T7	161842	0	0	0
T8	559315	0	0	0
T9	201782	0	0	0
T10	188309	0	0	0
T11	732539	0	0	0
T12	496280	0	0	0
T13	0	57	0	0
T14	0	42	0	0
T15	0	67	0	0
T16	0	35	0	0
T17	0	3	0	0
T18	0	17	0	0
T19	0	61	0	0
T23	0	19	0	0
T24	0	12	0	0