Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7281	1			T4	20		T6	20		T7	43
testmodes[AdcCtrlTestmodeNormal]	5487	1			T3	3		T5	1		T7	32
testmodes[AdcCtrlTestmodeLowpower]	5788	1			T1	2		T2	11		T5	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	4014	1			T4	19		T6	19		T7	10
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1746	1			T7	17		T9	3		T43	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1404	1			T7	16		T18	9		T34	9
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1754	1			T7	14		T9	4		T43	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1955	1			T3	2		T7	6		T9	6
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1439	1			T5	1		T7	12		T17	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1401	1			T7	19		T17	1		T18	7
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1447	1			T5	1		T7	9		T17	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2697	1			T1	1		T2	10		T7	18