| | | | | | | |
tb.dut.AdcKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.AlertsKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 2147483647 | 60 | 0 | 0 |
|
tb.dut.IntrKnown
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.TlOAReadyKnown
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.TlODValidKnown
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.WakeKnown
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_0_rd_A
| 0 | 0 | 2147483647 | 2268 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_1_rd_A
| 0 | 0 | 2147483647 | 2473 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_2_rd_A
| 0 | 0 | 2147483647 | 2457 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_3_rd_A
| 0 | 0 | 2147483647 | 2382 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_4_rd_A
| 0 | 0 | 2147483647 | 2389 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_5_rd_A
| 0 | 0 | 2147483647 | 2458 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_6_rd_A
| 0 | 0 | 2147483647 | 2365 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_7_rd_A
| 0 | 0 | 2147483647 | 2355 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_0_rd_A
| 0 | 0 | 2147483647 | 2414 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_1_rd_A
| 0 | 0 | 2147483647 | 2487 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_2_rd_A
| 0 | 0 | 2147483647 | 2283 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_3_rd_A
| 0 | 0 | 2147483647 | 2415 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_4_rd_A
| 0 | 0 | 2147483647 | 2347 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_5_rd_A
| 0 | 0 | 2147483647 | 2366 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_6_rd_A
| 0 | 0 | 2147483647 | 2290 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_7_rd_A
| 0 | 0 | 2147483647 | 2319 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_en_ctl_rd_A
| 0 | 0 | 2147483647 | 1925 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_fsm_rst_rd_A
| 0 | 0 | 2147483647 | 1706 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_intr_ctl_rd_A
| 0 | 0 | 2147483647 | 2779 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_lp_sample_ctl_rd_A
| 0 | 0 | 2147483647 | 1930 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_pd_ctl_rd_A
| 0 | 0 | 2147483647 | 2192 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_sample_ctl_rd_A
| 0 | 0 | 2147483647 | 1733 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_wakeup_ctl_rd_A
| 0 | 0 | 2147483647 | 2060 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.intr_enable_rd_A
| 0 | 0 | 2147483647 | 3052 | 0 | 0 |
|
tb.dut.tlul_assert_device.aKnown_A
| 0 | 0 | 2147483647 | 26421553 | 0 | 0 |
|
tb.dut.tlul_assert_device.aKnown_AKnownEnable
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.tlul_assert_device.aReadyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.tlul_assert_device.dKnown_A
| 0 | 0 | 2147483647 | 4711822 | 0 | 0 |
|
tb.dut.tlul_assert_device.dKnown_AKnownEnable
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.tlul_assert_device.dReadyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[222].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[223].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[225].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.aDataKnown_M
| 0 | 0 | 2147483647 | 17622349 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A
| 0 | 0 | 2147483647 | 2662 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.contigMask_M
| 0 | 0 | 2147483647 | 16021401 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.dDataKnown_A
| 0 | 0 | 2147483647 | 3889155 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A
| 0 | 0 | 2147483647 | 2582 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAParam_M
| 0 | 0 | 2147483647 | 26421647 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalDParam_A
| 0 | 0 | 2147483647 | 4711886 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M
| 0 | 0 | 2147483647 | 26421647 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A
| 0 | 0 | 2147483647 | 4711886 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respOpcode_A
| 0 | 0 | 2147483647 | 4711886 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A
| 0 | 0 | 2147483647 | 4711886 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A
| 0 | 0 | 2147483647 | 2334 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A
| 0 | 0 | 2147483647 | 2606 | 0 | 0 |
|
tb.dut.tlul_assert_device.p_dbw.TlDbw_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.MaxFilters_A
| 0 | 0 | 35015949 | 34699489 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck00_A
| 0 | 0 | 35015949 | 9770034 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck01_A
| 0 | 0 | 35015949 | 2642662 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck10_A
| 0 | 0 | 35015949 | 3240794 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck11_A
| 0 | 0 | 35015949 | 19045999 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck00_A
| 0 | 0 | 35015949 | 12496696 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck01_A
| 0 | 0 | 35015949 | 1120464 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck10_A
| 0 | 0 | 35015949 | 1395605 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck11_A
| 0 | 0 | 35015949 | 19686724 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck00_A
| 0 | 0 | 35015949 | 12594841 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck01_A
| 0 | 0 | 35015949 | 748608 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck10_A
| 0 | 0 | 35015949 | 681337 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck11_A
| 0 | 0 | 35015949 | 20674703 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck00_A
| 0 | 0 | 35015949 | 11980706 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck01_A
| 0 | 0 | 35015949 | 239101 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck10_A
| 0 | 0 | 35015949 | 168449 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck11_A
| 0 | 0 | 35015949 | 22311233 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck00_A
| 0 | 0 | 35015949 | 13003561 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck01_A
| 0 | 0 | 35015949 | 13 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck10_A
| 0 | 0 | 35015949 | 37089 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck11_A
| 0 | 0 | 35015949 | 21658826 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck00_A
| 0 | 0 | 35015949 | 13009721 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck01_A
| 0 | 0 | 35015949 | 64621 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck10_A
| 0 | 0 | 35015949 | 69502 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck11_A
| 0 | 0 | 35015949 | 21555645 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck00_A
| 0 | 0 | 35015949 | 12809867 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck01_A
| 0 | 0 | 35015949 | 134055 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck10_A
| 0 | 0 | 35015949 | 33031 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck11_A
| 0 | 0 | 35015949 | 21722536 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck00_A
| 0 | 0 | 35015949 | 13367604 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck01_A
| 0 | 0 | 35015949 | 146326 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck10_A
| 0 | 0 | 35015949 | 99811 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck11_A
| 0 | 0 | 35015949 | 21085748 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.LpSampleCntCfg_M
| 0 | 0 | 32605803 | 32523633 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrMisMatch_A
| 0 | 0 | 32605803 | 170373 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrPwrDn_A
| 0 | 0 | 32605803 | 96061 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpSampleCntCfg_M
| 0 | 0 | 32605803 | 32523633 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.FsmDebugOut_A
| 0 | 0 | 32605803 | 32523633 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.FsmStateHwReset_A
| 0 | 0 | 1166 | 1166 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.FsmStateSwReset_A
| 0 | 0 | 32605803 | 6615 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.LpSampleCntHwReset_A
| 0 | 0 | 1166 | 1166 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.LpSampleCntSwReset_A
| 0 | 0 | 32605803 | 6615 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.NpSampleCntHwReset_A
| 0 | 0 | 1166 | 1166 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.NpSampleCntSwReset_A
| 0 | 0 | 32605803 | 6615 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.PwrupTimerCntHwReset_A
| 0 | 0 | 1166 | 1166 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.PwrupTimerCntSwReset_A
| 0 | 0 | 32605803 | 6615 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.WakeupTimerCntHwReset_A
| 0 | 0 | 1166 | 1166 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.WakeupTimerCntSwReset_A
| 0 | 0 | 32605803 | 6615 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.i_adc_ctrl_intr_o.IntrTKind_A
| 0 | 0 | 754 | 754 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 2147483647 | 17730 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.SyncReqAckHoldReq
| 0 | 0 | 35015949 | 17728 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_oneshot_done_sync.DstPulseCheck_A
| 0 | 0 | 2147483647 | 6799 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_oneshot_done_sync.SrcPulseCheck_M
| 0 | 0 | 35015949 | 6800 | 0 | 0 |
|
tb.dut.u_reg.en2addrHit
| 0 | 0 | 2147483647 | 2388605 | 0 | 0 |
|
tb.dut.u_reg.reAfterRv
| 0 | 0 | 2147483647 | 2388605 | 0 | 0 |
|
tb.dut.u_reg.rePulse
| 0 | 0 | 2147483647 | 2096756 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1896625 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2076 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2076 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 35095447 | 2076 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 1968 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2086 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1788585 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 1952 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 1952 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 35095447 | 1952 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 1846 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 1961 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1775601 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 1959 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 1959 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 35095447 | 1959 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 1853 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 1970 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1739579 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 1935 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 1935 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 35095447 | 1935 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 1830 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 1945 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1770305 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 1953 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 1953 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 35095447 | 1953 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 1847 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 1963 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1753948 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 1963 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 1963 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 35095447 | 1963 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 1856 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 1974 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1729191 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 1947 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 1947 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 35095447 | 1947 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 1841 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 1957 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1701306 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 1922 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 1922 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 35095447 | 1922 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 1816 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 1933 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1856329 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2076 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2076 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 35095447 | 2076 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 1970 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2088 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1710585 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 1945 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 1945 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 35095447 | 1945 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 1837 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 1955 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1701655 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 1924 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 1924 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 35095447 | 1924 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 1819 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 1935 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1770339 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 1992 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 1992 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 35095447 | 1992 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 1888 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2002 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1700412 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 1931 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 1931 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 35095447 | 1931 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 1827 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 1942 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1723398 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 1955 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 1955 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 35095447 | 1955 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 1849 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 1964 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1725036 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 1946 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 1946 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 35095447 | 1946 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 1839 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 1956 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1725275 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 1957 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 1957 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 35095447 | 1957 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 1850 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 1965 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_0_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_0_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A
| 0 | 0 | 35095447 | 649956 | 0 | 919 |
|
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 35095447 | 650125 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 2147483647 | 650129 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 35095447 | 649848 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_1_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_1_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A
| 0 | 0 | 35095447 | 634736 | 0 | 919 |
|
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 35095447 | 642766 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 2147483647 | 642769 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 35095447 | 632104 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 36104295 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 39176 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 39176 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 35095447 | 39195 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 39061 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 39236 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 18559035 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 20505 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 20505 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 35095447 | 20505 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 20400 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 20516 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 105976 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 90 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 35095447 | 3286875 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 2147483647 | 3287000 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 35095447 | 1710651 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 85 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 393 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 12916561 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 14630 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 14630 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 35095447 | 14631 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 14499 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 14675 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 16220437 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 18254 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 18254 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 35095447 | 18255 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 18144 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 18265 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 12956240 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 14588 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 14588 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 35095447 | 14589 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 14460 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 14635 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1232523 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 1430 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 1430 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 35095447 | 1430 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 1328 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 1441 | 0 | 0 |
|
tb.dut.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 64177583 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.DstReqKnown_A
| 0 | 0 | 35095447 | 34744878 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 68264 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A
| 0 | 0 | 35095447 | 15773 | 0 | 919 |
|
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 35095447 | 15836 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 2147483647 | 84100 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 35095447 | 83301 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 35095447 | 68159 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 68276 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.u_reg.wePulse
| 0 | 0 | 2147483647 | 291849 | 0 | 0 |
|