Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27131

1

T1

21

T2

11

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23179

1

T1

21

T2

11

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3952

1

T5

44

T8

11

T13

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20849

1

T2

11

T4

20

T6

20

auto[1]

6282

1

T1

21

T3

3

T5

59

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

21

T2

11

T3

3

auto[1]

4248

1

T5

21

T10

21

T12

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	2	1			T120	2		-	-		-	-
values[0]	49	1			T50	2		T141	13		T152	16
values[1]	619	1			T8	11		T13	12		T31	2
values[2]	720	1			T5	15		T11	5		T12	3
values[3]	837	1			T27	45		T32	21		T33	1
values[4]	693	1			T5	23		T13	3		T15	1
values[5]	2999	1			T1	21		T3	3		T10	23
values[6]	769	1			T5	21		T15	1		T31	1
values[7]	666	1			T8	3		T12	12		T17	11
values[8]	787	1			T32	50		T18	2		T132	17
values[9]	1364	1			T27	9		T19	3		T126	1
minimum	17626	1			T2	11		T4	20		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	722	1			T8	11		T12	3		T13	20
values[1]	816	1			T5	15		T11	5		T15	1
values[2]	847	1			T5	23		T15	1		T27	33
values[3]	3087	1			T1	21		T3	3		T10	23
values[4]	705	1			T15	1		T17	4		T36	5
values[5]	743	1			T5	21		T17	11		T31	1
values[6]	613	1			T8	3		T12	12		T127	23
values[7]	790	1			T32	50		T18	2		T126	1
values[8]	773	1			T19	3		T206	25		T131	17
values[9]	389	1			T27	9		T127	11		T131	3
minimum	17646	1			T2	11		T4	20		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

4327

1

T1

19

T5

35

T8

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T12	1		T13	2		T31	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T8	11		T31	1		T48	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	10		T11	5		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T15	1		T27	4		T32	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T27	15		T132	18		T49	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T5	19		T15	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1599	1			T1	21		T3	3		T10	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T13	1		T96	1		T97	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T15	1		T17	4		T36	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T206	9		T51	10		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T17	9		T20	2		T120	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T5	9		T31	1		T49	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T8	3		T12	3		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T127	12		T147	2		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T32	29		T126	1		T132	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T18	2		T148	4		T123	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T206	13		T21	5		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T19	3		T131	1		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T27	7		T131	1		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T127	3		T207	8		T174	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17478	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T208	20		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	2		T13	18		T118	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T48	2		T128	7		T50	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T5	5		T120	1		T125	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T27	8		T32	11		T49	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T27	18		T132	4		T49	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	4		T131	2		T50	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1033	1			T10	21		T28	6		T209	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	2		T96	4		T97	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T36	1		T207	7		T210	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T206	11		T51	6		T164	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T17	2		T20	1		T120	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T5	12		T49	11		T169	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T12	9		T133	7		T118	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T127	11		T130	9		T141	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T32	21		T132	10		T211	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T123	2		T164	10		T137	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T206	12		T21	1		T120	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T131	16		T118	15		T38	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T27	2		T131	2		T164	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T127	8		T207	9		T174	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	1		T18	2		T19	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T120	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T141	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T50	1		T152	9		T212	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	1		T31	1		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T8	11		T31	1		T213	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	10		T11	5		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T15	1		T48	15		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T27	15		T33	1		T132	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T27	4		T32	10		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T30	7		T36	4		T49	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T5	19		T13	1		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1553	1			T1	21		T3	3		T10	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T96	1		T206	9		T51	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T15	1		T120	13		T122	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T5	9		T31	1		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T8	3		T12	3		T17	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T127	12		T147	2		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T32	29		T132	7		T125	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T18	2		T148	4		T123	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	379	1			T27	7		T126	1		T206	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T19	3		T127	3		T131	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17478	1			T2	11		T4	20		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T120	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T141	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T50	1		T152	7		T212	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	11		T118	12		T120	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T169	10		T23	7		T75	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	5		T12	2		T13	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T48	2		T128	7		T49	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T27	18		T132	4		T125	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T27	8		T32	11		T50	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T36	1		T49	10		T210	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	4		T13	2		T97	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1016	1			T10	21		T28	6		T209	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T96	4		T206	11		T51	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T120	12		T122	6		T207	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	12		T169	1		T142	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	9		T17	2		T133	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T127	11		T130	9		T49	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T32	21		T132	10		T125	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T123	2		T141	2		T214	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T27	2		T206	12		T131	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	388	1			T127	8		T131	16		T118	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	1		T18	2		T19	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	3		T13	20		T31	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T8	1		T31	1		T48	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	6		T11	1		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T15	1		T27	9		T32	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T27	19		T132	5		T49	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T5	5		T15	1		T131	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T1	2		T3	3		T10	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T13	3		T96	5		T97	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T15	1		T17	4		T36	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T206	12		T51	7		T164	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T17	7		T20	3		T120	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T5	13		T31	1		T49	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T8	1		T12	10		T133	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T127	12		T147	2		T130	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T32	23		T126	1		T132	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T18	2		T148	1		T123	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T206	13		T21	5		T120	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T19	3		T131	17		T118	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T27	3		T131	3		T164	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T127	9		T207	10		T174	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17626	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T208	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T215	9		T216	2		T178	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T8	10		T48	14		T169	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	9		T11	4		T125	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T27	3		T32	9		T49	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T27	14		T132	17		T49	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T5	18		T50	11		T51	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1257	1			T1	19		T40	26		T30	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T121	2		T217	7		T215	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T36	1		T37	1		T207	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T206	8		T51	9		T142	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T17	4		T120	12		T122	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T5	8		T49	9		T218	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T8	2		T12	2		T219	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T127	11		T149	7		T220	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T32	27		T132	6		T211	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T148	3		T123	11		T137	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T206	12		T21	1		T125	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T38	2		T123	7		T214	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T27	6		T143	2		T221	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T127	2		T207	7		T174	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T208	19		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T120	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T141	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T50	2		T152	8		T212	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	12		T31	1		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T8	1		T31	1		T213	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	6		T11	1		T12	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T15	1		T48	3		T128	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T27	19		T33	1		T132	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T27	9		T32	12		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T30	1		T36	4		T49	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	5		T13	3		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T1	2		T3	3		T10	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T96	5		T206	12		T51	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T15	1		T120	13		T122	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T5	13		T31	1		T169	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T8	1		T12	10		T17	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T127	12		T147	2		T130	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T32	23		T132	11		T125	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T18	2		T148	1		T123	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T27	3		T126	1		T206	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	447	1			T19	3		T127	9		T131	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17626	1			T2	11		T4	20		T6	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T152	8		T212	5		T222	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T215	9		T178	9		T223	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	10		T169	10		T183	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T5	9		T11	4		T216	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T48	14		T49	12		T224	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T27	14		T132	17		T125	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T27	3		T32	9		T50	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T30	6		T36	1		T49	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T5	18		T51	2		T121	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1202	1			T1	19		T40	26		T129	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T206	8		T51	9		T22	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T120	12		T122	5		T207	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T5	8		T142	14		T218	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T8	2		T12	2		T17	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T127	11		T49	9		T218	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T32	27		T132	6		T125	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T148	3		T123	11		T214	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T27	6		T206	12		T21	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T127	2		T38	2		T123	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

auto[0]

4327

1

T1

19

T5

35

T8

12

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27131

1

T1

21

T2

11

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23508

1

T1

21

T2

11

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3623

1

T5

21

T8

11

T13

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20625

1

T2

11

T4

20

T5

36

auto[1]

6506

1

T1

21

T3

3

T5

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

21

T2

11

T3

3

auto[1]

4248

1

T5

21

T10

21

T12

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	6	1			T210	3		T225	1		T226	2
values[0]	54	1			T31	1		T150	6		T227	1
values[1]	652	1			T13	12		T15	1		T96	5
values[2]	824	1			T5	15		T15	1		T32	15
values[3]	576	1			T8	11		T31	1		T36	5
values[4]	863	1			T17	11		T30	7		T51	16
values[5]	846	1			T12	12		T13	8		T27	33
values[6]	740	1			T12	3		T97	12		T33	1
values[7]	782	1			T8	3		T206	25		T147	1
values[8]	3011	1			T1	21		T3	3		T10	23
values[9]	1151	1			T5	44		T15	1		T17	4
minimum	17626	1			T2	11		T4	20		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	831	1			T13	12		T15	2		T96	5
values[1]	837	1			T5	15		T31	1		T32	15
values[2]	687	1			T8	11		T36	5		T206	20
values[3]	839	1			T17	11		T27	33		T30	7
values[4]	777	1			T12	12		T13	8		T32	35
values[5]	691	1			T12	3		T97	12		T33	1
values[6]	3163	1			T1	21		T3	3		T8	3
values[7]	621	1			T5	21		T11	5		T15	1
values[8]	843	1			T5	23		T17	4		T27	21
values[9]	190	1			T31	1		T131	3		T49	26
minimum	17652	1			T2	11		T4	20		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

4327

1

T1

19

T5

35

T8

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T96	1		T158	1		T169	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	1		T15	2		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T5	10		T19	3		T127	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T31	1		T32	9		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T206	9		T37	3		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T8	11		T36	4		T123	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T27	15		T30	7		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T17	9		T134	1		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	3		T126	1		T164	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T13	1		T32	20		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	1		T97	1		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T121	3		T174	12		T215	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1671	1			T1	21		T3	3		T8	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T118	1		T132	7		T49	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	5		T18	2		T48	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	9		T15	1		T132	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T5	19		T17	4		T32	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T27	11		T127	3		T20	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T131	1		T49	13		T229	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T31	1		T124	1		T225	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17479	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T49	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T96	4		T169	1		T22	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	11		T130	9		T118	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	5		T127	11		T118	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T32	6		T131	16		T121	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T206	11		T51	6		T123	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T36	1		T123	21		T140	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T27	18		T128	7		T38	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T17	2		T228	14		T218	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T12	9		T164	12		T143	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T13	7		T32	15		T130	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T12	2		T97	11		T120	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T121	14		T174	10		T215	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1049	1			T10	21		T13	2		T28	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T118	15		T132	10		T49	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T48	2		T50	1		T21	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T5	12		T132	4		T120	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	4		T32	11		T133	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T27	10		T127	8		T20	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T131	2		T49	13		T229	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T230	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	1		T18	2		T19	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T49	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T210	1		T226	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T225	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T226	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T31	1		T150	6		T227	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T96	1		T158	1		T124	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	1		T15	1		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T5	10		T19	3		T127	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T15	1		T32	9		T121	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T206	9		T119	1		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	11		T31	1		T36	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T30	7		T51	10		T125	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T17	9		T170	1		T172	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T12	3		T27	15		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	1		T32	20		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	1		T97	1		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T119	1		T121	3		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T8	3		T206	13		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T118	1		T132	7		T125	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1647	1			T1	21		T3	3		T10	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T132	18		T49	10		T213	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	353	1			T5	19		T17	4		T32	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T5	9		T15	1		T27	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17478	1			T2	11		T4	20		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T210	2		T226	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T226	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T231	8		T232	4		T233	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T96	4		T169	1		T22	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T13	11		T130	9		T118	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	5		T127	11		T118	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T32	6		T121	14		T123	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T206	11		T35	2		T229	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T36	1		T131	16		T123	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T51	6		T125	6		T164	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T17	2		T172	12		T218	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	9		T27	18		T128	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T13	7		T32	15		T130	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	2		T97	11		T120	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T121	14		T215	4		T234	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T206	12		T224	14		T220	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T118	15		T132	10		T125	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T10	21		T13	2		T28	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T132	4		T49	11		T120	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T5	4		T32	11		T133	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	12		T27	10		T127	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	1		T18	2		T19	1