Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27131

1

T1

21

T2

11

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23200

1

T1

21

T2

11

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3931

1

T5

44

T8

11

T13

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20828

1

T2

11

T4

20

T6

20

auto[1]

6303

1

T1

21

T3

3

T5

59

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

21

T2

11

T3

3

auto[1]

4248

1

T5

21

T10

21

T12

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	327	1			T38	8		T164	13		T141	12
values[0]	23	1			T50	2		T141	13		T302	1
values[1]	668	1			T8	11		T13	12		T31	2
values[2]	679	1			T5	15		T11	5		T12	3
values[3]	906	1			T15	1		T27	33		T32	21
values[4]	653	1			T5	23		T13	3		T97	12
values[5]	3056	1			T1	21		T3	3		T10	23
values[6]	734	1			T5	21		T31	1		T20	3
values[7]	644	1			T8	3		T12	12		T17	11
values[8]	728	1			T32	50		T18	2		T132	17
values[9]	1087	1			T27	9		T19	3		T126	1
minimum	17626	1			T2	11		T4	20		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	612	1			T8	11		T12	3		T13	20
values[1]	782	1			T5	15		T11	5		T15	1
values[2]	815	1			T5	23		T15	1		T27	33
values[3]	3134	1			T1	21		T3	3		T10	23
values[4]	652	1			T15	1		T17	4		T206	20
values[5]	746	1			T5	21		T17	11		T31	1
values[6]	593	1			T8	3		T12	12		T127	23
values[7]	841	1			T32	50		T18	2		T126	1
values[8]	929	1			T27	9		T19	3		T127	11
values[9]	221	1			T164	13		T175	1		T152	30
minimum	17806	1			T2	11		T4	20		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

4327

1

T1

19

T5

35

T8

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T13	2		T31	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T8	11		T31	1		T48	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	10		T11	5		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T15	1		T27	4		T32	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T27	15		T49	12		T253	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T5	19		T15	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1628	1			T1	21		T3	3		T10	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T13	1		T96	1		T97	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	1		T17	4		T37	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T206	9		T51	10		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T17	9		T20	2		T122	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T5	9		T31	1		T49	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T8	3		T12	3		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T127	12		T147	2		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T32	29		T126	1		T132	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T18	2		T148	4		T123	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T27	7		T206	13		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T19	3		T127	3		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T164	1		T175	1		T221	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T152	14		T309	1		T275	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17522	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T50	1		T152	9		T310	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T12	2		T13	18		T118	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T48	2		T128	7		T49	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T5	5		T120	1		T125	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T27	8		T32	11		T224	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T27	18		T49	10		T214	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	4		T131	2		T50	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T10	21		T28	6		T36	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T13	2		T96	4		T97	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T120	12		T207	7		T210	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T206	11		T51	6		T164	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T17	2		T20	1		T122	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T5	12		T49	11		T169	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	9		T133	7		T118	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T127	11		T130	9		T149	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T32	21		T132	10		T211	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T123	2		T164	10		T141	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T27	2		T206	12		T131	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T127	8		T131	16		T118	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T164	12		T311	11		T312	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T152	16		T309	10		T275	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	1		T18	2		T19	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T50	1		T152	7		T310	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T164	1		T175	1		T227	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T38	4		T141	1		T267	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T141	1		T302	1		T154	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T50	1		T222	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	1		T31	1		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T8	11		T31	1		T213	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	10		T11	5		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T15	1		T27	4		T48	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T27	15		T33	1		T132	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T15	1		T32	10		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T30	7		T36	4		T49	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T5	19		T13	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1554	1			T1	21		T3	3		T10	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T96	1		T206	9		T51	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T20	2		T120	13		T122	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T5	9		T31	1		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T8	3		T12	3		T17	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T127	12		T147	2		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T32	29		T132	7		T125	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T18	2		T148	4		T123	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T27	7		T126	1		T206	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T19	3		T127	3		T131	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17478	1			T2	11		T4	20		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T164	12		T313	10		T261	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T38	4		T141	11		T73	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T141	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T50	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T13	11		T118	12		T140	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T169	10		T23	7		T75	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	5		T12	2		T13	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T27	8		T48	2		T128	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T27	18		T132	4		T125	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T32	11		T50	4		T121	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T36	1		T49	10		T269	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	4		T13	2		T97	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1037	1			T10	21		T28	6		T209	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T96	4		T206	11		T51	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T20	1		T120	12		T122	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	12		T169	1		T218	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	9		T17	2		T133	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T127	11		T130	9		T49	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T32	21		T132	10		T125	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T123	2		T141	2		T137	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T27	2		T206	12		T131	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T127	8		T131	16		T118	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	1		T18	2		T19	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	3		T13	20		T31	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T8	1		T31	1		T48	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	6		T11	1		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T15	1		T27	9		T32	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T27	19		T49	11		T253	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T5	5		T15	1		T131	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1385	1			T1	2		T3	3		T10	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T13	3		T96	5		T97	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T15	1		T17	4		T37	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T206	12		T51	7		T164	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T17	7		T20	3		T122	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T5	13		T31	1		T49	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T8	1		T12	10		T133	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T127	12		T147	2		T130	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T32	23		T126	1		T132	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T18	2		T148	1		T123	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T27	3		T206	13		T131	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T19	3		T127	9		T131	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T164	13		T175	1		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T152	17		T309	11		T275	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17675	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T50	2		T152	8		T310	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T215	9		T178	9		T223	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T8	10		T48	14		T49	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	9		T11	4		T125	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T27	3		T32	9		T224	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T27	14		T49	11		T214	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	18		T50	11		T51	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T1	19		T40	26		T30	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T121	2		T217	7		T215	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T37	1		T120	12		T207	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T206	8		T51	9		T142	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T17	4		T122	5		T216	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T5	8		T49	9		T218	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T8	2		T12	2		T218	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T127	11		T149	7		T252	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T32	27		T132	6		T211	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T148	3		T123	11		T137	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T27	6		T206	12		T21	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T127	2		T38	2		T123	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T221	7		T311	19		T312	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T152	13		T275	14		T300	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T165	12		T155	15		T314	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T152	8		T310	13		T292	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T164	13		T175	1		T227	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T38	6		T141	12		T267	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T141	13		T302	1		T154	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T50	2		T222	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	12		T31	1		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T8	1		T31	1		T213	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	6		T11	1		T12	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T15	1		T27	9		T48	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T27	19		T33	1		T132	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T15	1		T32	12		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T30	1		T36	4		T49	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	5		T13	3		T97	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T1	2		T3	3		T10	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T96	5		T206	12		T51	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T20	3		T120	13		T122	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	13		T31	1		T169	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T8	1		T12	10		T17	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T127	12		T147	2		T130	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T32	23		T132	11		T125	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T18	2		T148	1		T123	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T27	3		T126	1		T206	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T19	3		T127	9		T131	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17626	1			T2	11		T4	20		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T26	1		T315	8		T313	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T38	2		T73	13		T152	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T222	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T215	9		T178	9		T223	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T8	10		T169	10		T183	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T5	9		T11	4		T216	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T27	3		T48	14		T49	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T27	14		T132	17		T125	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T32	9		T50	11		T121	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T30	6		T36	1		T49	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	18		T51	2		T121	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1200	1			T1	19		T40	26		T129	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T206	8		T51	9		T142	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T120	12		T122	5		T207	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T5	8		T218	3		T135	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T8	2		T12	2		T17	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T127	11		T49	9		T218	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T32	27		T132	6		T125	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T148	3		T123	11		T137	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T27	6		T206	12		T21	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T127	2		T123	7		T207	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

auto[0]

4327

1

T1

19

T5

35

T8

12