Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27131

1

T1

21

T2

11

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23243

1

T1

21

T2

11

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3888

1

T8

11

T11

5

T12

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20909

1

T2

11

T4

20

T6

20

auto[1]

6222

1

T1

21

T3

3

T5

59

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

21

T2

11

T3

3

auto[1]

4248

1

T5

21

T10

21

T12

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	60	1			T250	9		T319	18		T322	9
values[0]	128	1			T32	21		T150	10		T178	7
values[1]	684	1			T13	15		T97	12		T27	12
values[2]	3062	1			T1	21		T3	3		T10	23
values[3]	746	1			T15	1		T30	7		T31	1
values[4]	678	1			T5	21		T11	5		T31	1
values[5]	630	1			T5	15		T15	1		T27	42
values[6]	780	1			T12	3		T96	5		T131	17
values[7]	743	1			T126	1		T128	8		T21	6
values[8]	706	1			T5	23		T17	11		T31	1
values[9]	1288	1			T8	14		T15	1		T18	2
minimum	17626	1			T2	11		T4	20		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	939	1			T13	12		T27	12		T32	21
values[1]	3095	1			T1	21		T3	3		T10	23
values[2]	655	1			T11	5		T30	7		T33	1
values[3]	818	1			T5	21		T27	33		T31	1
values[4]	538	1			T5	15		T15	1		T27	9
values[5]	842	1			T12	3		T96	5		T126	1
values[6]	630	1			T19	3		T128	8		T133	8
values[7]	700	1			T5	23		T31	1		T126	1
values[8]	969	1			T8	3		T15	1		T17	11
values[9]	291	1			T8	11		T51	9		T122	12
minimum	17654	1			T2	11		T4	20		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

4327

1

T1

19

T5

35

T8

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T213	1		T225	1		T218	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T13	1		T27	4		T32	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1647	1			T1	21		T3	3		T10	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	3		T15	1		T32	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T30	7		T33	1		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	5		T119	1		T120	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	9		T130	1		T37	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T27	15		T31	1		T118	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T5	10		T140	1		T224	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T15	1		T27	7		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T126	1		T131	1		T38	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T12	1		T96	1		T119	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T19	3		T128	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T120	1		T210	1		T253	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T5	19		T31	1		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T206	9		T158	1		T148	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T8	3		T17	9		T18	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T15	1		T36	4		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T122	6		T282	1		T248	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T8	11		T51	3		T150	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17478	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T97	1		T73	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T218	15		T184	6		T216	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	11		T27	8		T32	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1037	1			T10	21		T13	9		T28	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	9		T32	15		T127	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T207	9		T164	10		T215	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T120	12		T141	2		T137	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	12		T130	9		T125	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T27	18		T118	15		T49	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T5	5		T140	1		T224	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T27	2		T118	12		T132	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T131	16		T38	4		T121	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	2		T96	4		T169	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T128	7		T133	7		T21	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T120	1		T210	11		T253	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	4		T130	11		T49	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T206	11		T220	2		T265	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T17	2		T211	10		T218	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T36	1		T131	2		T172	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T122	6		T282	9		T248	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T51	6		T282	15		T258	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	1		T18	2		T19	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T97	11		T73	8		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T322	3		T323	16		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T250	1		T319	14		T91	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T150	10		T178	7		T223	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T32	10		T293	14		T324	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	1		T127	3		T225	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	1		T97	1		T27	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1645	1			T1	21		T3	3		T10	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	3		T127	12		T118	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T30	7		T31	1		T32	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T15	1		T206	13		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	9		T128	1		T37	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	5		T31	1		T118	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T5	10		T126	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T15	1		T27	22		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T131	1		T38	4		T51	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T12	1		T96	1		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T126	1		T128	1		T21	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T210	1		T169	11		T253	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T5	19		T17	9		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T206	9		T158	1		T148	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	353	1			T8	3		T18	2		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	399	1			T8	11		T15	1		T36	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17478	1			T2	11		T4	20		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T322	6		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T250	8		T319	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T245	9		T325	3		T261	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T32	11		T324	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	2		T127	8		T218	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	11		T97	11		T27	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T10	21		T13	7		T28	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	9		T127	11		T118	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T32	6		T131	2		T207	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T206	12		T49	11		T120	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	12		T164	10		T141	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T118	15		T50	4		T35	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T5	5		T130	9		T140	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T27	20		T118	12		T132	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T131	16		T38	4		T51	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	2		T96	4		T123	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T128	7		T21	1		T164	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T210	11		T169	10		T253	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	4		T17	2		T133	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T206	11		T120	1		T220	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T130	11		T211	10		T122	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T36	1		T131	2		T51	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	1		T18	2		T19	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T213	1		T225	1		T218	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T13	12		T27	9		T32	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1389	1			T1	2		T3	3		T10	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T12	10		T15	1		T32	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T30	1		T33	1		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	1		T119	1		T120	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	13		T130	10		T37	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T27	19		T31	1		T118	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T5	6		T140	2		T224	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T15	1		T27	3		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T126	1		T131	17		T38	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T12	3		T96	5		T119	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T19	3		T128	8		T133	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T120	2		T210	12		T253	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	5		T31	1		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T206	12		T158	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T8	1		T17	7		T18	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T15	1		T36	4		T131	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T122	7		T282	10		T248	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T8	1		T51	7		T150	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17626	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T97	12		T73	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T218	3		T184	2		T216	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T27	3		T32	9		T48	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T1	19		T40	26		T32	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	2		T32	19		T127	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T30	6		T207	7		T215	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	4		T120	12		T137	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T5	8		T37	1		T125	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T27	14		T49	9		T50	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T5	9		T224	10		T239	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T27	6		T132	6		T123	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T38	2		T121	14		T125	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T169	10		T171	6		T220	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T21	1		T51	9		T217	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T253	1		T235	10		T216	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	18		T49	12		T123	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T206	8		T148	3		T220	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T8	2		T17	4		T211	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T36	1		T214	12		T149	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T122	5		T248	12		T326	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T8	10		T51	2		T150	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T73	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T322	9		T323	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T250	9		T319	5		T91	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T150	1		T178	1		T223	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T32	12		T293	1		T324	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	3		T127	9		T225	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T13	12		T97	12		T27	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T1	2		T3	3		T10	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T12	10		T127	12		T118	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T30	1		T31	1		T32	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T15	1		T206	13		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	13		T128	1		T37	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T11	1		T31	1		T118	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T5	6		T126	1		T130	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T15	1		T27	22		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T131	17		T38	6		T51	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	3		T96	5		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T126	1		T128	8		T21	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T210	12		T169	11		T253	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T5	5		T17	7		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T206	12		T158	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T8	1		T18	2		T130	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T8	1		T15	1		T36	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17626	1			T2	11		T4	20		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T323	15		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T319	13		T91	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T150	9		T178	6		T223	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T32	9		T293	13		T324	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T127	2		T218	3		T184	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T27	3		T32	19		T48	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T1	19		T40	26		T129	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	2		T127	11		T132	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T30	6		T32	8		T207	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T206	12		T49	9		T120	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T5	8		T37	1		T217	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T11	4		T50	11		T148	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T5	9		T125	15		T224	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T27	20		T132	6		T193	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T38	2		T51	9		T121	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T123	11		T125	11		T171	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T21	1		T217	6		T214	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T169	10		T253	1		T235	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	18		T17	4		T49	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T206	8		T148	3		T220	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T8	2		T211	10		T122	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T8	10		T36	1		T51	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

auto[0]

4327

1

T1

19

T5

35

T8

12