Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27131

1

T1

21

T2

11

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23605

1

T1

21

T2

11

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3526

1

T8

14

T12

15

T13

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20171

1

T2

11

T4

20

T5

21

auto[1]

6960

1

T1

21

T3

3

T5

38

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

21

T2

11

T3

3

auto[1]

4248

1

T5

21

T10

21

T12

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	878	1			T7	2		T18	20		T34	1
values[0]	65	1			T193	30		T266	1		T75	1
values[1]	711	1			T5	23		T12	12		T13	3
values[2]	3140	1			T1	21		T3	3		T5	21
values[3]	699	1			T31	1		T32	35		T211	21
values[4]	751	1			T5	15		T15	1		T32	21
values[5]	711	1			T8	11		T13	12		T27	33
values[6]	642	1			T27	12		T127	23		T128	1
values[7]	684	1			T11	5		T13	8		T27	9
values[8]	721	1			T15	2		T96	5		T97	12
values[9]	995	1			T8	3		T17	15		T31	1
minimum	17134	1			T2	11		T4	20		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	713	1			T5	23		T13	3		T32	15
values[1]	3210	1			T1	21		T3	3		T5	21
values[2]	818	1			T5	15		T31	1		T32	21
values[3]	695	1			T15	1		T48	17		T127	11
values[4]	647	1			T8	11		T13	12		T27	33
values[5]	721	1			T11	5		T27	12		T127	23
values[6]	588	1			T13	8		T27	9		T18	2
values[7]	776	1			T8	3		T15	2		T96	5
values[8]	974	1			T17	4		T31	1		T33	1
values[9]	194	1			T124	1		T225	1		T220	21
minimum	17795	1			T2	11		T4	20		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

4327

1

T1

19

T5

35

T8

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	19		T126	1		T131	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	1		T32	9		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1671	1			T1	21		T3	3		T5	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T12	1		T31	1		T19	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T5	10		T32	10		T211	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T31	1		T121	15		T124	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T15	1		T127	3		T206	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T48	15		T36	4		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	1		T30	7		T207	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T8	11		T27	15		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	5		T127	12		T38	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T27	4		T133	1		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	1		T27	7		T18	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T130	1		T21	5		T267	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T15	1		T97	1		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T8	3		T15	1		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T118	1		T132	25		T49	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T17	4		T31	1		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T124	1		T220	8		T136	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T225	1		T320	20		T155	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17545	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T12	3		T193	14		T149	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	4		T131	18		T118	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	2		T32	6		T121	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1078	1			T5	12		T10	21		T28	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T12	2		T123	13		T282	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	5		T32	11		T211	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T121	14		T141	12		T215	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T127	8		T206	11		T130	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T48	2		T36	1		T50	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	11		T207	7		T142	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T27	18		T118	13		T50	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T127	11		T38	4		T120	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T27	8		T133	7		T131	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	7		T27	2		T164	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T130	9		T21	1		T184	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T97	11		T49	13		T125	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T96	4		T17	2		T206	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T118	12		T132	14		T49	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T128	7		T120	1		T174	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T220	13		T264	16		T143	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T320	4		T155	16		T82	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	1		T18	2		T19	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T12	9		T193	16		T149	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	598	1			T7	2		T18	20		T34	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T217	8		T170	1		T241	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T266	1		T75	1		T165	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T193	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T5	19		T131	2		T118	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T12	3		T13	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1606	1			T1	21		T3	3		T5	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T12	1		T31	1		T32	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T32	20		T211	11		T122	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T31	1		T121	15		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T5	10		T15	1		T32	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T48	15		T36	4		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T13	1		T30	7		T207	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T8	11		T27	15		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T127	12		T38	4		T228	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T27	4		T128	1		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T11	5		T13	1		T27	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T21	5		T141	1		T252	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T15	1		T97	1		T18	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T15	1		T96	1		T206	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T118	1		T132	25		T37	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T8	3		T17	13		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16986	1			T2	11		T4	20		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T49	11		T220	13		T300	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T328	11		T329	12		T320	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T268	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T193	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	4		T131	18		T118	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T12	9		T13	2		T121	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1040	1			T5	12		T10	21		T28	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	2		T32	6		T123	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T32	15		T211	10		T122	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T121	14		T215	4		T136	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	5		T32	11		T127	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T48	2		T36	1		T50	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	11		T207	7		T142	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T27	18		T118	13		T140	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T127	11		T38	4		T228	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T27	8		T133	7		T130	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	7		T27	2		T120	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T21	1		T141	2		T258	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T97	11		T49	13		T125	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T96	4		T206	12		T51	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T118	12		T132	14		T35	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T17	2		T128	7		T120	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	1		T18	2		T19	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T5	5		T126	1		T131	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	3		T32	7		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1435	1			T1	2		T3	3		T5	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T12	3		T31	1		T19	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	6		T32	12		T211	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T31	1		T121	15		T124	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T15	1		T127	9		T206	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T48	3		T36	4		T50	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	12		T30	1		T207	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T8	1		T27	19		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	1		T127	12		T38	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T27	9		T133	8		T131	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	8		T27	3		T18	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T130	10		T21	5		T267	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T15	1		T97	12		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T8	1		T15	1		T96	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T118	13		T132	16		T49	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T17	4		T31	1		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T124	1		T220	14		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T225	1		T320	5		T155	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17670	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T12	10		T193	17		T149	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	18		T49	11		T51	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T32	8		T148	9		T121	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T1	19		T5	8		T40	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T123	12		T282	14		T284	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	9		T32	9		T211	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T121	14		T215	9		T136	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T127	2		T206	8		T148	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T48	14		T36	1		T235	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T30	6		T207	11		T142	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T8	10		T27	14		T50	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	4		T127	11		T38	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T27	3		T169	10		T149	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T27	6		T253	1		T220	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T21	1		T184	14		T252	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T49	12		T125	9		T189	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T8	2		T17	4		T206	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T132	23		T49	9		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T217	7		T174	11		T214	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T220	7		T136	13		T264	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T320	19		T155	15		T82	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T171	6		T178	9		T165	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T12	2		T193	13		T149	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	610	1			T7	2		T18	20		T34	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T217	1		T170	1		T241	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T266	1		T75	1		T165	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T193	17		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T5	5		T131	20		T118	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	10		T13	3		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1385	1			T1	2		T3	3		T5	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T12	3		T31	1		T32	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T32	16		T211	11		T122	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T31	1		T121	15		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	6		T15	1		T32	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T48	3		T36	4		T50	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	12		T30	1		T207	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T8	1		T27	19		T118	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T127	12		T38	6		T228	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T27	9		T128	1		T133	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T11	1		T13	8		T27	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T21	5		T141	3		T252	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T15	1		T97	12		T18	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T15	1		T96	5		T206	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T118	13		T132	16		T37	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T8	1		T17	11		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17134	1			T2	11		T4	20		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T49	9		T220	7		T136	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T217	7		T328	9		T329	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T165	12		T254	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T193	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	18		T51	9		T123	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T12	2		T148	9		T121	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T1	19		T5	8		T40	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T32	8		T123	12		T135	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T32	19		T211	10		T122	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T121	14		T215	9		T136	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	9		T32	9		T127	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T48	14		T36	1		T216	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T30	6		T207	11		T142	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T8	10		T27	14		T215	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T127	11		T38	2		T183	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T27	3		T50	11		T169	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T11	4		T27	6		T120	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T21	1		T252	11		T258	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T49	12		T125	9		T253	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T206	12		T51	2		T22	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T132	23		T37	1		T218	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T8	2		T17	4		T174	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

auto[0]

4327

1

T1

19

T5

35

T8

12