Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27131

1

T1

21

T2

11

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23392

1

T1

21

T2

11

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3739

1

T5

21

T8

11

T13

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20658

1

T2

11

T4

20

T5

36

auto[1]

6473

1

T1

21

T3

3

T5

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

21

T2

11

T3

3

auto[1]

4248

1

T5

21

T10

21

T12

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	244	1			T17	4		T131	3		T49	26
values[0]	18	1			T126	1		T22	5		T227	1
values[1]	662	1			T13	12		T15	1		T96	5
values[2]	826	1			T5	15		T15	1		T32	15
values[3]	633	1			T8	11		T31	1		T36	5
values[4]	849	1			T17	11		T30	7		T51	16
values[5]	792	1			T12	12		T13	8		T27	33
values[6]	787	1			T12	3		T97	12		T33	1
values[7]	735	1			T8	3		T13	3		T206	25
values[8]	3063	1			T1	21		T3	3		T10	23
values[9]	896	1			T5	44		T15	1		T27	21
minimum	17626	1			T2	11		T4	20		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	662	1			T13	12		T15	1		T96	5
values[1]	851	1			T5	15		T8	11		T32	15
values[2]	651	1			T31	1		T36	5		T206	20
values[3]	890	1			T17	11		T27	33		T30	7
values[4]	787	1			T12	12		T13	8		T32	35
values[5]	669	1			T12	3		T97	12		T33	1
values[6]	3130	1			T1	21		T3	3		T8	3
values[7]	697	1			T5	21		T11	5		T15	1
values[8]	854	1			T5	23		T17	4		T27	9
values[9]	137	1			T27	12		T131	3		T49	26
minimum	17803	1			T2	11		T4	20		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

4327

1

T1

19

T5

35

T8

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T96	1		T19	3		T158	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	1		T15	1		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T5	10		T127	12		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T8	11		T32	9		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T206	9		T119	1		T51	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T31	1		T36	4		T123	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T27	15		T128	1		T38	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T17	9		T30	7		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	3		T164	1		T235	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T13	1		T32	20		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T97	1		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T148	10		T121	3		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1671	1			T1	21		T3	3		T8	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T118	1		T132	7		T49	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	5		T18	2		T48	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T5	9		T15	1		T132	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T5	19		T17	4		T32	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T27	7		T31	1		T127	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T131	1		T49	13		T119	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T27	4		T225	1		T330	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17509	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T15	1		T126	1		T49	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T96	4		T169	1		T184	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T13	11		T130	9		T118	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	5		T127	11		T118	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T32	6		T131	16		T121	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T206	11		T51	6		T123	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T36	1		T123	13		T140	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T27	18		T128	7		T38	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T17	2		T218	5		T260	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T12	9		T164	12		T143	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T13	7		T32	15		T130	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T12	2		T97	11		T120	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T121	14		T164	10		T174	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T10	21		T13	2		T28	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T118	15		T132	10		T49	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T48	2		T131	2		T50	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	12		T132	4		T120	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	4		T32	11		T133	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T27	2		T127	8		T20	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T131	2		T49	13		T236	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T27	8		T268	16		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	1		T18	2		T19	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T49	10		T231	8		T239	18

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T17	4		T131	1		T49	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T124	1		T252	12		T310	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T22	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T126	1		T227	1		T232	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T96	1		T158	1		T169	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	1		T15	1		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T5	10		T19	3		T127	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T15	1		T32	9		T121	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T206	9		T119	1		T123	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T8	11		T31	1		T36	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T51	10		T125	10		T217	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T17	9		T30	7		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	3		T27	15		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	1		T32	20		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	1		T97	1		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T119	1		T148	10		T121	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	3		T13	1		T206	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T118	1		T132	7		T125	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1660	1			T1	21		T3	3		T10	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T132	18		T49	10		T213	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T5	19		T32	10		T18	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T5	9		T15	1		T27	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17478	1			T2	11		T4	20		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T131	2		T49	13		T207	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T310	4		T295	21		T331	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T22	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T232	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T96	4		T169	1		T184	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	11		T130	9		T118	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	5		T127	11		T118	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T32	6		T121	14		T123	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T206	11		T123	2		T35	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T36	1		T131	16		T123	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T51	6		T125	6		T253	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T17	2		T218	5		T260	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	9		T27	18		T128	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	7		T32	15		T130	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	2		T97	11		T120	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T121	14		T164	10		T174	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T13	2		T206	12		T220	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T118	15		T132	10		T125	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1030	1			T10	21		T28	6		T48	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T132	4		T49	11		T120	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	4		T32	11		T133	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	12		T27	10		T127	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	1		T18	2		T19	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T96	5		T19	3		T158	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T13	12		T15	1		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T5	6		T127	12		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T8	1		T32	7		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T206	12		T119	1		T51	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T31	1		T36	4		T123	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T27	19		T128	8		T38	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T17	7		T30	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	10		T164	13		T235	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T13	8		T32	16		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	3		T97	12		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T148	1		T121	15		T164	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1393	1			T1	2		T3	3		T8	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T118	16		T132	11		T49	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	1		T18	2		T48	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	13		T15	1		T132	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	5		T17	4		T32	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T27	3		T31	1		T127	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T131	3		T49	14		T119	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T27	9		T225	1		T330	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17658	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T15	1		T126	1		T49	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T184	2		T75	11		T223	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T211	10		T122	5		T135	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T5	9		T127	11		T37	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T8	10		T32	8		T121	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T206	8		T51	9		T123	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T36	1		T123	12		T171	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T27	14		T38	2		T217	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T17	4		T30	6		T218	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	2		T235	10		T136	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T32	19		T218	9		T234	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T184	14		T25	3		T152	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T148	9		T121	2		T174	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T1	19		T8	2		T40	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T132	6		T49	9		T125	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	4		T48	14		T21	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	8		T132	17		T120	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	18		T32	9		T207	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T27	6		T127	2		T23	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T49	12		T236	13		T240	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T27	3		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T22	1		T321	5		T273	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T49	11		T219	2		T231	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T17	4		T131	3		T49	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T124	1		T252	1		T310	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T22	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T126	1		T227	1		T232	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T96	5		T158	1		T169	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T13	12		T15	1		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T5	6		T19	3		T127	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T15	1		T32	7		T121	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T206	12		T119	1		T123	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	1		T31	1		T36	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T51	7		T125	7		T217	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T17	7		T30	1		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	10		T27	19		T128	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T13	8		T32	16		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	3		T97	12		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T119	1		T148	1		T121	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T8	1		T13	3		T206	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T118	16		T132	11		T125	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T1	2		T3	3		T10	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T132	5		T49	12		T213	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T5	5		T32	12		T18	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T5	13		T15	1		T27	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17626	1			T2	11		T4	20		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T49	12		T207	11		T78	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T252	11		T310	4		T295	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T22	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T232	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T184	2		T75	11		T223	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T49	11		T211	10		T122	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	9		T127	11		T37	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T32	8		T121	14		T123	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T206	8		T123	11		T149	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T8	10		T36	1		T123	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T51	9		T125	9		T217	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T17	4		T30	6		T218	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	2		T27	14		T38	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T32	19		T218	9		T216	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T184	14		T143	12		T25	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T148	9		T121	2		T174	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T8	2		T206	12		T214	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T132	6		T125	11		T224	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T1	19		T11	4		T40	26
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T132	17		T49	9		T120	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T5	18		T32	9		T253	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	8		T27	9		T127	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

auto[0]

4327

1

T1

19

T5

35

T8

12