Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27131

1

T1

21

T2

11

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23241

1

T1

21

T2

11

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3890

1

T8

11

T11

5

T12

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20977

1

T2

11

T4

20

T6

20

auto[1]

6154

1

T1

21

T3

3

T5

59

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

21

T2

11

T3

3

auto[1]

4248

1

T5

21

T10

21

T12

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	283	1			T131	3		T211	21		T172	13
values[0]	49	1			T223	12		T332	8		T245	10
values[1]	727	1			T13	12		T97	12		T27	12
values[2]	3086	1			T1	21		T3	3		T10	23
values[3]	674	1			T15	1		T30	7		T31	1
values[4]	866	1			T5	21		T11	5		T31	1
values[5]	547	1			T5	15		T15	1		T27	42
values[6]	790	1			T12	3		T96	5		T126	1
values[7]	697	1			T128	8		T21	6		T51	16
values[8]	686	1			T5	23		T31	1		T19	3
values[9]	1100	1			T8	14		T15	1		T17	11
minimum	17626	1			T2	11		T4	20		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	673	1			T13	12		T32	21		T48	17
values[1]	3062	1			T1	21		T3	3		T10	23
values[2]	704	1			T11	5		T15	1		T30	7
values[3]	789	1			T5	21		T27	33		T31	1
values[4]	554	1			T5	15		T15	1		T27	9
values[5]	885	1			T12	3		T96	5		T126	1
values[6]	550	1			T19	3		T128	8		T133	8
values[7]	758	1			T5	23		T31	1		T18	2
values[8]	1048	1			T8	14		T15	1		T17	11
values[9]	171	1			T282	10		T151	1		T258	18
minimum	17937	1			T2	11		T4	20		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

4327

1

T1

19

T5

35

T8

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T127	3		T218	4		T267	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	1		T32	10		T48	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1616	1			T1	21		T3	3		T10	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	3		T32	20		T127	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T30	7		T33	1		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	5		T15	1		T206	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	9		T130	1		T37	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T27	15		T31	1		T118	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T5	10		T38	4		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T15	1		T27	7		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T126	1		T131	1		T121	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	1		T96	1		T119	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T19	3		T128	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T120	1		T210	1		T253	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T5	19		T31	1		T18	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T206	9		T158	1		T148	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T8	3		T17	9		T211	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T8	11		T15	1		T36	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T282	1		T302	1		T248	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T151	1		T258	9		T270	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17570	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T97	1		T27	4		T174	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T127	8		T218	15		T184	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	11		T32	11		T48	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1024	1			T10	21		T13	9		T28	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T12	9		T32	15		T127	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T207	16		T164	10		T215	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T206	12		T49	11		T120	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	12		T130	9		T125	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T27	18		T118	15		T50	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T5	5		T38	4		T140	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T27	2		T118	12		T132	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T131	16		T121	14		T125	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	2		T96	4		T169	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T128	7		T133	7		T21	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T120	1		T210	11		T253	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T5	4		T130	11		T49	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T206	11		T220	2		T310	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T17	2		T211	10		T122	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T36	1		T131	2		T51	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T282	9		T302	11		T248	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T258	9		T270	3		T243	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	1		T18	2		T19	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T97	11		T27	8		T174	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T211	11		T249	16		T223	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T131	1		T172	1		T149	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T223	12		T332	8		T245	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T324	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T127	3		T225	1		T218	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	1		T97	1		T27	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1616	1			T1	21		T3	3		T10	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T12	3		T32	20		T127	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T30	7		T31	1		T32	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T15	1		T206	13		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	9		T128	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T11	5		T31	1		T118	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T5	10		T140	1		T224	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T15	1		T27	22		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T126	1		T131	1		T38	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T12	1		T96	1		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T128	1		T21	5		T51	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T210	1		T169	11		T253	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T5	19		T31	1		T19	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T206	9		T158	1		T148	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T8	3		T17	9		T18	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T8	11		T15	1		T36	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17478	1			T2	11		T4	20		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T211	10		T286	6		T322	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T131	2		T172	12		T259	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T245	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T324	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T127	8		T218	15		T184	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	11		T97	11		T27	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1006	1			T10	21		T13	9		T28	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	9		T32	15		T127	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T32	6		T207	9		T145	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T206	12		T120	12		T210	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	12		T130	9		T125	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T118	15		T49	11		T50	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T5	5		T140	1		T224	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T27	20		T118	12		T132	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T131	16		T38	4		T121	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	2		T96	4		T123	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T128	7		T21	1		T51	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T210	11		T169	10		T253	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	4		T133	7		T49	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T206	11		T120	1		T220	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T17	2		T130	11		T122	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T36	1		T51	6		T220	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	1		T18	2		T19	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T127	9		T218	16		T267	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	12		T32	12		T48	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T1	2		T3	3		T10	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T12	10		T32	16		T127	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T30	1		T33	1		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	1		T15	1		T206	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T5	13		T130	10		T37	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T27	19		T31	1		T118	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	6		T38	6		T140	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T15	1		T27	3		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T126	1		T131	17		T121	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T12	3		T96	5		T119	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T19	3		T128	8		T133	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T120	2		T210	12		T253	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T5	5		T31	1		T18	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T206	12		T158	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T8	1		T17	7		T211	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T8	1		T15	1		T36	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T282	10		T302	12		T248	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T151	1		T258	10		T270	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17693	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T97	12		T27	9		T174	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T127	2		T218	3		T183	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T32	9		T48	14		T132	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T1	19		T40	26		T32	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	2		T32	19		T127	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T30	6		T207	18		T217	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	4		T206	12		T49	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T5	8		T37	1		T125	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T27	14		T50	11		T148	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T5	9		T38	2		T224	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T27	6		T132	6		T123	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T121	14		T125	9		T231	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T169	10		T171	6		T220	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T21	1		T51	9		T217	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T253	1		T235	10		T216	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	18		T49	12		T123	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T206	8		T148	3		T220	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T8	2		T17	4		T211	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T8	10		T36	1		T51	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T248	12		T326	8		T222	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T258	8		T270	3		T333	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T178	6		T223	11		T332	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T27	3		T174	11		T143	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T211	11		T249	1		T223	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T131	3		T172	13		T149	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T223	1		T332	1		T245	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T324	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T127	9		T225	1		T218	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T13	12		T97	12		T27	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1363	1			T1	2		T3	3		T10	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T12	10		T32	16		T127	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T30	1		T31	1		T32	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T15	1		T206	13		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	13		T128	1		T130	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T11	1		T31	1		T118	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T5	6		T140	2		T224	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T15	1		T27	22		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T126	1		T131	17		T38	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T12	3		T96	5		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T128	8		T21	5		T51	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T210	12		T169	11		T253	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T5	5		T31	1		T19	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T206	12		T158	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T8	1		T17	7		T18	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T8	1		T15	1		T36	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17626	1			T2	11		T4	20		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T211	10		T249	15		T223	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T149	10		T150	5		T73	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T223	11		T332	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T324	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T127	2		T218	3		T183	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T27	3		T32	9		T48	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1259	1			T1	19		T40	26		T129	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	2		T32	19		T127	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T30	6		T32	8		T207	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T206	12		T120	12		T214	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	8		T37	1		T125	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T11	4		T49	9		T50	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T5	9		T224	10		T239	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T27	20		T132	6		T142	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T38	2		T121	14		T125	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T123	11		T125	11		T171	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T21	1		T51	9		T217	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T169	10		T253	1		T235	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	18		T49	12		T123	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T206	8		T148	3		T220	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T8	2		T17	4		T122	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T8	10		T36	1		T51	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

auto[0]

4327

1

T1

19

T5

35

T8

12