Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T96	5		T158	1		T169	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T13	12		T15	2		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T5	6		T19	3		T127	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T31	1		T32	7		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T206	12		T37	2		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T8	1		T36	4		T123	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T27	19		T30	1		T128	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T17	7		T134	1		T228	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	10		T126	1		T164	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T13	8		T32	16		T130	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T12	3		T97	12		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T121	15		T174	11		T215	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1405	1			T1	2		T3	3		T8	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T118	16		T132	11		T49	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	1		T18	2		T48	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T5	13		T15	1		T132	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	5		T17	4		T32	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T27	12		T127	9		T20	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T131	3		T49	14		T229	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T31	1		T124	1		T225	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17630	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T49	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T22	1		T184	2		T137	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T211	10		T122	5		T135	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T5	9		T127	11		T50	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T32	8		T121	14		T125	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T206	8		T37	1		T51	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T8	10		T36	1		T123	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T27	14		T30	6		T38	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T17	4		T218	3		T196	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	2		T235	10		T136	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T32	19		T218	9		T234	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T148	9		T184	14		T152	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T121	2		T174	11		T215	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T1	19		T8	2		T40	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T132	6		T49	9		T125	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	4		T48	14		T21	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	8		T132	17		T207	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	18		T32	9		T207	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T27	9		T127	2		T120	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T49	12		T78	4		T236	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T237	2		T238	17		T230	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T49	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T210	3		T226	2		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T225	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T226	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T31	1		T150	1		T227	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T96	5		T158	1		T124	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	12		T15	1		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T5	6		T19	3		T127	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T15	1		T32	7		T121	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T206	12		T119	1		T35	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	1		T31	1		T36	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T30	1		T51	7		T125	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T17	7		T170	1		T172	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	10		T27	19		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T13	8		T32	16		T130	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T12	3		T97	12		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T119	1		T121	15		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T8	1		T206	13		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T118	16		T132	11		T125	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T1	2		T3	3		T10	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T132	5		T49	12		T213	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T5	5		T17	4		T32	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T5	13		T15	1		T27	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17626	1			T2	11		T4	20		T6	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T150	5		T231	10		T232	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T22	1		T184	2		T75	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T49	11		T211	10		T122	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	9		T127	11		T37	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T32	8		T121	14		T123	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T206	8		T149	10		T239	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T8	10		T36	1		T123	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T30	6		T51	9		T125	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T17	4		T218	3		T189	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	2		T27	14		T38	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T32	19		T218	9		T216	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T148	9		T184	14		T143	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T121	2		T215	9		T234	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T8	2		T206	12		T224	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T132	6		T125	11		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1298	1			T1	19		T11	4		T40	26
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T132	17		T49	9		T120	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T5	18		T32	9		T49	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T5	8		T27	9		T127	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

auto[0]

4327

1

T1

19

T5

35

T8

12