Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27131

1

T1

21

T2

11

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23601

1

T1

21

T2

11

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3530

1

T5

44

T8

11

T11

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20963

1

T2

11

T4

20

T6

20

auto[1]

6168

1

T1

21

T3

3

T5

59

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

21

T2

11

T3

3

auto[1]

4248

1

T5

21

T10

21

T12

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	354	1			T32	21		T131	3		T118	14
values[0]	10	1			T240	10		-	-		-	-
values[1]	801	1			T97	12		T31	1		T147	1
values[2]	834	1			T15	2		T31	1		T32	15
values[3]	747	1			T5	21		T96	5		T18	2
values[4]	647	1			T8	3		T17	11		T36	5
values[5]	2951	1			T1	21		T3	3		T5	15
values[6]	722	1			T5	23		T8	11		T12	3
values[7]	813	1			T17	4		T30	7		T32	35
values[8]	684	1			T27	33		T33	1		T19	3
values[9]	942	1			T11	5		T12	12		T13	20
minimum	17626	1			T2	11		T4	20		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	802	1			T15	1		T97	12		T31	1
values[1]	763	1			T15	1		T31	1		T32	15
values[2]	745	1			T5	21		T96	5		T17	11
values[3]	3033	1			T1	21		T3	3		T8	3
values[4]	544	1			T5	38		T133	8		T131	3
values[5]	764	1			T8	11		T12	3		T13	3
values[6]	881	1			T17	4		T30	7		T32	35
values[7]	640	1			T12	12		T27	33		T33	1
values[8]	983	1			T11	5		T13	20		T27	21
values[9]	130	1			T32	21		T131	3		T241	1
minimum	17846	1			T2	11		T4	20		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

4327

1

T1

19

T5

35

T8

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T97	1		T147	1		T121	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T15	1		T31	1		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T15	1		T131	1		T50	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T31	1		T32	9		T206	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T96	1		T17	9		T18	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T5	9		T127	12		T206	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1667	1			T1	21		T3	3		T8	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T36	4		T125	12		T22	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	10		T131	1		T118	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	19		T133	1		T38	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T13	1		T15	1		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T8	11		T12	1		T20	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T17	4		T19	3		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T30	7		T32	20		T132	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	3		T27	15		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T37	3		T51	10		T148	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T27	11		T126	1		T49	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T11	5		T13	2		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T241	1		T165	4		T242	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T32	10		T131	1		T151	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17514	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T232	17		T243	1		T155	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T97	11		T121	14		T169	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T130	11		T132	4		T120	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T131	16		T50	4		T120	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T32	6		T206	11		T122	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T96	4		T17	2		T127	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	12		T127	11		T206	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1067	1			T10	21		T28	6		T209	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T36	1		T125	14		T22	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T5	5		T131	2		T118	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T5	4		T133	7		T38	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T13	2		T48	2		T128	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	2		T20	1		T35	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T49	24		T123	13		T224	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T32	15		T132	10		T164	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	9		T27	18		T211	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T51	6		T142	14		T244	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T27	10		T49	10		T50	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T13	18		T118	13		T21	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T245	9		T246	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T32	11		T131	2		T247	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	1		T18	2		T19	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T232	10		T155	12		T248	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T50	1		T234	9		T249	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T32	10		T131	1		T118	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T240	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T97	1		T147	1		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T31	1		T130	1		T132	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T15	1		T131	1		T50	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T15	1		T31	1		T32	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T96	1		T18	2		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T5	9		T127	12		T206	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T8	3		T17	9		T51	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T36	4		T193	1		T22	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1612	1			T1	21		T3	3		T5	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T133	1		T38	4		T124	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T13	1		T15	1		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	19		T8	11		T12	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T17	4		T128	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T30	7		T32	20		T20	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T27	15		T33	1		T19	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T141	1		T142	15		T22	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T12	3		T27	11		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T11	5		T13	2		T37	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17478	1			T2	11		T4	20		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T50	1		T234	8		T250	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T32	11		T131	2		T118	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T240	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T97	11		T130	9		T121	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T130	11		T132	4		T120	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T131	16		T50	4		T120	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T32	6		T206	11		T229	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T96	4		T127	8		T118	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	12		T127	11		T206	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T17	2		T51	6		T141	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T36	1		T22	1		T220	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1024	1			T5	5		T10	21		T28	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T133	7		T38	4		T125	29
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	2		T48	2		T120	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T5	4		T12	2		T35	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T128	7		T49	11		T123	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T32	15		T20	1		T132	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T27	18		T49	13		T211	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T141	12		T142	14		T137	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	9		T27	10		T49	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	18		T51	6		T207	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	1		T18	2		T19	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T97	12		T147	1		T121	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T15	1		T31	1		T130	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T15	1		T131	17		T50	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T31	1		T32	7		T206	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T96	5		T17	7		T18	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T5	13		T127	12		T206	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1420	1			T1	2		T3	3		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T36	4		T125	15		T22	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	6		T131	3		T118	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T5	5		T133	8		T38	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	3		T15	1		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T8	1		T12	3		T20	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T17	4		T19	3		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T30	1		T32	16		T132	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T12	10		T27	19		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T37	2		T51	7		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T27	12		T126	1		T49	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T11	1		T13	20		T118	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T241	1		T165	1		T242	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T32	12		T131	3		T151	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17680	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T232	11		T243	1		T155	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T121	2		T169	10		T218	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T132	17		T120	12		T207	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T50	11		T214	1		T149	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T32	8		T206	8		T122	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T17	4		T127	2		T251	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T5	8		T127	11		T206	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T1	19		T8	2		T40	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T36	1		T125	11		T22	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	9		T252	13		T232	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	18		T38	2		T125	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T48	14		T215	11		T183	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	10		T253	1		T214	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T49	21		T148	3		T123	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T30	6		T32	19		T132	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	2		T27	14		T211	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T37	1		T51	9		T148	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T27	9		T49	11		T234	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T11	4		T21	1		T121	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T165	3		T246	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T32	9		T247	6		T254	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T255	2		T256	2		T257	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T232	16		T155	14		T248	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T50	2		T234	9		T249	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T32	12		T131	3		T118	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T240	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T97	12		T147	1		T130	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T31	1		T130	12		T132	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T15	1		T131	17		T50	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T15	1		T31	1		T32	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T96	5		T18	2		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T5	13		T127	12		T206	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T8	1		T17	7		T51	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T36	4		T193	1		T22	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T1	2		T3	3		T5	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T133	8		T38	6		T124	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T13	3		T15	1		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T5	5		T8	1		T12	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T17	4		T128	8		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T30	1		T32	16		T20	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T27	19		T33	1		T19	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T141	13		T142	15		T22	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	10		T27	12		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T11	1		T13	20		T37	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17626	1			T2	11		T4	20		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T234	8		T249	15		T256	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T32	9		T21	1		T121	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T240	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T121	2		T218	3		T234	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T132	17		T120	12		T207	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T50	11		T169	10		T214	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T32	8		T206	8		T258	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T127	2		T150	5		T251	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	8		T127	11		T206	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	2		T17	4		T51	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T36	1		T22	1		T220	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T1	19		T5	9		T40	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T38	2		T125	26		T218	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T48	14		T215	11		T216	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	18		T8	10		T253	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T49	9		T148	3		T123	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T30	6		T32	19		T132	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T27	14		T49	12		T211	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T142	14		T137	15		T236	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	2		T27	9		T49	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T11	4		T37	1		T51	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

auto[0]

4327

1

T1

19

T5

35

T8

12