Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27131

1

T1

21

T2

11

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21274

1

T2

11

T4

20

T5

23

auto[ADC_CTRL_FILTER_COND_OUT]

5857

1

T1

21

T3

3

T5

36

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21195

1

T2

11

T4

20

T5

59

auto[1]

5936

1

T1

21

T3

3

T10

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

21

T2

11

T3

3

auto[1]

4248

1

T5

21

T10

21

T12

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	221	1			T12	3		T206	20		T118	13
values[0]	10	1			T232	10		-	-		-	-
values[1]	785	1			T13	12		T15	1		T31	1
values[2]	770	1			T13	8		T17	11		T27	33
values[3]	597	1			T97	12		T31	1		T18	2
values[4]	738	1			T5	15		T13	3		T96	5
values[5]	788	1			T5	23		T12	12		T15	1
values[6]	802	1			T8	3		T15	1		T17	4
values[7]	679	1			T128	9		T147	1		T131	17
values[8]	762	1			T8	11		T11	5		T30	7
values[9]	3353	1			T1	21		T3	3		T5	21
minimum	17626	1			T2	11		T4	20		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	679	1			T13	12		T17	11		T19	3
values[1]	3189	1			T1	21		T3	3		T10	23
values[2]	612	1			T5	15		T97	12		T27	12
values[3]	805	1			T5	23		T13	3		T15	1
values[4]	571	1			T8	3		T12	12		T31	1
values[5]	919	1			T15	1		T17	4		T27	9
values[6]	754	1			T128	1		T206	25		T147	1
values[7]	741	1			T8	11		T11	5		T30	7
values[8]	870	1			T5	21		T12	3		T206	20
values[9]	133	1			T118	13		T121	17		T225	1
minimum	17858	1			T2	11		T4	20		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

4327

1

T1

19

T5

35

T8

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T19	3		T21	5		T120	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T13	1		T17	9		T50	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T32	20		T123	21		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1594	1			T1	21		T3	3		T10	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T27	4		T18	2		T49	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	10		T97	1		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T5	19		T13	1		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T32	10		T49	12		T51	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	3		T12	3		T48	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T31	1		T218	10		T234	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T17	4		T27	7		T127	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T15	1		T128	1		T148	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T206	13		T147	1		T20	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T128	1		T119	1		T148	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T11	5		T30	7		T36	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T8	11		T127	3		T132	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T12	1		T206	9		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T5	9		T131	1		T49	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T118	1		T121	3		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T259	1		T189	1		T77	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17525	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T15	1		T31	1		T125	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T21	1		T120	1		T218	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	11		T17	2		T50	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T32	15		T123	21		T140	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1087	1			T10	21		T13	7		T27	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T27	8		T49	11		T122	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	5		T97	11		T35	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	4		T13	2		T96	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T32	11		T49	10		T51	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T12	9		T48	2		T132	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T218	9		T234	8		T143	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T27	2		T127	11		T51	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T128	7		T121	14		T215	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T206	12		T20	1		T131	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T120	12		T141	11		T174	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T36	1		T125	6		T207	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T127	8		T132	10		T210	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T12	2		T206	11		T130	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	12		T131	2		T49	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T118	12		T121	14		T137	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T259	10		T189	1		T257	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	1		T18	2		T19	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T125	15		T77	1		T226	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T12	1		T206	9		T118	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T49	13		T229	1		T247	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T232	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T21	5		T207	8		T218	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T13	1		T15	1		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T32	20		T19	3		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	1		T17	9		T27	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T18	2		T122	6		T123	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T97	1		T31	1		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T13	1		T96	1		T27	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	10		T32	10		T49	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	19		T12	3		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T31	1		T169	11		T253	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T8	3		T17	4		T27	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T15	1		T119	1		T121	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T147	1		T131	1		T118	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T128	2		T148	14		T120	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T11	5		T30	7		T206	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T8	11		T127	3		T132	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T36	4		T130	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1721	1			T1	21		T3	3		T5	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17478	1			T2	11		T4	20		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T12	2		T206	11		T118	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T49	13		T247	17		T257	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T232	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T21	1		T207	9		T218	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T13	11		T50	4		T125	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T32	15		T120	1		T123	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	7		T17	2		T27	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T122	6		T123	13		T169	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T97	11		T35	2		T260	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	2		T96	4		T27	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	5		T32	11		T49	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T5	4		T12	9		T48	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T169	10		T253	3		T218	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T27	2		T127	11		T164	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T121	14		T174	10		T215	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T131	16		T118	15		T51	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T128	7		T120	12		T141	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T206	12		T20	1		T125	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T127	8		T132	10		T210	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T36	1		T130	9		T131	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1071	1			T5	12		T10	21		T28	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	1		T18	2		T19	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T19	3		T21	5		T120	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	12		T17	7		T50	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T32	16		T123	23		T140	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1427	1			T1	2		T3	3		T10	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T27	9		T18	2		T49	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	6		T97	12		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T5	5		T13	3		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T32	12		T49	11		T51	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T8	1		T12	10		T48	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T31	1		T218	10		T234	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T17	4		T27	3		T127	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T15	1		T128	8		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T206	13		T147	1		T20	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T128	1		T119	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	1		T30	1		T36	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T8	1		T127	9		T132	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T12	3		T206	12		T130	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	13		T131	3		T49	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T118	13		T121	15		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T259	11		T189	2		T77	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17685	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T15	1		T31	1		T125	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T21	1		T218	3		T143	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T17	4		T50	11		T150	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T32	19		T123	19		T125	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1254	1			T1	19		T40	26		T27	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T27	3		T49	9		T122	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T5	9		T215	11		T184	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	18		T142	14		T149	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T32	9		T49	11		T51	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T8	2		T12	2		T48	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T218	9		T234	8		T235	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T27	6		T127	11		T37	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T148	3		T121	14		T217	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T206	12		T123	11		T214	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T148	9		T120	12		T174	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T11	4		T30	6		T36	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T8	10		T127	2		T132	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T206	8		T217	7		T183	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	8		T49	12		T38	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T121	2		T137	4		T236	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T257	12		T261	16		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T207	7		T262	11		T263	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T125	15		T77	1		T178	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T12	3		T206	12		T118	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T49	14		T229	1		T247	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T232	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T21	5		T207	10		T218	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T13	12		T15	1		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T32	16		T19	3		T120	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T13	8		T17	7		T27	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T18	2		T122	7		T123	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T97	12		T31	1		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T13	3		T96	5		T27	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	6		T32	12		T49	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	5		T12	10		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T31	1		T169	11		T253	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T8	1		T17	4		T27	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T15	1		T119	1		T121	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T147	1		T131	17		T118	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T128	9		T148	2		T120	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T11	1		T30	1		T206	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T8	1		T127	9		T132	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T36	4		T130	10		T131	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1434	1			T1	2		T3	3		T5	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17626	1			T2	11		T4	20		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T206	8		T137	4		T189	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T49	12		T247	12		T257	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T232	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T21	1		T207	7		T218	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T50	11		T125	15		T150	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T32	19		T123	7		T125	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T17	4		T27	14		T32	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T122	5		T123	12		T216	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T184	2		T264	12		T265	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T27	3		T49	9		T142	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T5	9		T32	9		T49	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	18		T12	2		T48	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T169	10		T253	1		T218	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T8	2		T27	6		T127	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T121	14		T174	11		T215	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T51	9		T123	11		T214	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T148	12		T120	12		T217	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	4		T30	6		T206	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T8	10		T127	2		T132	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T36	1		T121	2		T207	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1358	1			T1	19		T5	8		T40	26

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

auto[0]

4327

1

T1

19

T5

35

T8

12