Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27131

1

T1

21

T2

11

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23482

1

T1

21

T2

11

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3649

1

T8

3

T12

12

T13

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20204

1

T2

11

T4

20

T5

21

auto[1]

6927

1

T1

21

T3

3

T5

38

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

21

T2

11

T3

3

auto[1]

4248

1

T5

21

T10

21

T12

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	537	1			T7	2		T18	20		T34	1
values[0]	36	1			T234	17		T266	1		T75	1
values[1]	718	1			T5	23		T12	12		T13	3
values[2]	3153	1			T1	21		T3	3		T5	21
values[3]	744	1			T31	1		T32	56		T148	4
values[4]	756	1			T5	15		T15	1		T48	17
values[5]	739	1			T8	11		T13	12		T27	33
values[6]	561	1			T27	12		T127	23		T128	1
values[7]	699	1			T11	5		T13	8		T27	9
values[8]	743	1			T15	2		T96	5		T97	12
values[9]	1311	1			T8	3		T17	4		T31	1
minimum	17134	1			T2	11		T4	20		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	902	1			T5	23		T12	12		T13	3
values[1]	3167	1			T1	21		T3	3		T5	21
values[2]	826	1			T5	15		T31	1		T32	21
values[3]	688	1			T15	1		T48	17		T127	11
values[4]	646	1			T8	11		T13	12		T27	33
values[5]	732	1			T11	5		T27	12		T127	23
values[6]	655	1			T13	8		T27	9		T18	2
values[7]	707	1			T8	3		T15	2		T96	5
values[8]	882	1			T17	4		T31	1		T33	1
values[9]	293	1			T128	8		T147	1		T124	1
minimum	17633	1			T2	11		T4	20		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

4327

1

T1

19

T5

35

T8

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T5	19		T126	1		T131	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	3		T13	1		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1643	1			T1	21		T3	3		T5	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T32	9		T19	3		T213	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T5	10		T31	1		T32	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T124	1		T210	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T15	1		T127	3		T206	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T48	15		T36	4		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T8	11		T13	1		T30	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T27	15		T128	1		T118	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T11	5		T127	12		T38	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T27	4		T133	1		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	1		T27	7		T18	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T21	5		T267	1		T184	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T15	1		T96	1		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T8	3		T15	1		T97	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T17	4		T118	1		T132	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T31	1		T33	1		T37	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T124	1		T220	8		T143	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T128	1		T147	1		T225	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17479	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T187	1		T268	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	4		T131	18		T118	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T12	9		T13	2		T49	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1072	1			T5	12		T10	21		T12	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T32	6		T123	13		T215	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	5		T32	11		T211	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T210	11		T141	12		T73	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T127	8		T206	11		T20	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T48	2		T36	1		T130	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T13	11		T207	7		T172	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T27	18		T118	13		T50	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T127	11		T38	4		T169	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T27	8		T133	7		T130	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	7		T27	2		T125	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T21	1		T184	14		T25	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T96	4		T132	10		T49	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T97	11		T17	2		T206	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T118	12		T132	4		T49	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T269	8		T143	4		T229	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T220	13		T143	12		T270	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T128	7		T218	9		T264	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	1		T18	2		T19	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T268	3		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	510	1			T7	2		T18	20		T34	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T214	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T266	1		T75	1		T271	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T234	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T5	19		T131	2		T118	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	3		T13	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1627	1			T1	21		T3	3		T5	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T32	9		T19	3		T49	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T31	1		T32	30		T211	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T148	4		T170	1		T253	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T5	10		T15	1		T127	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T48	15		T130	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T8	11		T13	1		T30	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T27	15		T36	4		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T127	12		T38	4		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T27	4		T128	1		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	5		T13	1		T27	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T130	1		T21	5		T120	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	1		T96	1		T18	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T15	1		T97	1		T17	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T17	4		T118	1		T132	25
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	382	1			T8	3		T31	1		T33	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16986	1			T2	11		T4	20		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T272	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T234	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	4		T131	18		T118	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	9		T13	2		T121	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1081	1			T5	12		T10	21		T12	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T32	6		T49	10		T123	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T32	26		T211	10		T121	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T215	4		T136	19		T265	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	5		T127	8		T206	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T48	2		T130	11		T140	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	11		T207	7		T172	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T27	18		T36	1		T118	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T127	11		T38	4		T164	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T27	8		T133	7		T131	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	7		T27	2		T164	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T130	9		T21	1		T120	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T96	4		T49	13		T51	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T97	11		T17	2		T206	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T118	12		T132	14		T49	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T128	7		T218	9		T269	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	1		T18	2		T19	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T5	5		T126	1		T131	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T12	10		T13	3		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1432	1			T1	2		T3	3		T5	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T32	7		T19	3		T213	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	6		T31	1		T32	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T124	1		T210	12		T141	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T15	1		T127	9		T206	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T48	3		T36	4		T130	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T8	1		T13	12		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T27	19		T128	1		T118	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	1		T127	12		T38	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T27	9		T133	8		T130	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	8		T27	3		T18	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T21	5		T267	1		T184	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T15	1		T96	5		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T8	1		T15	1		T97	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T17	4		T118	13		T132	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T31	1		T33	1		T37	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T124	1		T220	14		T143	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T128	8		T147	1		T225	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17628	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T187	1		T268	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T5	18		T51	9		T123	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	2		T49	11		T148	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T1	19		T5	8		T40	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T32	8		T123	12		T215	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T5	9		T32	9		T211	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T150	5		T73	7		T265	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T127	2		T206	8		T123	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T48	14		T36	1		T148	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T8	10		T30	6		T207	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T27	14		T50	11		T215	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T11	4		T127	11		T38	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T27	3		T120	12		T149	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T27	6		T125	9		T253	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T21	1		T184	14		T150	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T132	6		T49	12		T51	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T8	2		T17	4		T206	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T132	17		T49	9		T217	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T37	1		T143	2		T262	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T220	7		T143	12		T270	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T218	9		T214	12		T136	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	508	1			T7	2		T18	20		T34	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T214	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T266	1		T75	1		T271	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T234	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	5		T131	20		T118	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	10		T13	3		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1431	1			T1	2		T3	3		T5	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T32	7		T19	3		T49	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T31	1		T32	28		T211	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T148	1		T170	1		T253	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T5	6		T15	1		T127	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T48	3		T130	12		T140	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	1		T13	12		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T27	19		T36	4		T118	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T127	12		T38	6		T164	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T27	9		T128	1		T133	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	1		T13	8		T27	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T130	10		T21	5		T120	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T15	1		T96	5		T18	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T15	1		T97	12		T17	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T17	4		T118	13		T132	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	394	1			T8	1		T31	1		T33	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17134	1			T2	11		T4	20		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T272	11		T273	5		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T214	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T254	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T234	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	18		T51	9		T123	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	2		T148	9		T121	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T1	19		T5	8		T40	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T32	8		T49	11		T123	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T32	28		T211	10		T121	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T148	3		T215	9		T136	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	9		T127	2		T206	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T48	14		T216	2		T223	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T8	10		T30	6		T207	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T27	14		T36	1		T215	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T127	11		T38	2		T183	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T27	3		T50	11		T149	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	4		T27	6		T169	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T21	1		T120	12		T252	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T49	12		T51	2		T125	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T17	4		T206	12		T22	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T132	23		T49	9		T217	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T8	2		T37	1		T218	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

auto[0]

4327

1

T1

19

T5

35

T8

12