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Summary for Variable clk_gate_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for clk_gate_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 27131 1 T1 21 T2 11 T3 3



Summary for Variable cond_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cond_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[ADC_CTRL_FILTER_COND_IN] 23213 1 T1 21 T2 11 T3 3
auto[ADC_CTRL_FILTER_COND_OUT] 3918 1 T5 21 T8 11 T12 15



Summary for Variable en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 20896 1 T2 11 T4 20 T5 38
auto[1] 6235 1 T1 21 T3 3 T5 21



Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22883 1 T1 21 T2 11 T3 3
auto[1] 4248 1 T5 21 T10 21 T12 12



Summary for Variable max_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for max_v_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
maximum 201 1 T19 3 T158 1 T213 1
values[0] 17 1 T118 13 T165 4 - -
values[1] 772 1 T8 3 T11 5 T15 1
values[2] 593 1 T8 11 T12 12 T18 2
values[3] 733 1 T5 44 T96 5 T17 15
values[4] 3150 1 T1 21 T3 3 T10 23
values[5] 752 1 T13 11 T30 7 T128 9
values[6] 743 1 T15 1 T32 35 T48 17
values[7] 676 1 T15 1 T131 6 T132 17
values[8] 880 1 T5 15 T12 3 T31 2
values[9] 988 1 T13 12 T97 12 T32 15
minimum 17626 1 T2 11 T4 20 T6 20



Summary for Variable min_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 1 11 91.67


User Defined Bins for min_v_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
maximum 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 651 1 T8 11 T11 5 T15 1
values[1] 636 1 T12 12 T17 4 T18 2
values[2] 740 1 T5 44 T96 5 T17 11
values[3] 3225 1 T1 21 T3 3 T10 23
values[4] 728 1 T15 1 T30 7 T32 35
values[5] 650 1 T13 8 T15 1 T126 1
values[6] 809 1 T12 3 T31 1 T48 17
values[7] 891 1 T5 15 T13 12 T31 1
values[8] 763 1 T97 12 T32 15 T33 1
values[9] 159 1 T122 12 T123 16 T207 17
minimum 17879 1 T2 11 T4 20 T6 20



Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22804 1 T1 2 T2 11 T3 3
auto[1] 4327 1 T1 19 T5 35 T8 12



Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] * -- -- 4


Covered bins
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 159 1 T11 5 T15 1 T27 4
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 208 1 T8 11 T27 15 T32 10
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 187 1 T17 4 T147 1 T130 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 182 1 T12 3 T18 2 T132 18
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 152 1 T5 19 T96 1 T17 9
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 254 1 T5 9 T36 4 T49 13
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1644 1 T1 21 T3 3 T10 2
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 262 1 T27 7 T118 1 T125 16
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 144 1 T15 1 T128 1 T133 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 237 1 T30 7 T32 20 T128 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 221 1 T126 1 T20 2 T50 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 141 1 T13 1 T15 1 T172 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 211 1 T48 15 T131 1 T132 7
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 228 1 T12 1 T31 1 T127 3
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 260 1 T5 10 T31 1 T206 22
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 241 1 T13 1 T127 12 T118 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 211 1 T49 10 T213 1 T169 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 234 1 T97 1 T32 9 T33 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 8 1 T122 6 T274 1 T246 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 88 1 T123 8 T207 8 T225 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 17535 1 T2 11 T4 20 T6 20
auto[0] minimum auto[ADC_CTRL_FILTER_COND_OUT] 76 1 T260 1 T232 6 T165 4
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 89 1 T27 8 T118 12 T149 8
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 195 1 T27 18 T32 11 T140 1
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 150 1 T130 9 T49 10 T218 9
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 117 1 T12 9 T132 4 T121 14
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 133 1 T5 4 T96 4 T17 2
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 201 1 T5 12 T36 1 T49 13
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1045 1 T10 21 T13 2 T28 6
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 274 1 T27 2 T118 15 T125 15
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 164 1 T128 7 T133 7 T51 6
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 183 1 T32 15 T131 16 T210 11
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 172 1 T20 1 T50 1 T164 10
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 116 1 T13 7 T172 12 T135 9
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 196 1 T48 2 T131 2 T132 10
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 174 1 T12 2 T127 8 T131 2
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 208 1 T5 5 T206 23 T121 14
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 182 1 T13 11 T127 11 T118 13
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 115 1 T49 11 T169 1 T216 2
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 203 1 T97 11 T32 6 T125 14
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 6 1 T122 6 - - - -
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 57 1 T123 8 T207 9 T275 16
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 203 1 T12 1 T18 2 T19 1
auto[1] minimum auto[ADC_CTRL_FILTER_COND_OUT] 65 1 T260 10 T232 4 T276 12



Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 3 45 93.75 3


Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [values[0]] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 74 1 T213 1 T277 1 T178 10
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 63 1 T19 3 T158 1 T207 8
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 1 1 T118 1 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 4 1 T165 4 - - - -
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 181 1 T8 3 T11 5 T15 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 239 1 T27 15 T32 10 T147 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 160 1 T147 1 T130 1 T170 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 199 1 T8 11 T12 3 T18 2
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 171 1 T5 19 T96 1 T17 13
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 221 1 T5 9 T36 4 T49 13
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 1605 1 T1 21 T3 3 T10 2
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 263 1 T27 7 T118 1 T125 16
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 183 1 T13 1 T128 1 T133 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 232 1 T13 1 T30 7 T128 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 241 1 T15 1 T48 15 T126 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 168 1 T32 20 T37 3 T172 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 201 1 T131 1 T132 7 T134 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 178 1 T15 1 T131 1 T21 5
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 215 1 T5 10 T31 1 T206 13
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 251 1 T12 1 T31 1 T127 15
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 222 1 T206 9 T49 10 T122 6
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 333 1 T13 1 T97 1 T32 9
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 17478 1 T2 11 T4 20 T6 20
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 13 1 T278 10 T279 1 T280 2
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 51 1 T207 9 T220 20 T281 13
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 12 1 T118 12 - - - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 113 1 T27 8 T211 10 T123 13
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 239 1 T27 18 T32 11 T140 1
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 122 1 T130 9 T218 9 T282 14
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 112 1 T12 9 T132 4 T121 14
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 141 1 T5 4 T96 4 T17 2
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 200 1 T5 12 T36 1 T49 13
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 1025 1 T10 21 T28 6 T209 18
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 257 1 T27 2 T118 15 T125 15
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 168 1 T13 2 T128 7 T133 7
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 169 1 T13 7 T131 16 T210 11
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 204 1 T48 2 T20 1 T164 10
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 130 1 T32 15 T172 12 T136 19
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 158 1 T131 2 T132 10 T50 1
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 139 1 T131 2 T21 1 T51 6
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 227 1 T5 5 T206 12 T121 14
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 187 1 T12 2 T127 19 T50 4
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 150 1 T206 11 T49 11 T122 6
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 283 1 T13 11 T97 11 T32 6
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 148 1 T12 1 T18 2 T19 1



Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] * -- -- 4


Covered bins
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 121 1 T11 1 T15 1 T27 9
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 234 1 T8 1 T27 19 T32 12
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 187 1 T17 4 T147 1 T130 10
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 144 1 T12 10 T18 2 T132 5
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 166 1 T5 5 T96 5 T17 7
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 249 1 T5 13 T36 4 T49 14
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1399 1 T1 2 T3 3 T10 23
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 316 1 T27 3 T118 16 T125 16
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 210 1 T15 1 T128 8 T133 8
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 226 1 T30 1 T32 16 T128 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 225 1 T126 1 T20 3 T50 2
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 143 1 T13 8 T15 1 T172 13
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 235 1 T48 3 T131 3 T132 11
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 220 1 T12 3 T31 1 T127 9
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 254 1 T5 6 T31 1 T206 25
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 223 1 T13 12 T127 12 T118 14
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 154 1 T49 12 T213 1 T169 2
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 248 1 T97 12 T32 7 T33 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 9 1 T122 7 T274 1 T246 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 69 1 T123 9 T207 10 T225 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 17694 1 T2 11 T4 20 T6 20
auto[0] minimum auto[ADC_CTRL_FILTER_COND_OUT] 78 1 T260 11 T232 5 T165 1
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 127 1 T11 4 T27 3 T149 7
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 169 1 T8 10 T27 14 T32 9
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 150 1 T49 11 T218 9 T282 14
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 155 1 T12 2 T132 17 T121 14
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 119 1 T5 18 T17 4 T183 12
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 206 1 T5 8 T36 1 T49 12
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1290 1 T1 19 T40 26 T129 18
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 220 1 T27 6 T125 15 T169 10
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 98 1 T51 2 T135 8 T78 4
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 194 1 T30 6 T32 19 T37 1
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 168 1 T217 7 T224 10 T171 6
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 114 1 T135 4 T136 12 T262 11
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 172 1 T48 14 T132 6 T125 9
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 182 1 T127 2 T21 1 T51 9
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 214 1 T5 9 T206 20 T121 2
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 200 1 T127 11 T50 11 T38 2
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 172 1 T49 9 T216 2 T79 2
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 189 1 T32 8 T125 11 T207 11
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 5 1 T122 5 - - - -
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 76 1 T123 7 T207 7 T275 14
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 44 1 T8 2 T211 10 T123 12
auto[1] minimum auto[ADC_CTRL_FILTER_COND_OUT] 63 1 T232 5 T165 3 T283 14



Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [values[0]] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1


Covered bins
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 27 1 T213 1 T277 1 T178 1
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 62 1 T19 3 T158 1 T207 10
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 13 1 T118 13 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 1 1 T165 1 - - - -
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 151 1 T8 1 T11 1 T15 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 284 1 T27 19 T32 12 T147 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 154 1 T147 1 T130 10 T170 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 142 1 T8 1 T12 10 T18 2
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 179 1 T5 5 T96 5 T17 11
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 241 1 T5 13 T36 4 T49 14
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 1373 1 T1 2 T3 3 T10 23
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 297 1 T27 3 T118 16 T125 16
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 218 1 T13 3 T128 8 T133 8
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 215 1 T13 8 T30 1 T128 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 255 1 T15 1 T48 3 T126 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 158 1 T32 16 T37 2 T172 13
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 201 1 T131 3 T132 11 T134 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 176 1 T15 1 T131 3 T21 5
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 265 1 T5 6 T31 1 T206 13
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 233 1 T12 3 T31 1 T127 21
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 192 1 T206 12 T49 12 T122 7
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 341 1 T13 12 T97 12 T32 7
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 17626 1 T2 11 T4 20 T6 20
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 60 1 T178 9 T284 22 T223 5
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 52 1 T207 7 T220 18 T281 10
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 3 1 T165 3 - - - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 143 1 T8 2 T11 4 T27 3
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 194 1 T27 14 T32 9 T216 8
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 128 1 T218 9 T282 14 T26 2
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 169 1 T8 10 T12 2 T132 17
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 133 1 T5 18 T17 4 T49 11
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 180 1 T5 8 T36 1 T49 12
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 1257 1 T1 19 T40 26 T129 18
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 223 1 T27 6 T125 15 T169 10
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 133 1 T51 2 T235 10 T73 7
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 186 1 T30 6 T148 9 T216 9
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 190 1 T48 14 T217 7 T224 10
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 140 1 T32 19 T37 1 T136 12
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 158 1 T132 6 T125 9 T171 6
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 141 1 T21 1 T51 9 T120 12
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 177 1 T5 9 T206 12 T121 2
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 205 1 T127 13 T50 11 T142 14
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 180 1 T206 8 T49 9 T122 5
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 275 1 T32 8 T38 2 T123 7



Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for wakeup_gated_xp

Element holes
wakeup_cpclk_gate_cpCOUNTAT LEASTNUMBERSTATUS
* [auto[1]] -- -- 2


Covered bins
wakeup_cpclk_gate_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 22804 1 T1 2 T2 11 T3 3
auto[1] auto[0] 4327 1 T1 19 T5 35 T8 12

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