Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27131

1

T1

21

T2

11

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23677

1

T1

21

T2

11

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3454

1

T5

44

T8

11

T11

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21178

1

T2

11

T4

20

T6

20

auto[1]

5953

1

T1

21

T3

3

T5

59

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

21

T2

11

T3

3

auto[1]

4248

1

T5

21

T10

21

T12

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	66	1			T26	5		T256	32		T285	29
values[0]	47	1			T152	21		T286	12		T240	10
values[1]	775	1			T97	12		T31	1		T147	1
values[2]	813	1			T15	2		T31	1		T32	15
values[3]	826	1			T5	21		T96	5		T18	2
values[4]	591	1			T8	3		T17	11		T36	5
values[5]	2969	1			T1	21		T3	3		T5	15
values[6]	709	1			T5	23		T8	11		T12	3
values[7]	743	1			T17	4		T30	7		T128	8
values[8]	713	1			T12	12		T27	33		T32	35
values[9]	1253	1			T11	5		T13	20		T27	21
minimum	17626	1			T2	11		T4	20		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1012	1			T15	1		T97	12		T31	1
values[1]	775	1			T15	1		T32	15		T206	20
values[2]	696	1			T5	21		T96	5		T17	11
values[3]	3062	1			T1	21		T3	3		T8	3
values[4]	538	1			T5	38		T12	3		T131	3
values[5]	774	1			T8	11		T13	3		T15	1
values[6]	884	1			T17	4		T30	7		T32	35
values[7]	611	1			T12	12		T27	33		T33	1
values[8]	945	1			T11	5		T13	20		T27	21
values[9]	187	1			T32	21		T131	3		T21	6
minimum	17647	1			T2	11		T4	20		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

4327

1

T1

19

T5

35

T8

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T97	1		T147	1		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T15	1		T31	1		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T15	1		T118	1		T50	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T32	9		T206	9		T122	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T96	1		T17	9		T18	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T5	9		T31	1		T127	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1642	1			T1	21		T3	3		T8	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T125	12		T22	4		T220	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	10		T131	1		T118	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	19		T12	1		T38	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T13	1		T48	15		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T8	11		T15	1		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T17	4		T19	3		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T30	7		T32	20		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	3		T27	15		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T37	3		T119	1		T148	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T13	2		T27	11		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T11	5		T118	1		T121	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T21	5		T216	10		T287	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T32	10		T131	1		T124	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17478	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T152	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T97	11		T130	9		T131	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T130	11		T120	12		T207	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T118	15		T50	4		T120	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T32	6		T206	11		T122	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T96	4		T17	2		T169	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	12		T127	19		T206	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1035	1			T10	21		T28	6		T36	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T125	14		T22	1		T220	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T5	5		T131	2		T118	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T5	4		T12	2		T38	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	2		T48	2		T128	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T20	1		T132	10		T35	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T49	24		T123	13		T224	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T32	15		T141	12		T214	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	9		T27	18		T51	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T142	14		T244	1		T288	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	18		T27	10		T49	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T118	13		T121	14		T207	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T21	1		T216	11		T289	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T32	11		T131	2		T77	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	1		T18	2		T19	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T152	11		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T256	13		T285	12		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T26	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T290	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T152	10		T286	8		T240	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T97	1		T147	1		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T31	1		T130	1		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T15	1		T131	1		T50	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T15	1		T31	1		T32	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T96	1		T18	2		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T5	9		T127	15		T206	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T8	3		T17	9		T36	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T193	1		T22	4		T220	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1596	1			T1	21		T3	3		T5	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T31	1		T134	1		T38	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T13	1		T48	15		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	19		T8	11		T12	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T17	4		T128	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T30	7		T20	2		T132	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T12	3		T27	15		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T32	20		T141	1		T22	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	353	1			T13	2		T27	11		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	377	1			T11	5		T32	10		T131	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17478	1			T2	11		T4	20		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T256	19		T285	17		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T26	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T290	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T152	11		T286	4		T240	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T97	11		T130	9		T132	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T130	11		T207	9		T218	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T131	16		T50	4		T120	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T32	6		T120	12		T140	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T96	4		T118	15		T210	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	12		T127	19		T206	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T17	2		T36	1		T51	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T22	1		T220	20		T265	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T5	5		T10	21		T28	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T38	4		T125	29		T141	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	2		T48	2		T120	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T5	4		T12	2		T35	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T128	7		T49	11		T123	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T20	1		T132	10		T164	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	9		T27	18		T49	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T32	15		T141	12		T137	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T13	18		T27	10		T49	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T32	11		T131	2		T118	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	1		T18	2		T19	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T97	12		T147	1		T130	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T15	1		T31	1		T130	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T15	1		T118	16		T50	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T32	7		T206	12		T122	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T96	5		T17	7		T18	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T5	13		T31	1		T127	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T1	2		T3	3		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T125	15		T22	4		T220	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	6		T131	3		T118	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	5		T12	3		T38	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T13	3		T48	3		T128	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T8	1		T15	1		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T17	4		T19	3		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T30	1		T32	16		T141	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T12	10		T27	19		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T37	2		T119	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T13	20		T27	12		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T11	1		T118	14		T121	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T21	5		T216	12		T287	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T32	12		T131	3		T124	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17626	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T152	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T132	17		T121	2		T169	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T120	12		T207	7		T218	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T50	11		T214	1		T234	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T32	8		T206	8		T122	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T17	4		T264	12		T150	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	8		T127	13		T206	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T1	19		T8	2		T40	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T125	11		T22	1		T220	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T5	9		T252	13		T232	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T5	18		T38	2		T125	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T48	14		T214	12		T215	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T8	10		T132	6		T253	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T49	21		T148	3		T123	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T30	6		T32	19		T214	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	2		T27	14		T51	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T37	1		T148	9		T217	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T27	9		T49	11		T234	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	4		T121	14		T207	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T21	1		T216	9		T289	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T32	9		T77	1		T247	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T152	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T256	20		T285	18		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T26	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T290	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T152	12		T286	5		T240	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T97	12		T147	1		T130	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T31	1		T130	12		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T15	1		T131	17		T50	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T15	1		T31	1		T32	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T96	5		T18	2		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T5	13		T127	21		T206	25
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T8	1		T17	7		T36	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T193	1		T22	4		T220	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T1	2		T3	3		T5	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T31	1		T134	1		T38	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	3		T48	3		T120	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	5		T8	1		T12	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T17	4		T128	8		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T30	1		T20	3		T132	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T12	10		T27	19		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T32	16		T141	13		T22	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T13	20		T27	12		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T11	1		T32	12		T131	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17626	1			T2	11		T4	20		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T256	12		T285	11		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T26	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T152	9		T286	7		T240	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T132	17		T121	2		T218	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T207	7		T218	9		T291	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T50	11		T169	10		T214	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T32	8		T120	12		T258	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T251	11		T239	6		T292	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T5	8		T127	13		T206	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	2		T17	4		T36	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T22	1		T220	18		T150	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T1	19		T5	9		T40	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T38	2		T125	26		T218	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T48	14		T214	12		T215	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	18		T8	10		T253	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T49	9		T123	12		T171	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T30	6		T132	6		T214	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	2		T27	14		T49	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T32	19		T149	10		T137	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T27	9		T49	11		T21	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T11	4		T32	9		T37	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

auto[0]

4327

1

T1

19

T5

35

T8

12