Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27131

1

T1

21

T2

11

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23527

1

T1

21

T2

11

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3604

1

T5

59

T8

14

T13

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20964

1

T2

11

T4

20

T5

15

auto[1]

6167

1

T1

21

T3

3

T5

44

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

21

T2

11

T3

3

auto[1]

4248

1

T5

21

T10

21

T12

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	30	1			T293	14		T294	16		-	-
values[0]	92	1			T97	12		T220	21		T295	36
values[1]	855	1			T12	12		T18	2		T131	17
values[2]	607	1			T8	11		T12	3		T27	33
values[3]	655	1			T17	4		T30	7		T128	1
values[4]	773	1			T5	21		T48	17		T127	23
values[5]	871	1			T8	3		T17	11		T27	12
values[6]	849	1			T11	5		T126	2		T127	11
values[7]	580	1			T5	38		T13	8		T15	1
values[8]	669	1			T13	12		T15	1		T31	2
values[9]	3524	1			T1	21		T3	3		T10	23
minimum	17626	1			T2	11		T4	20		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1009	1			T12	12		T97	12		T31	1
values[1]	636	1			T8	11		T12	3		T17	4
values[2]	847	1			T30	7		T127	23		T133	8
values[3]	749	1			T5	21		T17	11		T27	12
values[4]	747	1			T8	3		T126	1		T50	16
values[5]	814	1			T5	15		T11	5		T15	1
values[6]	2934	1			T1	21		T3	3		T10	23
values[7]	609	1			T5	23		T13	23		T15	1
values[8]	963	1			T15	1		T19	3		T206	20
values[9]	175	1			T142	29		T75	1		T296	1
minimum	17648	1			T2	11		T4	20		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

4327

1

T1

19

T5

35

T8

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T12	3		T18	2		T33	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T97	1		T31	1		T118	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	1		T17	4		T27	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T8	11		T128	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T127	12		T118	1		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T30	7		T133	1		T49	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T48	15		T148	10		T123	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	9		T17	9		T27	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T50	12		T120	1		T175	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	3		T126	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	5		T15	1		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T5	10		T127	3		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1598	1			T1	21		T3	3		T10	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T96	1		T27	7		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T13	2		T15	1		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	19		T13	1		T32	29
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T217	7		T174	12		T193	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T15	1		T19	3		T206	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T142	15		T75	1		T296	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T233	14		T297	11		T298	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17483	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T299	1		T286	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T12	9		T130	9		T131	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T97	11		T118	13		T141	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T12	2		T27	18		T32	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T132	4		T172	12		T214	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T127	11		T118	15		T121	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T133	7		T49	21		T21	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T48	2		T123	2		T184	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	12		T17	2		T27	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T50	4		T120	1		T218	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T140	1		T210	11		T228	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T36	1		T132	10		T234	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T5	5		T127	8		T118	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1035	1			T10	21		T28	6		T209	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T96	4		T27	2		T125	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T13	9		T20	1		T164	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	4		T13	11		T32	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T174	10		T193	7		T22	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T206	11		T130	11		T131	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T142	14		T247	17		T300	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T233	13		T297	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	1		T18	2		T19	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T286	6		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T294	16		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T293	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T220	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T97	1		T295	15		T301	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T12	3		T18	2		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T119	1		T141	1		T225	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T12	1		T27	15		T32	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T8	11		T31	1		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T17	4		T118	1		T119	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T30	7		T128	1		T49	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T48	15		T127	12		T148	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	9		T133	1		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T50	12		T175	1		T218	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T8	3		T17	9		T27	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	5		T126	1		T36	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T126	1		T127	3		T118	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T13	1		T15	1		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	29		T96	1		T27	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T15	1		T31	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	1		T31	1		T32	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1795	1			T1	21		T3	3		T10	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T15	1		T32	20		T19	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17478	1			T2	11		T4	20		T6	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T220	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T97	11		T295	21		T301	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T12	9		T131	16		T49	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T141	11		T260	10		T259	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T12	2		T27	18		T32	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T118	13		T132	4		T172	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T118	15		T122	6		T224	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T49	11		T121	14		T125	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T48	2		T127	11		T123	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T5	12		T133	7		T131	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T50	4		T218	5		T234	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T17	2		T27	8		T128	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T36	1		T132	10		T120	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T127	8		T118	12		T253	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T13	7		T120	12		T302	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	9		T96	4		T27	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T20	1		T135	21		T137	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	11		T32	6		T206	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1182	1			T10	21		T13	2		T28	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T32	15		T206	11		T130	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	1		T18	2		T19	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T12	10		T18	2		T33	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T97	12		T31	1		T118	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T12	3		T17	4		T27	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T8	1		T128	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T127	12		T118	16		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T30	1		T133	8		T49	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T48	3		T148	1		T123	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	13		T17	7		T27	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T50	5		T120	2		T175	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T8	1		T126	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	1		T15	1		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T5	6		T127	9		T118	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1388	1			T1	2		T3	3		T10	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T96	5		T27	3		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	11		T15	1		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T5	5		T13	12		T32	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T217	1		T174	11		T193	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T15	1		T19	3		T206	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T142	15		T75	1		T296	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T233	14		T297	9		T298	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17631	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T299	1		T286	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T12	2		T49	12		T148	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T214	13		T216	2		T264	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T27	14		T32	9		T178	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T8	10		T132	17		T214	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T127	11		T121	14		T122	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T30	6		T49	20		T21	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T48	14		T148	9		T123	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T5	8		T17	4		T27	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T50	11		T218	3		T234	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	2		T143	12		T282	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	4		T36	1		T132	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	9		T127	2		T51	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1245	1			T1	19		T40	26		T129	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T27	6		T125	15		T207	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T37	1		T135	8		T189	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	18		T32	27		T206	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T217	6		T174	11		T193	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T206	8		T51	2		T211	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T142	14		T26	1		T247	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T233	13		T297	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T203	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T286	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T294	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T293	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T220	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T97	12		T295	22		T301	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T12	10		T18	2		T131	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T119	1		T141	12		T225	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	3		T27	19		T32	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T8	1		T31	1		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T17	4		T118	16		T119	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T30	1		T128	1		T49	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T48	3		T127	12		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	13		T133	8		T131	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T50	5		T175	1		T218	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T8	1		T17	7		T27	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	1		T126	1		T36	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T126	1		T127	9		T118	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	8		T15	1		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T5	11		T96	5		T27	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T15	1		T31	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	12		T31	1		T32	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1566	1			T1	2		T3	3		T10	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T15	1		T32	16		T19	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17626	1			T2	11		T4	20		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T294	15		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T293	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T220	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T295	14		T301	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T12	2		T49	12		T148	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T214	12		T196	5		T303	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T27	14		T32	9		T121	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	10		T132	17		T214	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T122	5		T224	10		T73	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T30	6		T49	9		T121	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T48	14		T127	11		T148	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	8		T49	11		T21	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T50	11		T218	3		T234	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T8	2		T17	4		T27	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	4		T36	1		T132	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T127	2		T183	12		T184	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T120	12		T263	2		T283	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	27		T27	6		T123	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T135	12		T137	15		T189	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T32	8		T206	12		T38	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1411	1			T1	19		T40	26		T129	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T32	19		T206	8		T51	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

auto[0]

4327

1

T1

19

T5

35

T8

12