Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27131

1

T1

21

T2

11

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23476

1

T1

21

T2

11

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3655

1

T5

44

T8

11

T13

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21053

1

T2

11

T4

20

T6

20

auto[1]

6078

1

T1

21

T3

3

T5

59

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

21

T2

11

T3

3

auto[1]

4248

1

T5

21

T10

21

T12

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	237	1			T19	3		T123	26		T124	1
values[0]	40	1			T248	16		T304	1		T301	23
values[1]	852	1			T12	12		T97	12		T18	2
values[2]	615	1			T8	11		T12	3		T27	33
values[3]	750	1			T17	4		T128	1		T118	16
values[4]	752	1			T5	21		T30	7		T48	17
values[5]	826	1			T8	3		T17	11		T27	12
values[6]	841	1			T126	1		T127	11		T36	5
values[7]	576	1			T5	15		T11	5		T15	1
values[8]	657	1			T5	23		T13	20		T15	1
values[9]	3359	1			T1	21		T3	3		T10	23
minimum	17626	1			T2	11		T4	20		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	776	1			T31	1		T18	2		T33	1
values[1]	700	1			T8	11		T12	3		T17	4
values[2]	854	1			T30	7		T127	23		T133	8
values[3]	658	1			T5	21		T17	11		T27	12
values[4]	836	1			T8	3		T126	1		T50	16
values[5]	673	1			T5	15		T11	5		T15	1
values[6]	3036	1			T1	21		T3	3		T10	23
values[7]	634	1			T5	23		T13	23		T15	1
values[8]	960	1			T15	1		T19	3		T206	20
values[9]	149	1			T142	29		T75	1		T81	1
minimum	17855	1			T2	11		T4	20		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

4327

1

T1

19

T5

35

T8

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T18	2		T33	1		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T31	1		T118	1		T119	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	1		T17	4		T27	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T8	11		T128	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T127	12		T118	1		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T30	7		T133	1		T49	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T48	15		T148	10		T123	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	9		T17	9		T27	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T8	3		T50	12		T120	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T126	1		T158	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	10		T11	5		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T127	3		T118	1		T51	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1614	1			T1	21		T3	3		T10	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T96	1		T27	7		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	2		T15	1		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T5	19		T13	1		T32	29
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T217	7		T174	12		T193	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T15	1		T19	3		T206	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T142	15		T81	1		T26	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T75	1		T238	18		T233	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17532	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T97	1		T193	1		T299	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T130	9		T215	6		T79	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T118	13		T141	23		T214	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T12	2		T27	18		T32	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T132	4		T172	12		T214	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T127	11		T118	15		T121	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T133	7		T49	21		T21	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T48	2		T123	2		T305	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T5	12		T17	2		T27	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T50	4		T120	1		T218	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T140	1		T210	11		T228	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	5		T36	1		T132	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T127	8		T118	12		T51	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1031	1			T10	21		T28	6		T209	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T96	4		T27	2		T125	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T13	9		T20	1		T164	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	4		T13	11		T32	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T174	10		T193	7		T22	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T206	11		T130	11		T131	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T142	14		T306	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T233	13		T297	8		T307	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T12	10		T18	2		T19	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T97	11		T295	21		T286	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T142	15		T77	1		T81	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T19	3		T123	13		T124	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T248	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T304	1		T301	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T12	3		T18	2		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T97	1		T119	1		T141	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	1		T27	15		T32	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T8	11		T31	1		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T17	4		T118	1		T119	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T128	1		T49	12		T121	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T48	15		T127	12		T148	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T5	9		T30	7		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T8	3		T50	12		T175	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T17	9		T27	4		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T126	1		T36	4		T132	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T127	3		T118	1		T51	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	10		T11	5		T15	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T96	1		T27	7		T123	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	1		T15	1		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	19		T13	1		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1746	1			T1	21		T3	3		T10	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T15	1		T32	29		T206	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17478	1			T2	11		T4	20		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T142	14		T308	3		T306	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T123	13		T220	20		T269	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T248	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T301	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	9		T131	16		T49	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T97	11		T141	23		T214	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T12	2		T27	18		T32	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T118	13		T132	4		T172	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T118	15		T122	6		T224	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T49	10		T121	14		T125	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T48	2		T127	11		T123	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T5	12		T133	7		T131	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T50	4		T218	5		T234	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T17	2		T27	8		T128	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T36	1		T132	10		T120	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T127	8		T118	12		T51	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T5	5		T120	12		T269	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T96	4		T27	2		T123	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	7		T20	1		T207	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	4		T13	11		T206	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1139	1			T10	21		T13	2		T28	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T32	21		T206	11		T130	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	1		T18	2		T19	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T18	2		T33	1		T130	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T31	1		T118	14		T119	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	3		T17	4		T27	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	1		T128	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T127	12		T118	16		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T30	1		T133	8		T49	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T48	3		T148	1		T123	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	13		T17	7		T27	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T8	1		T50	5		T120	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T126	1		T158	1		T140	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	6		T11	1		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T127	9		T118	13		T51	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T1	2		T3	3		T10	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T96	5		T27	3		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	11		T15	1		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	5		T13	12		T32	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T217	1		T174	11		T193	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T15	1		T19	3		T206	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T142	15		T81	1		T26	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T75	1		T238	1		T233	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17724	1			T2	11		T4	20		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T97	12		T193	1		T299	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T171	6		T215	11		T136	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T214	13		T235	10		T216	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T27	14		T32	9		T169	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	10		T132	17		T214	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T127	11		T121	14		T122	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T30	6		T49	20		T21	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T48	14		T148	9		T123	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T5	8		T17	4		T27	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T8	2		T50	11		T218	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T193	13		T143	12		T282	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T5	9		T11	4		T36	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T127	2		T51	9		T123	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1259	1			T1	19		T40	26		T129	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T27	6		T125	15		T253	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T37	1		T135	8		T137	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	18		T32	27		T206	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T217	6		T174	11		T193	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T206	8		T51	2		T211	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T142	14		T26	1		T306	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T238	17		T233	13		T297	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T12	2		T49	12		T148	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T295	14		T286	7		T301	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T142	15		T77	1		T81	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T19	3		T123	14		T124	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T248	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T304	1		T301	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T12	10		T18	2		T131	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T97	12		T119	1		T141	25
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	3		T27	19		T32	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	1		T31	1		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T17	4		T118	16		T119	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T128	1		T49	11		T121	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T48	3		T127	12		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	13		T30	1		T133	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	1		T50	5		T175	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T17	7		T27	9		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T126	1		T36	4		T132	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T127	9		T118	13		T51	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	6		T11	1		T15	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T96	5		T27	3		T123	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	8		T15	1		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	5		T13	12		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1512	1			T1	2		T3	3		T10	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T15	1		T32	23		T206	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17626	1			T2	11		T4	20		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T142	14		T26	1		T221	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T123	12		T220	18		T293	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T301	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T12	2		T49	12		T148	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T214	13		T196	5		T303	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T27	14		T32	9		T121	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T8	10		T132	17		T214	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T122	5		T224	10		T73	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T49	11		T121	2		T125	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T48	14		T127	11		T148	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T5	8		T30	6		T49	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T8	2		T50	11		T218	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T17	4		T27	3		T193	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T36	1		T132	6		T217	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T127	2		T51	9		T183	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T5	9		T11	4		T120	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T27	6		T123	7		T125	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T207	11		T135	12		T137	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	18		T206	12		T38	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1373	1			T1	19		T40	26		T129	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T32	27		T206	8		T51	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22804

1

T1

2

T2

11

T3

3

auto[1]

auto[0]

4327

1

T1

19

T5

35

T8

12