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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.86 99.07 96.67 100.00 100.00 98.83 98.33 92.11


Total test records in report: 919
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T794 /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2958700486 Jul 20 05:57:06 PM PDT 24 Jul 20 06:12:24 PM PDT 24 386891982364 ps
T795 /workspace/coverage/default/40.adc_ctrl_alert_test.309099762 Jul 20 06:00:05 PM PDT 24 Jul 20 06:00:07 PM PDT 24 360633442 ps
T796 /workspace/coverage/default/1.adc_ctrl_fsm_reset.3847672237 Jul 20 05:56:35 PM PDT 24 Jul 20 06:00:13 PM PDT 24 71761915607 ps
T797 /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2467271598 Jul 20 06:00:41 PM PDT 24 Jul 20 06:07:35 PM PDT 24 163027745672 ps
T56 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.16844367 Jul 20 05:56:20 PM PDT 24 Jul 20 05:56:24 PM PDT 24 426970565 ps
T798 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2834196946 Jul 20 05:56:24 PM PDT 24 Jul 20 05:56:28 PM PDT 24 472972555 ps
T799 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.742641271 Jul 20 05:56:32 PM PDT 24 Jul 20 05:56:36 PM PDT 24 407991476 ps
T47 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2787579389 Jul 20 05:56:20 PM PDT 24 Jul 20 05:56:29 PM PDT 24 3962357669 ps
T800 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2640478966 Jul 20 05:56:22 PM PDT 24 Jul 20 05:56:25 PM PDT 24 439138488 ps
T52 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.119700460 Jul 20 05:56:07 PM PDT 24 Jul 20 05:56:21 PM PDT 24 4341734383 ps
T62 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.478201035 Jul 20 05:56:11 PM PDT 24 Jul 20 05:56:14 PM PDT 24 529874304 ps
T44 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3688321365 Jul 20 05:56:06 PM PDT 24 Jul 20 05:56:12 PM PDT 24 2543440653 ps
T53 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3762228276 Jul 20 05:56:05 PM PDT 24 Jul 20 05:56:11 PM PDT 24 4405535347 ps
T801 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2017256807 Jul 20 05:56:21 PM PDT 24 Jul 20 05:56:23 PM PDT 24 540195892 ps
T117 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.354209833 Jul 20 05:56:05 PM PDT 24 Jul 20 05:56:08 PM PDT 24 1285423747 ps
T802 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1095586648 Jul 20 05:56:30 PM PDT 24 Jul 20 05:56:35 PM PDT 24 410917137 ps
T803 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3983212203 Jul 20 05:56:06 PM PDT 24 Jul 20 05:56:09 PM PDT 24 335542177 ps
T804 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2454492338 Jul 20 05:56:18 PM PDT 24 Jul 20 05:56:20 PM PDT 24 425119378 ps
T54 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2844392848 Jul 20 05:56:21 PM PDT 24 Jul 20 05:56:27 PM PDT 24 4276727131 ps
T98 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2132864859 Jul 20 05:56:14 PM PDT 24 Jul 20 05:56:18 PM PDT 24 445254424 ps
T63 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.4076859246 Jul 20 05:56:21 PM PDT 24 Jul 20 05:56:25 PM PDT 24 479960868 ps
T66 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1674267102 Jul 20 05:56:06 PM PDT 24 Jul 20 05:56:09 PM PDT 24 381387616 ps
T83 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2368697079 Jul 20 05:56:12 PM PDT 24 Jul 20 05:56:14 PM PDT 24 738187888 ps
T68 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1004467038 Jul 20 05:56:06 PM PDT 24 Jul 20 05:56:09 PM PDT 24 559133607 ps
T45 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2315265412 Jul 20 05:56:14 PM PDT 24 Jul 20 05:56:22 PM PDT 24 5400220658 ps
T46 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2947391715 Jul 20 05:56:13 PM PDT 24 Jul 20 05:56:22 PM PDT 24 3181608591 ps
T805 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1408469597 Jul 20 05:56:28 PM PDT 24 Jul 20 05:56:31 PM PDT 24 353416045 ps
T806 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1750630912 Jul 20 05:56:21 PM PDT 24 Jul 20 05:56:24 PM PDT 24 429093428 ps
T114 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2040264012 Jul 20 05:56:20 PM PDT 24 Jul 20 05:56:27 PM PDT 24 2529868267 ps
T93 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1577948611 Jul 20 05:56:13 PM PDT 24 Jul 20 05:56:19 PM PDT 24 4311695992 ps
T807 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3981727876 Jul 20 05:56:12 PM PDT 24 Jul 20 05:56:15 PM PDT 24 557180277 ps
T84 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.412944824 Jul 20 05:56:04 PM PDT 24 Jul 20 05:56:06 PM PDT 24 602885364 ps
T99 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3776578604 Jul 20 05:56:08 PM PDT 24 Jul 20 05:56:14 PM PDT 24 1035785349 ps
T100 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2499191175 Jul 20 05:56:08 PM PDT 24 Jul 20 05:56:41 PM PDT 24 49724342272 ps
T808 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1683125218 Jul 20 05:56:31 PM PDT 24 Jul 20 05:56:35 PM PDT 24 315692033 ps
T101 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.4102365634 Jul 20 05:56:12 PM PDT 24 Jul 20 05:56:15 PM PDT 24 380425407 ps
T57 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.611099926 Jul 20 05:56:15 PM PDT 24 Jul 20 05:56:29 PM PDT 24 9603607759 ps
T334 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2234763044 Jul 20 05:55:58 PM PDT 24 Jul 20 05:56:10 PM PDT 24 4424804401 ps
T809 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.149391619 Jul 20 05:56:15 PM PDT 24 Jul 20 05:56:18 PM PDT 24 463025742 ps
T58 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.472527890 Jul 20 05:56:13 PM PDT 24 Jul 20 05:56:34 PM PDT 24 8107049474 ps
T94 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3172435334 Jul 20 05:56:17 PM PDT 24 Jul 20 05:56:35 PM PDT 24 8599336987 ps
T102 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1445555711 Jul 20 05:56:06 PM PDT 24 Jul 20 05:56:11 PM PDT 24 1009632807 ps
T810 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3847652548 Jul 20 05:56:17 PM PDT 24 Jul 20 05:56:19 PM PDT 24 533469844 ps
T811 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.462333369 Jul 20 05:56:29 PM PDT 24 Jul 20 05:56:32 PM PDT 24 502575729 ps
T95 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.578616524 Jul 20 05:56:06 PM PDT 24 Jul 20 05:56:12 PM PDT 24 4164379512 ps
T812 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.4280243517 Jul 20 05:56:23 PM PDT 24 Jul 20 05:56:26 PM PDT 24 402423581 ps
T813 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2124345865 Jul 20 05:56:32 PM PDT 24 Jul 20 05:56:36 PM PDT 24 440142101 ps
T103 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.461365717 Jul 20 05:56:11 PM PDT 24 Jul 20 05:56:16 PM PDT 24 1165240544 ps
T814 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3580947293 Jul 20 05:56:19 PM PDT 24 Jul 20 05:56:22 PM PDT 24 502921467 ps
T115 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.78729380 Jul 20 05:56:29 PM PDT 24 Jul 20 05:56:42 PM PDT 24 4483544695 ps
T815 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3474612687 Jul 20 05:56:32 PM PDT 24 Jul 20 05:56:37 PM PDT 24 505434743 ps
T69 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1898241782 Jul 20 05:56:10 PM PDT 24 Jul 20 05:56:22 PM PDT 24 8528970932 ps
T816 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3865423968 Jul 20 05:56:07 PM PDT 24 Jul 20 05:56:13 PM PDT 24 715742873 ps
T817 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3633122049 Jul 20 05:56:30 PM PDT 24 Jul 20 05:56:34 PM PDT 24 436741768 ps
T818 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.141324329 Jul 20 05:56:17 PM PDT 24 Jul 20 05:56:20 PM PDT 24 480204359 ps
T819 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3941084880 Jul 20 05:56:31 PM PDT 24 Jul 20 05:56:35 PM PDT 24 592095878 ps
T820 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2733636226 Jul 20 05:56:25 PM PDT 24 Jul 20 05:56:28 PM PDT 24 487820943 ps
T821 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3102127645 Jul 20 05:56:14 PM PDT 24 Jul 20 05:56:16 PM PDT 24 367399320 ps
T822 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1740487222 Jul 20 05:56:20 PM PDT 24 Jul 20 05:56:21 PM PDT 24 523790216 ps
T70 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3965490626 Jul 20 05:56:14 PM PDT 24 Jul 20 05:56:19 PM PDT 24 5559606171 ps
T823 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3481230922 Jul 20 05:56:21 PM PDT 24 Jul 20 05:56:23 PM PDT 24 301775431 ps
T116 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.972930592 Jul 20 05:56:11 PM PDT 24 Jul 20 05:56:23 PM PDT 24 4238431027 ps
T104 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3758219862 Jul 20 05:56:05 PM PDT 24 Jul 20 05:56:07 PM PDT 24 531398995 ps
T824 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3774777654 Jul 20 05:56:23 PM PDT 24 Jul 20 05:56:25 PM PDT 24 644281984 ps
T67 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2062088858 Jul 20 05:56:15 PM PDT 24 Jul 20 05:56:19 PM PDT 24 670917575 ps
T825 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.730693691 Jul 20 05:56:31 PM PDT 24 Jul 20 05:56:36 PM PDT 24 422035869 ps
T105 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1060365322 Jul 20 05:56:13 PM PDT 24 Jul 20 05:56:16 PM PDT 24 380080978 ps
T826 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2516753621 Jul 20 05:56:28 PM PDT 24 Jul 20 05:56:34 PM PDT 24 545498906 ps
T106 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.533052108 Jul 20 05:56:06 PM PDT 24 Jul 20 05:56:11 PM PDT 24 826392302 ps
T827 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2482338830 Jul 20 05:56:14 PM PDT 24 Jul 20 05:56:17 PM PDT 24 397786152 ps
T828 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2343724333 Jul 20 05:56:06 PM PDT 24 Jul 20 05:56:19 PM PDT 24 5135657866 ps
T829 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1200886575 Jul 20 05:56:24 PM PDT 24 Jul 20 05:56:37 PM PDT 24 4260825233 ps
T107 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2305868052 Jul 20 05:56:12 PM PDT 24 Jul 20 05:56:14 PM PDT 24 1162083086 ps
T830 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.482193252 Jul 20 05:56:13 PM PDT 24 Jul 20 05:56:37 PM PDT 24 8550195594 ps
T831 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2212969157 Jul 20 05:56:28 PM PDT 24 Jul 20 05:56:30 PM PDT 24 336397356 ps
T832 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1231483472 Jul 20 05:56:27 PM PDT 24 Jul 20 05:56:30 PM PDT 24 390536871 ps
T833 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3676771212 Jul 20 05:56:17 PM PDT 24 Jul 20 05:56:27 PM PDT 24 3776983280 ps
T834 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.640272303 Jul 20 05:56:13 PM PDT 24 Jul 20 05:56:17 PM PDT 24 470366595 ps
T835 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2443500120 Jul 20 05:56:05 PM PDT 24 Jul 20 05:56:18 PM PDT 24 7832621564 ps
T836 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1450876773 Jul 20 05:56:26 PM PDT 24 Jul 20 05:56:28 PM PDT 24 567721722 ps
T837 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.864794777 Jul 20 05:56:09 PM PDT 24 Jul 20 05:56:11 PM PDT 24 363152190 ps
T838 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.423542684 Jul 20 05:56:05 PM PDT 24 Jul 20 05:56:06 PM PDT 24 538114797 ps
T839 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2814161091 Jul 20 05:56:05 PM PDT 24 Jul 20 05:56:08 PM PDT 24 379408947 ps
T840 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2271205323 Jul 20 05:56:29 PM PDT 24 Jul 20 05:56:36 PM PDT 24 4270384468 ps
T841 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.4049237747 Jul 20 05:56:12 PM PDT 24 Jul 20 05:56:22 PM PDT 24 2420649765 ps
T842 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3278893245 Jul 20 05:56:21 PM PDT 24 Jul 20 05:56:24 PM PDT 24 375074715 ps
T843 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4265549599 Jul 20 05:56:15 PM PDT 24 Jul 20 05:56:18 PM PDT 24 355482082 ps
T844 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1499644051 Jul 20 05:55:56 PM PDT 24 Jul 20 05:55:59 PM PDT 24 584009284 ps
T845 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4231455016 Jul 20 05:56:12 PM PDT 24 Jul 20 05:56:14 PM PDT 24 505693228 ps
T846 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.123457599 Jul 20 05:56:23 PM PDT 24 Jul 20 05:56:26 PM PDT 24 361003913 ps
T847 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.4223432923 Jul 20 05:56:07 PM PDT 24 Jul 20 05:56:12 PM PDT 24 2052101390 ps
T848 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.734969559 Jul 20 05:56:27 PM PDT 24 Jul 20 05:56:35 PM PDT 24 2083075735 ps
T849 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2866906380 Jul 20 05:56:19 PM PDT 24 Jul 20 05:56:22 PM PDT 24 710622205 ps
T850 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2942527695 Jul 20 05:56:06 PM PDT 24 Jul 20 05:56:09 PM PDT 24 440919022 ps
T851 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2774444184 Jul 20 05:56:16 PM PDT 24 Jul 20 05:56:18 PM PDT 24 357958987 ps
T852 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3764935089 Jul 20 05:56:15 PM PDT 24 Jul 20 05:56:28 PM PDT 24 4490827243 ps
T853 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.4045438151 Jul 20 05:56:27 PM PDT 24 Jul 20 05:56:30 PM PDT 24 461406018 ps
T854 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2341013745 Jul 20 05:56:14 PM PDT 24 Jul 20 05:56:20 PM PDT 24 4388178489 ps
T108 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2358594646 Jul 20 05:56:04 PM PDT 24 Jul 20 05:56:06 PM PDT 24 807228966 ps
T855 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.25688320 Jul 20 05:56:32 PM PDT 24 Jul 20 05:56:38 PM PDT 24 4406393128 ps
T856 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3630281586 Jul 20 05:56:07 PM PDT 24 Jul 20 05:56:10 PM PDT 24 535791520 ps
T857 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2177149551 Jul 20 05:56:31 PM PDT 24 Jul 20 05:56:38 PM PDT 24 4682911966 ps
T109 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.224287669 Jul 20 05:56:08 PM PDT 24 Jul 20 05:56:12 PM PDT 24 461044845 ps
T858 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1716555004 Jul 20 05:56:24 PM PDT 24 Jul 20 05:56:27 PM PDT 24 437865868 ps
T859 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2099562841 Jul 20 05:56:11 PM PDT 24 Jul 20 05:56:14 PM PDT 24 500060640 ps
T860 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2505085118 Jul 20 05:56:14 PM PDT 24 Jul 20 05:56:19 PM PDT 24 384791126 ps
T861 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.545226195 Jul 20 05:56:13 PM PDT 24 Jul 20 05:56:16 PM PDT 24 440280692 ps
T110 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3244156572 Jul 20 05:56:08 PM PDT 24 Jul 20 05:57:35 PM PDT 24 24558503653 ps
T111 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.276765987 Jul 20 05:56:03 PM PDT 24 Jul 20 05:56:08 PM PDT 24 677212544 ps
T862 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1191134838 Jul 20 05:56:30 PM PDT 24 Jul 20 05:56:41 PM PDT 24 3887760034 ps
T112 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4143889737 Jul 20 05:56:05 PM PDT 24 Jul 20 05:56:12 PM PDT 24 1246166876 ps
T863 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1592664261 Jul 20 05:56:13 PM PDT 24 Jul 20 05:56:15 PM PDT 24 299738245 ps
T864 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.4151167799 Jul 20 05:56:07 PM PDT 24 Jul 20 05:56:11 PM PDT 24 2036003242 ps
T865 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1653258518 Jul 20 05:56:04 PM PDT 24 Jul 20 05:56:06 PM PDT 24 602774186 ps
T866 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1729740099 Jul 20 05:56:08 PM PDT 24 Jul 20 05:56:11 PM PDT 24 302422944 ps
T867 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.903110479 Jul 20 05:56:25 PM PDT 24 Jul 20 05:56:28 PM PDT 24 456930968 ps
T868 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.859619607 Jul 20 05:56:21 PM PDT 24 Jul 20 05:56:24 PM PDT 24 423574755 ps
T869 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3582909046 Jul 20 05:56:11 PM PDT 24 Jul 20 05:56:13 PM PDT 24 403644461 ps
T870 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.465657500 Jul 20 05:56:03 PM PDT 24 Jul 20 05:56:06 PM PDT 24 476904339 ps
T871 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1297234999 Jul 20 05:56:16 PM PDT 24 Jul 20 05:56:18 PM PDT 24 442699719 ps
T872 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2386752592 Jul 20 05:56:21 PM PDT 24 Jul 20 05:56:26 PM PDT 24 9606070676 ps
T873 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3056386106 Jul 20 05:56:15 PM PDT 24 Jul 20 05:56:18 PM PDT 24 456844624 ps
T874 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3432864161 Jul 20 05:56:23 PM PDT 24 Jul 20 05:56:26 PM PDT 24 448924780 ps
T113 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3008168293 Jul 20 05:56:08 PM PDT 24 Jul 20 05:57:03 PM PDT 24 42547246067 ps
T875 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1579036553 Jul 20 05:56:07 PM PDT 24 Jul 20 05:56:11 PM PDT 24 527440204 ps
T876 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3308291711 Jul 20 05:56:22 PM PDT 24 Jul 20 05:56:25 PM PDT 24 424441246 ps
T877 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3692963061 Jul 20 05:56:13 PM PDT 24 Jul 20 05:56:16 PM PDT 24 617087831 ps
T878 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1906979989 Jul 20 05:56:18 PM PDT 24 Jul 20 05:56:20 PM PDT 24 407994948 ps
T879 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2187950930 Jul 20 05:56:10 PM PDT 24 Jul 20 05:56:12 PM PDT 24 401966239 ps
T880 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4227160260 Jul 20 05:56:34 PM PDT 24 Jul 20 05:56:38 PM PDT 24 408073788 ps
T881 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4073932115 Jul 20 05:56:11 PM PDT 24 Jul 20 05:56:14 PM PDT 24 465459018 ps
T882 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1019688018 Jul 20 05:56:05 PM PDT 24 Jul 20 05:56:07 PM PDT 24 358347350 ps
T883 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.772701914 Jul 20 05:56:07 PM PDT 24 Jul 20 05:56:30 PM PDT 24 28627650856 ps
T884 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1653132935 Jul 20 05:56:06 PM PDT 24 Jul 20 05:56:09 PM PDT 24 742572018 ps
T885 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3465593903 Jul 20 05:56:12 PM PDT 24 Jul 20 05:56:14 PM PDT 24 426340880 ps
T886 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1398376919 Jul 20 05:56:16 PM PDT 24 Jul 20 05:56:19 PM PDT 24 517080081 ps
T887 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.43812041 Jul 20 05:56:12 PM PDT 24 Jul 20 05:56:14 PM PDT 24 534632524 ps
T888 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2897805591 Jul 20 05:56:15 PM PDT 24 Jul 20 05:56:20 PM PDT 24 3607198604 ps
T889 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.187908278 Jul 20 05:56:05 PM PDT 24 Jul 20 05:56:09 PM PDT 24 363537153 ps
T890 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3565933900 Jul 20 05:56:26 PM PDT 24 Jul 20 05:56:29 PM PDT 24 340277904 ps
T891 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3071850319 Jul 20 05:56:18 PM PDT 24 Jul 20 05:56:20 PM PDT 24 491129515 ps
T892 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2748463882 Jul 20 05:56:15 PM PDT 24 Jul 20 05:56:18 PM PDT 24 531195729 ps
T893 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.891383898 Jul 20 05:56:06 PM PDT 24 Jul 20 05:56:10 PM PDT 24 468498882 ps
T894 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.216838087 Jul 20 05:56:17 PM PDT 24 Jul 20 05:56:20 PM PDT 24 430658032 ps
T895 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3845597923 Jul 20 05:56:17 PM PDT 24 Jul 20 05:56:20 PM PDT 24 481068355 ps
T896 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2082340354 Jul 20 05:56:11 PM PDT 24 Jul 20 05:56:13 PM PDT 24 322673288 ps
T897 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2522904167 Jul 20 05:56:22 PM PDT 24 Jul 20 05:56:25 PM PDT 24 364921541 ps
T898 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2759503999 Jul 20 05:56:15 PM PDT 24 Jul 20 05:56:19 PM PDT 24 303459342 ps
T899 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3171828226 Jul 20 05:56:10 PM PDT 24 Jul 20 05:56:16 PM PDT 24 4622931402 ps
T900 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3390457389 Jul 20 05:56:22 PM PDT 24 Jul 20 05:56:24 PM PDT 24 347693898 ps
T901 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.897028692 Jul 20 05:56:30 PM PDT 24 Jul 20 05:56:48 PM PDT 24 3593579290 ps
T902 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3593854237 Jul 20 05:56:05 PM PDT 24 Jul 20 05:56:08 PM PDT 24 718693744 ps
T903 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1454578897 Jul 20 05:56:15 PM PDT 24 Jul 20 05:56:17 PM PDT 24 353789710 ps
T904 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2313241457 Jul 20 05:56:23 PM PDT 24 Jul 20 05:56:26 PM PDT 24 391614950 ps
T905 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.369845665 Jul 20 05:56:22 PM PDT 24 Jul 20 05:56:25 PM PDT 24 422422293 ps
T906 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.482391362 Jul 20 05:56:07 PM PDT 24 Jul 20 05:56:11 PM PDT 24 2393334255 ps
T907 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.351493464 Jul 20 05:56:19 PM PDT 24 Jul 20 05:56:20 PM PDT 24 468389211 ps
T908 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1128751350 Jul 20 05:56:11 PM PDT 24 Jul 20 05:56:14 PM PDT 24 759676798 ps
T909 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3029688836 Jul 20 05:56:20 PM PDT 24 Jul 20 05:56:22 PM PDT 24 540075197 ps
T910 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.140971992 Jul 20 05:56:06 PM PDT 24 Jul 20 05:56:15 PM PDT 24 2720706547 ps
T911 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3131701782 Jul 20 05:56:07 PM PDT 24 Jul 20 05:56:11 PM PDT 24 544119265 ps
T912 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2950661261 Jul 20 05:56:27 PM PDT 24 Jul 20 05:56:29 PM PDT 24 522449098 ps
T913 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2533990343 Jul 20 05:56:30 PM PDT 24 Jul 20 05:56:34 PM PDT 24 355555512 ps
T914 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3842090312 Jul 20 05:56:26 PM PDT 24 Jul 20 05:56:28 PM PDT 24 618094985 ps
T915 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1462803078 Jul 20 05:56:30 PM PDT 24 Jul 20 05:56:39 PM PDT 24 8459552784 ps
T916 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1776575963 Jul 20 05:56:15 PM PDT 24 Jul 20 05:56:18 PM PDT 24 493403777 ps
T917 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2136653868 Jul 20 05:56:20 PM PDT 24 Jul 20 05:56:22 PM PDT 24 358241784 ps
T918 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2270396302 Jul 20 05:56:03 PM PDT 24 Jul 20 05:56:05 PM PDT 24 571779386 ps
T919 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.918669790 Jul 20 05:56:17 PM PDT 24 Jul 20 05:56:20 PM PDT 24 381969250 ps

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2793895157
Short name T5
Test name
Test status
Simulation time 538220379516 ps
CPU time 336.16 seconds
Started Jul 20 05:59:59 PM PDT 24
Finished Jul 20 06:05:36 PM PDT 24
Peak memory 201752 kb
Host smart-d27d2d56-cab8-4040-82e0-9af8bef17018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793895157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2793895157
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3016069059
Short name T7
Test name
Test status
Simulation time 82035251094 ps
CPU time 416.24 seconds
Started Jul 20 05:59:16 PM PDT 24
Finished Jul 20 06:06:13 PM PDT 24
Peak memory 202052 kb
Host smart-75c4ec5a-1127-4969-ac06-0d11ab08fef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016069059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3016069059
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2952145352
Short name T17
Test name
Test status
Simulation time 317942804378 ps
CPU time 134.8 seconds
Started Jul 20 05:59:14 PM PDT 24
Finished Jul 20 06:01:30 PM PDT 24
Peak memory 210060 kb
Host smart-b82acab7-f08b-4079-99a5-cd992a4ea337
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952145352 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2952145352
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3675731740
Short name T27
Test name
Test status
Simulation time 522742830622 ps
CPU time 299.33 seconds
Started Jul 20 05:56:36 PM PDT 24
Finished Jul 20 06:01:38 PM PDT 24
Peak memory 201760 kb
Host smart-7a5c10bd-b2ef-4181-901f-dbb3c543ab44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675731740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3675731740
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1380895425
Short name T21
Test name
Test status
Simulation time 162047908660 ps
CPU time 300.39 seconds
Started Jul 20 05:57:00 PM PDT 24
Finished Jul 20 06:02:01 PM PDT 24
Peak memory 210504 kb
Host smart-65d3296b-a3ab-4e12-a25d-45bec13f006a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380895425 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1380895425
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3597193538
Short name T125
Test name
Test status
Simulation time 514685251773 ps
CPU time 1184.07 seconds
Started Jul 20 05:57:13 PM PDT 24
Finished Jul 20 06:16:58 PM PDT 24
Peak memory 201644 kb
Host smart-9c7051f9-c19c-4d00-895b-1f0b76828eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597193538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3597193538
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3370593020
Short name T12
Test name
Test status
Simulation time 335552597102 ps
CPU time 212.46 seconds
Started Jul 20 05:58:23 PM PDT 24
Finished Jul 20 06:01:55 PM PDT 24
Peak memory 201696 kb
Host smart-45176a12-9430-45a4-95c0-a8533f4468ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370593020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3370593020
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1065666764
Short name T216
Test name
Test status
Simulation time 506325725793 ps
CPU time 1080.23 seconds
Started Jul 20 05:57:11 PM PDT 24
Finished Jul 20 06:15:12 PM PDT 24
Peak memory 201876 kb
Host smart-46d6e4a6-f7c2-460e-b116-d413c06ffad6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065666764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1065666764
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2829257520
Short name T123
Test name
Test status
Simulation time 526506905283 ps
CPU time 242.17 seconds
Started Jul 20 06:01:40 PM PDT 24
Finished Jul 20 06:05:43 PM PDT 24
Peak memory 201744 kb
Host smart-827f6f13-f058-4a6e-8f2b-3d5974bc78b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829257520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2829257520
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.4076859246
Short name T63
Test name
Test status
Simulation time 479960868 ps
CPU time 3.27 seconds
Started Jul 20 05:56:21 PM PDT 24
Finished Jul 20 05:56:25 PM PDT 24
Peak memory 201816 kb
Host smart-f6ae8b1d-9814-46e3-8366-49369412f9af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076859246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.4076859246
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3031715818
Short name T120
Test name
Test status
Simulation time 528849132777 ps
CPU time 406.32 seconds
Started Jul 20 05:57:47 PM PDT 24
Finished Jul 20 06:04:34 PM PDT 24
Peak memory 201728 kb
Host smart-44a8a81b-23c6-4910-a8db-942a81b11f2a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031715818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3031715818
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2408910640
Short name T220
Test name
Test status
Simulation time 512585760540 ps
CPU time 920.03 seconds
Started Jul 20 06:01:46 PM PDT 24
Finished Jul 20 06:17:07 PM PDT 24
Peak memory 201760 kb
Host smart-358378f7-6f94-4c17-99a4-b1c3d375345f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408910640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2408910640
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2553290941
Short name T13
Test name
Test status
Simulation time 480129821599 ps
CPU time 281.38 seconds
Started Jul 20 05:56:45 PM PDT 24
Finished Jul 20 06:01:27 PM PDT 24
Peak memory 201744 kb
Host smart-b963da0b-4906-4d15-8d6c-1c47461be071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553290941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2553290941
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.4140501178
Short name T77
Test name
Test status
Simulation time 362814358883 ps
CPU time 395.92 seconds
Started Jul 20 05:56:49 PM PDT 24
Finished Jul 20 06:03:27 PM PDT 24
Peak memory 217620 kb
Host smart-5c373bd1-1761-448e-9e79-ec22f487c865
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140501178 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.4140501178
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.4014390230
Short name T152
Test name
Test status
Simulation time 479495877010 ps
CPU time 148.32 seconds
Started Jul 20 06:00:40 PM PDT 24
Finished Jul 20 06:03:09 PM PDT 24
Peak memory 201744 kb
Host smart-b2dfff9f-eda7-4871-8570-cf0fbde44a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014390230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.4014390230
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2520919568
Short name T32
Test name
Test status
Simulation time 527939023121 ps
CPU time 1250.88 seconds
Started Jul 20 05:56:59 PM PDT 24
Finished Jul 20 06:17:51 PM PDT 24
Peak memory 201744 kb
Host smart-537b5264-d034-48d7-873c-1e8d171f8388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520919568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2520919568
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.87233322
Short name T16
Test name
Test status
Simulation time 535946150 ps
CPU time 0.97 seconds
Started Jul 20 05:57:06 PM PDT 24
Finished Jul 20 05:57:07 PM PDT 24
Peak memory 201560 kb
Host smart-c2261762-53d1-4642-9521-7d539531a082
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87233322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.87233322
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3758219862
Short name T104
Test name
Test status
Simulation time 531398995 ps
CPU time 1.35 seconds
Started Jul 20 05:56:05 PM PDT 24
Finished Jul 20 05:56:07 PM PDT 24
Peak memory 201436 kb
Host smart-a76fda72-ddfd-43c6-a3ba-3046cde41ad8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758219862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3758219862
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1172736888
Short name T22
Test name
Test status
Simulation time 65530726982 ps
CPU time 144.57 seconds
Started Jul 20 06:00:38 PM PDT 24
Finished Jul 20 06:03:03 PM PDT 24
Peak memory 218044 kb
Host smart-b120faa1-a9e6-4f09-ad0e-a99c07ba75e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172736888 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1172736888
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1213352488
Short name T129
Test name
Test status
Simulation time 386964827795 ps
CPU time 107.42 seconds
Started Jul 20 05:57:18 PM PDT 24
Finished Jul 20 05:59:06 PM PDT 24
Peak memory 201664 kb
Host smart-ffc3dfcb-98e9-4848-9dc8-c1b9f99e0cbf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213352488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1213352488
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3843398351
Short name T72
Test name
Test status
Simulation time 3891756108 ps
CPU time 3.2 seconds
Started Jul 20 05:56:32 PM PDT 24
Finished Jul 20 05:56:38 PM PDT 24
Peak memory 217252 kb
Host smart-d282e7d8-8517-4868-9c8a-1816d2f1fac8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843398351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3843398351
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3174232732
Short name T232
Test name
Test status
Simulation time 527684744782 ps
CPU time 578.27 seconds
Started Jul 20 05:57:31 PM PDT 24
Finished Jul 20 06:07:10 PM PDT 24
Peak memory 201824 kb
Host smart-f5125edf-aa7c-4b35-bb49-2c8650a0eecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174232732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3174232732
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1036601989
Short name T223
Test name
Test status
Simulation time 580025046853 ps
CPU time 356.82 seconds
Started Jul 20 05:59:24 PM PDT 24
Finished Jul 20 06:05:21 PM PDT 24
Peak memory 201800 kb
Host smart-312ef0a7-8f3c-415e-bca1-174cbed05cf2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036601989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1036601989
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.106116941
Short name T121
Test name
Test status
Simulation time 348874616932 ps
CPU time 770.86 seconds
Started Jul 20 05:59:14 PM PDT 24
Finished Jul 20 06:12:06 PM PDT 24
Peak memory 201692 kb
Host smart-a13ff07b-4417-4bc8-b467-a5d75c64c0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106116941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.106116941
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3880098759
Short name T49
Test name
Test status
Simulation time 507147820060 ps
CPU time 342.04 seconds
Started Jul 20 06:00:38 PM PDT 24
Finished Jul 20 06:06:21 PM PDT 24
Peak memory 201768 kb
Host smart-f1ebd81f-b50a-4fa9-b3b0-1623770fcd43
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880098759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3880098759
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2345923227
Short name T141
Test name
Test status
Simulation time 483836964555 ps
CPU time 273.19 seconds
Started Jul 20 05:58:28 PM PDT 24
Finished Jul 20 06:03:02 PM PDT 24
Peak memory 201932 kb
Host smart-9d1ea3fd-3149-4205-9b94-363d2f854ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345923227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2345923227
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3283037196
Short name T164
Test name
Test status
Simulation time 495856844429 ps
CPU time 615.81 seconds
Started Jul 20 05:57:15 PM PDT 24
Finished Jul 20 06:07:31 PM PDT 24
Peak memory 201744 kb
Host smart-91cb6764-c6bc-4309-bac0-115ab446c648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283037196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3283037196
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.1018103390
Short name T270
Test name
Test status
Simulation time 333648078898 ps
CPU time 296.71 seconds
Started Jul 20 05:58:36 PM PDT 24
Finished Jul 20 06:03:33 PM PDT 24
Peak memory 201752 kb
Host smart-88c89dc8-eaf3-4b70-ab54-73871bfdcf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018103390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1018103390
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.757579225
Short name T75
Test name
Test status
Simulation time 497712488411 ps
CPU time 828.4 seconds
Started Jul 20 05:57:01 PM PDT 24
Finished Jul 20 06:10:50 PM PDT 24
Peak memory 201684 kb
Host smart-0f407be7-3d77-41f8-aa59-db871c37355d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757579225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.757579225
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3454356514
Short name T143
Test name
Test status
Simulation time 563387141186 ps
CPU time 517.64 seconds
Started Jul 20 05:56:56 PM PDT 24
Finished Jul 20 06:05:35 PM PDT 24
Peak memory 202060 kb
Host smart-7fbbb09b-ff3a-4e48-b846-35999b42a1a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454356514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3454356514
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.483807775
Short name T122
Test name
Test status
Simulation time 168907838100 ps
CPU time 95.18 seconds
Started Jul 20 05:59:40 PM PDT 24
Finished Jul 20 06:01:16 PM PDT 24
Peak memory 201732 kb
Host smart-40ed801d-ac6f-492f-9ef0-ee4f6eb06f07
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483807775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.483807775
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.611099926
Short name T57
Test name
Test status
Simulation time 9603607759 ps
CPU time 11.86 seconds
Started Jul 20 05:56:15 PM PDT 24
Finished Jul 20 05:56:29 PM PDT 24
Peak memory 201808 kb
Host smart-18dd80ed-67c3-49a0-9bc2-701a6a2732b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611099926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_in
tg_err.611099926
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1315977690
Short name T165
Test name
Test status
Simulation time 547983317843 ps
CPU time 281.86 seconds
Started Jul 20 05:57:40 PM PDT 24
Finished Jul 20 06:02:22 PM PDT 24
Peak memory 201800 kb
Host smart-0534d038-28f4-481e-86fb-1883143372b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315977690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1315977690
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1663014124
Short name T193
Test name
Test status
Simulation time 626303700990 ps
CPU time 745.77 seconds
Started Jul 20 05:57:04 PM PDT 24
Finished Jul 20 06:09:31 PM PDT 24
Peak memory 210308 kb
Host smart-3db946da-1349-4758-acba-dc21d38b7dd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663014124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1663014124
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.732075646
Short name T320
Test name
Test status
Simulation time 743008635559 ps
CPU time 1793.56 seconds
Started Jul 20 05:59:40 PM PDT 24
Finished Jul 20 06:29:34 PM PDT 24
Peak memory 201736 kb
Host smart-17e43001-86d4-40cc-aeb3-388432adcca9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732075646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.
732075646
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.4121838681
Short name T142
Test name
Test status
Simulation time 175637942836 ps
CPU time 99.96 seconds
Started Jul 20 05:57:55 PM PDT 24
Finished Jul 20 05:59:36 PM PDT 24
Peak memory 201744 kb
Host smart-92696610-c2bf-4f65-bf7e-36a9d46c620a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121838681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.4121838681
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3883725933
Short name T301
Test name
Test status
Simulation time 344552343969 ps
CPU time 199.32 seconds
Started Jul 20 06:01:06 PM PDT 24
Finished Jul 20 06:04:26 PM PDT 24
Peak memory 201720 kb
Host smart-dfd1fe20-f249-4cff-a5d1-5d1cd3fbeddd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883725933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3883725933
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1263605319
Short name T130
Test name
Test status
Simulation time 326213253531 ps
CPU time 734.73 seconds
Started Jul 20 05:58:12 PM PDT 24
Finished Jul 20 06:10:27 PM PDT 24
Peak memory 201820 kb
Host smart-d8b92b35-3bfd-4fb2-8ea8-d6677193ca46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263605319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1263605319
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2223957935
Short name T297
Test name
Test status
Simulation time 486163842495 ps
CPU time 1064.44 seconds
Started Jul 20 06:00:32 PM PDT 24
Finished Jul 20 06:18:16 PM PDT 24
Peak memory 201728 kb
Host smart-3ac8a508-57ca-42c1-b43b-819069f7f656
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223957935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2223957935
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2315265412
Short name T45
Test name
Test status
Simulation time 5400220658 ps
CPU time 6.29 seconds
Started Jul 20 05:56:14 PM PDT 24
Finished Jul 20 05:56:22 PM PDT 24
Peak memory 201832 kb
Host smart-db6c1a51-d953-4730-b22d-b7bce8810af3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315265412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2315265412
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3991733552
Short name T319
Test name
Test status
Simulation time 336137902691 ps
CPU time 211.08 seconds
Started Jul 20 05:57:09 PM PDT 24
Finished Jul 20 06:00:41 PM PDT 24
Peak memory 201636 kb
Host smart-d590a077-a3e4-46e2-b276-389e0378ee9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991733552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3991733552
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2161223536
Short name T257
Test name
Test status
Simulation time 361893930097 ps
CPU time 180.13 seconds
Started Jul 20 05:56:39 PM PDT 24
Finished Jul 20 05:59:40 PM PDT 24
Peak memory 201720 kb
Host smart-f0c125ef-ddec-4017-86cd-70d0e088e33d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161223536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2161223536
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2915437675
Short name T226
Test name
Test status
Simulation time 489347604748 ps
CPU time 591.54 seconds
Started Jul 20 05:58:12 PM PDT 24
Finished Jul 20 06:08:04 PM PDT 24
Peak memory 201748 kb
Host smart-413bd108-842b-478a-842c-0d874775ca44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915437675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2915437675
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1721874123
Short name T31
Test name
Test status
Simulation time 492984378793 ps
CPU time 1082.28 seconds
Started Jul 20 05:56:59 PM PDT 24
Finished Jul 20 06:15:03 PM PDT 24
Peak memory 201764 kb
Host smart-121d89e5-cef0-404d-9782-15af09c5514f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721874123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1721874123
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1334663859
Short name T322
Test name
Test status
Simulation time 381121303294 ps
CPU time 356.85 seconds
Started Jul 20 06:00:34 PM PDT 24
Finished Jul 20 06:06:31 PM PDT 24
Peak memory 210504 kb
Host smart-4d6ecb49-b848-482d-806a-23a465b1a064
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334663859 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1334663859
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.3361706416
Short name T239
Test name
Test status
Simulation time 503160928104 ps
CPU time 311.01 seconds
Started Jul 20 05:56:47 PM PDT 24
Finished Jul 20 06:02:00 PM PDT 24
Peak memory 201756 kb
Host smart-448a188c-ee68-4f1c-b688-a4e4fd11b1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361706416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3361706416
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2457015462
Short name T26
Test name
Test status
Simulation time 63163850124 ps
CPU time 100.92 seconds
Started Jul 20 06:01:13 PM PDT 24
Finished Jul 20 06:02:55 PM PDT 24
Peak memory 210132 kb
Host smart-6cad63e8-e286-4e70-91c8-08863db9977d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457015462 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2457015462
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.153159289
Short name T171
Test name
Test status
Simulation time 284154496926 ps
CPU time 836.06 seconds
Started Jul 20 06:01:49 PM PDT 24
Finished Jul 20 06:15:46 PM PDT 24
Peak memory 210284 kb
Host smart-482faee3-66ff-4f67-9bc4-83147b5a1107
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153159289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
153159289
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3818217013
Short name T240
Test name
Test status
Simulation time 910665268615 ps
CPU time 224.9 seconds
Started Jul 20 05:56:25 PM PDT 24
Finished Jul 20 06:00:12 PM PDT 24
Peak memory 210020 kb
Host smart-439f26b8-040d-4113-a8cd-f8dde7b40e04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818217013 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3818217013
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.573659493
Short name T118
Test name
Test status
Simulation time 490356945388 ps
CPU time 828.85 seconds
Started Jul 20 05:56:22 PM PDT 24
Finished Jul 20 06:10:12 PM PDT 24
Peak memory 201700 kb
Host smart-b6f65d45-9105-405f-b15b-8abc95c0b502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573659493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.573659493
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.47483183
Short name T281
Test name
Test status
Simulation time 334829948257 ps
CPU time 202.52 seconds
Started Jul 20 05:56:43 PM PDT 24
Finished Jul 20 06:00:07 PM PDT 24
Peak memory 201724 kb
Host smart-b9a2596f-d878-458c-88c1-18b346bfeb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47483183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.47483183
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.589332501
Short name T327
Test name
Test status
Simulation time 518548662395 ps
CPU time 459.15 seconds
Started Jul 20 05:56:40 PM PDT 24
Finished Jul 20 06:04:20 PM PDT 24
Peak memory 201724 kb
Host smart-0f1ece95-4d46-47b6-947e-a3b733b0dabb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589332501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.589332501
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2023483794
Short name T248
Test name
Test status
Simulation time 492576636133 ps
CPU time 544.15 seconds
Started Jul 20 05:56:58 PM PDT 24
Finished Jul 20 06:06:03 PM PDT 24
Peak memory 201732 kb
Host smart-59b9adfb-049a-4547-9421-8d8914c31f72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023483794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2023483794
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2605527737
Short name T234
Test name
Test status
Simulation time 327765268231 ps
CPU time 196.8 seconds
Started Jul 20 05:56:56 PM PDT 24
Finished Jul 20 06:00:14 PM PDT 24
Peak memory 201644 kb
Host smart-8389870f-0e25-48aa-a40a-44afbe253f1b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605527737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2605527737
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2239268574
Short name T293
Test name
Test status
Simulation time 177744856624 ps
CPU time 389.92 seconds
Started Jul 20 05:57:11 PM PDT 24
Finished Jul 20 06:03:42 PM PDT 24
Peak memory 201732 kb
Host smart-c1ad7429-c9db-498e-a105-7426f6dbdf60
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239268574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2239268574
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2278173062
Short name T97
Test name
Test status
Simulation time 160713670239 ps
CPU time 397.02 seconds
Started Jul 20 05:57:13 PM PDT 24
Finished Jul 20 06:03:51 PM PDT 24
Peak memory 201708 kb
Host smart-dc377ba6-b8a2-4a11-9e6f-5d3ddf7ccfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278173062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2278173062
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.4175275666
Short name T285
Test name
Test status
Simulation time 179149638460 ps
CPU time 134.12 seconds
Started Jul 20 05:57:21 PM PDT 24
Finished Jul 20 05:59:35 PM PDT 24
Peak memory 201708 kb
Host smart-dd91a0ce-cb25-4e0a-8b81-bc77c7fe22dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175275666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.4175275666
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1571554550
Short name T286
Test name
Test status
Simulation time 530499305600 ps
CPU time 1147.17 seconds
Started Jul 20 05:57:47 PM PDT 24
Finished Jul 20 06:16:54 PM PDT 24
Peak memory 201732 kb
Host smart-e25ff021-5342-49d5-90e9-5e0c2fce23c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571554550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1571554550
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.4101086682
Short name T268
Test name
Test status
Simulation time 328585238366 ps
CPU time 581.91 seconds
Started Jul 20 05:58:49 PM PDT 24
Finished Jul 20 06:08:31 PM PDT 24
Peak memory 201736 kb
Host smart-17c9d63f-ea76-46ad-8657-a09b7399a236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101086682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.4101086682
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.4262956598
Short name T324
Test name
Test status
Simulation time 167657673452 ps
CPU time 195.03 seconds
Started Jul 20 05:59:19 PM PDT 24
Finished Jul 20 06:02:34 PM PDT 24
Peak memory 201772 kb
Host smart-e32d565e-820a-42fd-8612-740affb79c7f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262956598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.4262956598
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2118817750
Short name T214
Test name
Test status
Simulation time 519790362118 ps
CPU time 292.41 seconds
Started Jul 20 05:56:40 PM PDT 24
Finished Jul 20 06:01:34 PM PDT 24
Peak memory 201940 kb
Host smart-35132155-3148-41d3-b964-43bf438da284
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118817750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2118817750
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1604838917
Short name T290
Test name
Test status
Simulation time 335365415294 ps
CPU time 423.69 seconds
Started Jul 20 05:56:32 PM PDT 24
Finished Jul 20 06:03:39 PM PDT 24
Peak memory 201788 kb
Host smart-a41428d3-635f-46b5-bae8-40cd164686b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604838917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1604838917
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.4261246622
Short name T203
Test name
Test status
Simulation time 268477810263 ps
CPU time 697.51 seconds
Started Jul 20 05:57:25 PM PDT 24
Finished Jul 20 06:09:03 PM PDT 24
Peak memory 210500 kb
Host smart-2ef6d733-7031-4707-b128-f84b728e4421
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261246622 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.4261246622
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3588403487
Short name T294
Test name
Test status
Simulation time 374048163542 ps
CPU time 230.52 seconds
Started Jul 20 05:57:31 PM PDT 24
Finished Jul 20 06:01:22 PM PDT 24
Peak memory 201808 kb
Host smart-4e34ac06-8490-430e-9704-e4b9d916311c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588403487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3588403487
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3889823388
Short name T208
Test name
Test status
Simulation time 551273601230 ps
CPU time 566.67 seconds
Started Jul 20 05:58:55 PM PDT 24
Finished Jul 20 06:08:22 PM PDT 24
Peak memory 201744 kb
Host smart-b3dbf554-f703-4714-aaec-f3599b84453a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889823388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3889823388
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3600840557
Short name T245
Test name
Test status
Simulation time 327645337091 ps
CPU time 376.41 seconds
Started Jul 20 05:59:53 PM PDT 24
Finished Jul 20 06:06:10 PM PDT 24
Peak memory 201828 kb
Host smart-0411ccec-de12-45c2-bae7-e331e0e088e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600840557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3600840557
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2504377618
Short name T222
Test name
Test status
Simulation time 529345085324 ps
CPU time 1243.58 seconds
Started Jul 20 05:59:56 PM PDT 24
Finished Jul 20 06:20:41 PM PDT 24
Peak memory 201808 kb
Host smart-82e84457-74fb-40e3-85e6-d7e60aec113f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504377618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2504377618
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.4145376572
Short name T316
Test name
Test status
Simulation time 175390285337 ps
CPU time 399.8 seconds
Started Jul 20 05:59:59 PM PDT 24
Finished Jul 20 06:06:39 PM PDT 24
Peak memory 201748 kb
Host smart-b375186f-5d48-4edc-b4f0-07610e6f173c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145376572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.4145376572
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1485549048
Short name T137
Test name
Test status
Simulation time 363603924940 ps
CPU time 771.85 seconds
Started Jul 20 06:00:13 PM PDT 24
Finished Jul 20 06:13:05 PM PDT 24
Peak memory 201752 kb
Host smart-1e16f2f6-7b0e-424d-b415-cf59a28089af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485549048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1485549048
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2482538213
Short name T272
Test name
Test status
Simulation time 403506029826 ps
CPU time 484.61 seconds
Started Jul 20 05:56:29 PM PDT 24
Finished Jul 20 06:04:35 PM PDT 24
Peak memory 201800 kb
Host smart-7d51e8fb-b0c1-4c7e-b6f8-35f65336a33b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482538213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2482538213
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2632622726
Short name T148
Test name
Test status
Simulation time 362398700207 ps
CPU time 203.48 seconds
Started Jul 20 05:56:49 PM PDT 24
Finished Jul 20 06:00:14 PM PDT 24
Peak memory 201752 kb
Host smart-72307c4c-6e8f-4444-8923-d77b500c728e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632622726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2632622726
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2822563020
Short name T323
Test name
Test status
Simulation time 346768733045 ps
CPU time 815.71 seconds
Started Jul 20 05:56:59 PM PDT 24
Finished Jul 20 06:10:36 PM PDT 24
Peak memory 201820 kb
Host smart-329b1aaf-0364-4274-8be4-54ca5bc19e77
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822563020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2822563020
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.4174155816
Short name T197
Test name
Test status
Simulation time 101200619917 ps
CPU time 536.26 seconds
Started Jul 20 05:57:15 PM PDT 24
Finished Jul 20 06:06:12 PM PDT 24
Peak memory 202160 kb
Host smart-f1e78614-42f3-4a88-be72-4cc540d8a86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174155816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.4174155816
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2882062240
Short name T78
Test name
Test status
Simulation time 380622065428 ps
CPU time 755.25 seconds
Started Jul 20 05:57:23 PM PDT 24
Finished Jul 20 06:09:59 PM PDT 24
Peak memory 201796 kb
Host smart-d9f720ef-64aa-4347-88a8-1ca8cd60a438
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882062240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2882062240
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3836579899
Short name T230
Test name
Test status
Simulation time 327155332364 ps
CPU time 780.31 seconds
Started Jul 20 06:00:34 PM PDT 24
Finished Jul 20 06:13:35 PM PDT 24
Peak memory 201752 kb
Host smart-404c17f1-50ff-4109-81d1-8c88fb86b825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836579899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3836579899
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.4286813720
Short name T225
Test name
Test status
Simulation time 496152197157 ps
CPU time 1224.77 seconds
Started Jul 20 06:01:24 PM PDT 24
Finished Jul 20 06:21:49 PM PDT 24
Peak memory 201760 kb
Host smart-eba99000-5978-4691-85a3-8821a6b74c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286813720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.4286813720
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.957426425
Short name T279
Test name
Test status
Simulation time 344847334755 ps
CPU time 364.09 seconds
Started Jul 20 05:56:31 PM PDT 24
Finished Jul 20 06:02:38 PM PDT 24
Peak memory 201736 kb
Host smart-8ee850cf-8f78-4bad-81a1-31483b54e220
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957426425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.957426425
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3597194785
Short name T42
Test name
Test status
Simulation time 131336772931 ps
CPU time 712.82 seconds
Started Jul 20 05:57:17 PM PDT 24
Finished Jul 20 06:09:11 PM PDT 24
Peak memory 202148 kb
Host smart-c7071ead-0fc7-4cb1-97d6-7ba60022a4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597194785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3597194785
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.4041550850
Short name T312
Test name
Test status
Simulation time 239188844375 ps
CPU time 405.11 seconds
Started Jul 20 05:57:17 PM PDT 24
Finished Jul 20 06:04:03 PM PDT 24
Peak memory 201800 kb
Host smart-31012ab7-4a06-4b4f-ace0-de6fc7c9f064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041550850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.4041550850
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2269564013
Short name T254
Test name
Test status
Simulation time 532331274403 ps
CPU time 300.6 seconds
Started Jul 20 05:56:36 PM PDT 24
Finished Jul 20 06:01:39 PM PDT 24
Peak memory 201416 kb
Host smart-949c291c-fdf5-44d4-85e7-b6c52800b139
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269564013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2269564013
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2607762908
Short name T321
Test name
Test status
Simulation time 576127833685 ps
CPU time 357.89 seconds
Started Jul 20 05:58:14 PM PDT 24
Finished Jul 20 06:04:12 PM PDT 24
Peak memory 201780 kb
Host smart-52e54907-7242-43be-9d33-dfc98e1a392b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607762908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2607762908
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.16054693
Short name T201
Test name
Test status
Simulation time 404067387528 ps
CPU time 511.76 seconds
Started Jul 20 05:59:22 PM PDT 24
Finished Jul 20 06:07:55 PM PDT 24
Peak memory 218472 kb
Host smart-892a02d7-9dc1-49cf-b5f4-af4ae589ddb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16054693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.16054693
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2077859707
Short name T339
Test name
Test status
Simulation time 109538553921 ps
CPU time 544.29 seconds
Started Jul 20 06:00:35 PM PDT 24
Finished Jul 20 06:09:40 PM PDT 24
Peak memory 202116 kb
Host smart-b191b8bd-2acd-46aa-9191-0e90f7c56bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077859707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2077859707
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2213995941
Short name T202
Test name
Test status
Simulation time 136423667279 ps
CPU time 741.57 seconds
Started Jul 20 06:00:35 PM PDT 24
Finished Jul 20 06:12:57 PM PDT 24
Peak memory 202160 kb
Host smart-0fbd1272-ba12-4171-9cc9-a990a7226c56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213995941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2213995941
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.1815897019
Short name T338
Test name
Test status
Simulation time 122821534207 ps
CPU time 487.73 seconds
Started Jul 20 06:00:41 PM PDT 24
Finished Jul 20 06:08:50 PM PDT 24
Peak memory 202036 kb
Host smart-33adf692-7b59-4dec-b2ac-7779803c4fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815897019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1815897019
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2975552404
Short name T73
Test name
Test status
Simulation time 509902726953 ps
CPU time 316.48 seconds
Started Jul 20 06:01:24 PM PDT 24
Finished Jul 20 06:06:41 PM PDT 24
Peak memory 201652 kb
Host smart-f2f684d1-930c-4073-bc5b-eeaebbc8cfc7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975552404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2975552404
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.980136112
Short name T50
Test name
Test status
Simulation time 325414343529 ps
CPU time 331.22 seconds
Started Jul 20 05:56:37 PM PDT 24
Finished Jul 20 06:02:10 PM PDT 24
Peak memory 201712 kb
Host smart-ff53633b-948c-4507-9596-d748adca9c45
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980136112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.980136112
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.224287669
Short name T109
Test name
Test status
Simulation time 461044845 ps
CPU time 2.51 seconds
Started Jul 20 05:56:08 PM PDT 24
Finished Jul 20 05:56:12 PM PDT 24
Peak memory 201580 kb
Host smart-921047e3-632e-4732-9a99-58330be16b54
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224287669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.224287669
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4143889737
Short name T112
Test name
Test status
Simulation time 1246166876 ps
CPU time 5.73 seconds
Started Jul 20 05:56:05 PM PDT 24
Finished Jul 20 05:56:12 PM PDT 24
Peak memory 201632 kb
Host smart-aebc9085-caa8-4123-b698-9abefeebf0dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143889737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.4143889737
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2305868052
Short name T107
Test name
Test status
Simulation time 1162083086 ps
CPU time 1.44 seconds
Started Jul 20 05:56:12 PM PDT 24
Finished Jul 20 05:56:14 PM PDT 24
Peak memory 201444 kb
Host smart-b5b169d6-c268-4264-8319-75451fe2eb9f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305868052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2305868052
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.423542684
Short name T838
Test name
Test status
Simulation time 538114797 ps
CPU time 1.29 seconds
Started Jul 20 05:56:05 PM PDT 24
Finished Jul 20 05:56:06 PM PDT 24
Peak memory 201592 kb
Host smart-6fabc3e2-3f45-4dd3-891a-feb0d19e3ec9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423542684 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.423542684
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3983212203
Short name T803
Test name
Test status
Simulation time 335542177 ps
CPU time 0.82 seconds
Started Jul 20 05:56:06 PM PDT 24
Finished Jul 20 05:56:09 PM PDT 24
Peak memory 201448 kb
Host smart-4ff45aa4-1dd1-4357-940a-223199082855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983212203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3983212203
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2343724333
Short name T828
Test name
Test status
Simulation time 5135657866 ps
CPU time 10.78 seconds
Started Jul 20 05:56:06 PM PDT 24
Finished Jul 20 05:56:19 PM PDT 24
Peak memory 201792 kb
Host smart-622fe24e-db59-4587-8aee-5f162a814adf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343724333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2343724333
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1499644051
Short name T844
Test name
Test status
Simulation time 584009284 ps
CPU time 1.89 seconds
Started Jul 20 05:55:56 PM PDT 24
Finished Jul 20 05:55:59 PM PDT 24
Peak memory 201752 kb
Host smart-8cdc395d-755e-4571-b616-12e3d3eb2699
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499644051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1499644051
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2234763044
Short name T334
Test name
Test status
Simulation time 4424804401 ps
CPU time 10.87 seconds
Started Jul 20 05:55:58 PM PDT 24
Finished Jul 20 05:56:10 PM PDT 24
Peak memory 201712 kb
Host smart-55095422-7b55-4f37-859e-cc013aa0739a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234763044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2234763044
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3865423968
Short name T816
Test name
Test status
Simulation time 715742873 ps
CPU time 3.64 seconds
Started Jul 20 05:56:07 PM PDT 24
Finished Jul 20 05:56:13 PM PDT 24
Peak memory 201660 kb
Host smart-5848981b-948f-497b-96de-7281e2213f52
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865423968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3865423968
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.772701914
Short name T883
Test name
Test status
Simulation time 28627650856 ps
CPU time 21.93 seconds
Started Jul 20 05:56:07 PM PDT 24
Finished Jul 20 05:56:30 PM PDT 24
Peak memory 201692 kb
Host smart-a0698aaa-197a-48cd-8f05-d5346c7ec2be
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772701914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.772701914
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2358594646
Short name T108
Test name
Test status
Simulation time 807228966 ps
CPU time 1.59 seconds
Started Jul 20 05:56:04 PM PDT 24
Finished Jul 20 05:56:06 PM PDT 24
Peak memory 201484 kb
Host smart-28d47bcc-db06-47b7-8224-7b6fd0a88639
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358594646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2358594646
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1653258518
Short name T865
Test name
Test status
Simulation time 602774186 ps
CPU time 1.33 seconds
Started Jul 20 05:56:04 PM PDT 24
Finished Jul 20 05:56:06 PM PDT 24
Peak memory 209984 kb
Host smart-4b5834ed-5d79-4f6c-abf3-af1d9a996cf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653258518 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.1653258518
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2814161091
Short name T839
Test name
Test status
Simulation time 379408947 ps
CPU time 1.61 seconds
Started Jul 20 05:56:05 PM PDT 24
Finished Jul 20 05:56:08 PM PDT 24
Peak memory 201396 kb
Host smart-92deacb1-3a49-4122-b7d8-b2bd00ffca10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814161091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2814161091
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.43812041
Short name T887
Test name
Test status
Simulation time 534632524 ps
CPU time 1.29 seconds
Started Jul 20 05:56:12 PM PDT 24
Finished Jul 20 05:56:14 PM PDT 24
Peak memory 201392 kb
Host smart-fbc892c9-30f6-4963-8555-ca85da964996
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43812041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.43812041
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.482391362
Short name T906
Test name
Test status
Simulation time 2393334255 ps
CPU time 2.03 seconds
Started Jul 20 05:56:07 PM PDT 24
Finished Jul 20 05:56:11 PM PDT 24
Peak memory 201584 kb
Host smart-47cbf60a-3649-43fa-8a56-808e04fc9367
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482391362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.482391362
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1019688018
Short name T882
Test name
Test status
Simulation time 358347350 ps
CPU time 1.72 seconds
Started Jul 20 05:56:05 PM PDT 24
Finished Jul 20 05:56:07 PM PDT 24
Peak memory 201776 kb
Host smart-b285811f-61e5-4d41-b76e-46ecbb1fcba5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019688018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1019688018
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2443500120
Short name T835
Test name
Test status
Simulation time 7832621564 ps
CPU time 12.21 seconds
Started Jul 20 05:56:05 PM PDT 24
Finished Jul 20 05:56:18 PM PDT 24
Peak memory 201672 kb
Host smart-80e2e10b-2ae5-4693-ba6a-e5667446aff3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443500120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2443500120
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3582909046
Short name T869
Test name
Test status
Simulation time 403644461 ps
CPU time 1.11 seconds
Started Jul 20 05:56:11 PM PDT 24
Finished Jul 20 05:56:13 PM PDT 24
Peak memory 201724 kb
Host smart-03e654ce-4e6a-4bf7-a4de-5d466b5ba0c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582909046 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3582909046
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2132864859
Short name T98
Test name
Test status
Simulation time 445254424 ps
CPU time 1.77 seconds
Started Jul 20 05:56:14 PM PDT 24
Finished Jul 20 05:56:18 PM PDT 24
Peak memory 201464 kb
Host smart-19313120-89f3-436a-805b-6ee6689c7a7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132864859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2132864859
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3465593903
Short name T885
Test name
Test status
Simulation time 426340880 ps
CPU time 0.81 seconds
Started Jul 20 05:56:12 PM PDT 24
Finished Jul 20 05:56:14 PM PDT 24
Peak memory 201432 kb
Host smart-e2489ea8-85a5-45ca-9c57-072dc7953e4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465593903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3465593903
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3764935089
Short name T852
Test name
Test status
Simulation time 4490827243 ps
CPU time 11.42 seconds
Started Jul 20 05:56:15 PM PDT 24
Finished Jul 20 05:56:28 PM PDT 24
Peak memory 201788 kb
Host smart-770770b3-709c-4953-ad6b-9bda738c4565
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764935089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3764935089
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.640272303
Short name T834
Test name
Test status
Simulation time 470366595 ps
CPU time 2.08 seconds
Started Jul 20 05:56:13 PM PDT 24
Finished Jul 20 05:56:17 PM PDT 24
Peak memory 201784 kb
Host smart-c41383ce-339a-4a2b-aee2-249a65fba973
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640272303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.640272303
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1200886575
Short name T829
Test name
Test status
Simulation time 4260825233 ps
CPU time 10.72 seconds
Started Jul 20 05:56:24 PM PDT 24
Finished Jul 20 05:56:37 PM PDT 24
Peak memory 201800 kb
Host smart-1d0e8c79-dd88-495e-b894-5d15f1c5a57b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200886575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1200886575
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3692963061
Short name T877
Test name
Test status
Simulation time 617087831 ps
CPU time 2.38 seconds
Started Jul 20 05:56:13 PM PDT 24
Finished Jul 20 05:56:16 PM PDT 24
Peak memory 201588 kb
Host smart-df4358fa-4e52-49eb-923f-d5c20e156b6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692963061 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3692963061
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2774444184
Short name T851
Test name
Test status
Simulation time 357958987 ps
CPU time 0.92 seconds
Started Jul 20 05:56:16 PM PDT 24
Finished Jul 20 05:56:18 PM PDT 24
Peak memory 201456 kb
Host smart-22898374-8d6c-4c8c-8218-f86c1f5da26a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774444184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2774444184
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.351493464
Short name T907
Test name
Test status
Simulation time 468389211 ps
CPU time 1.03 seconds
Started Jul 20 05:56:19 PM PDT 24
Finished Jul 20 05:56:20 PM PDT 24
Peak memory 201424 kb
Host smart-de9db6ed-9672-431a-aca5-b3cc676fd301
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351493464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.351493464
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2271205323
Short name T840
Test name
Test status
Simulation time 4270384468 ps
CPU time 4.21 seconds
Started Jul 20 05:56:29 PM PDT 24
Finished Jul 20 05:56:36 PM PDT 24
Peak memory 201836 kb
Host smart-5da866cf-b25d-4d2f-9627-4a162fc40b21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271205323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2271205323
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.16844367
Short name T56
Test name
Test status
Simulation time 426970565 ps
CPU time 3 seconds
Started Jul 20 05:56:20 PM PDT 24
Finished Jul 20 05:56:24 PM PDT 24
Peak memory 201860 kb
Host smart-4fdb3676-955e-4043-b74f-29727e982a72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16844367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.16844367
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3172435334
Short name T94
Test name
Test status
Simulation time 8599336987 ps
CPU time 16.69 seconds
Started Jul 20 05:56:17 PM PDT 24
Finished Jul 20 05:56:35 PM PDT 24
Peak memory 201716 kb
Host smart-5c4b8489-f0e2-4d48-9cf7-50445ce9c81e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172435334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3172435334
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2482338830
Short name T827
Test name
Test status
Simulation time 397786152 ps
CPU time 1.17 seconds
Started Jul 20 05:56:14 PM PDT 24
Finished Jul 20 05:56:17 PM PDT 24
Peak memory 201616 kb
Host smart-07796e7b-d31f-4473-867e-b0fc292487c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482338830 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2482338830
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4265549599
Short name T843
Test name
Test status
Simulation time 355482082 ps
CPU time 1.24 seconds
Started Jul 20 05:56:15 PM PDT 24
Finished Jul 20 05:56:18 PM PDT 24
Peak memory 201432 kb
Host smart-6ea625d9-17ac-4e1d-bbe3-f19509aa6d9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265549599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.4265549599
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1592664261
Short name T863
Test name
Test status
Simulation time 299738245 ps
CPU time 1.01 seconds
Started Jul 20 05:56:13 PM PDT 24
Finished Jul 20 05:56:15 PM PDT 24
Peak memory 201476 kb
Host smart-54c57cb0-c0eb-4ab2-bc87-33bb37a21494
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592664261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1592664261
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.78729380
Short name T115
Test name
Test status
Simulation time 4483544695 ps
CPU time 10.23 seconds
Started Jul 20 05:56:29 PM PDT 24
Finished Jul 20 05:56:42 PM PDT 24
Peak memory 201744 kb
Host smart-5be3ac22-20e0-4190-878d-a20913654d44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78729380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ct
rl_same_csr_outstanding.78729380
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.478201035
Short name T62
Test name
Test status
Simulation time 529874304 ps
CPU time 2.42 seconds
Started Jul 20 05:56:11 PM PDT 24
Finished Jul 20 05:56:14 PM PDT 24
Peak memory 201748 kb
Host smart-66f786b9-11af-4eaa-82ae-248107c603df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478201035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.478201035
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3965490626
Short name T70
Test name
Test status
Simulation time 5559606171 ps
CPU time 3.63 seconds
Started Jul 20 05:56:14 PM PDT 24
Finished Jul 20 05:56:19 PM PDT 24
Peak memory 201792 kb
Host smart-f632dd2c-729f-44cc-8bef-71a4e928f1f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965490626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3965490626
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2950661261
Short name T912
Test name
Test status
Simulation time 522449098 ps
CPU time 1.31 seconds
Started Jul 20 05:56:27 PM PDT 24
Finished Jul 20 05:56:29 PM PDT 24
Peak memory 201484 kb
Host smart-9e2126f6-f771-47ff-933d-4aa0e74afceb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950661261 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2950661261
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2748463882
Short name T892
Test name
Test status
Simulation time 531195729 ps
CPU time 1.44 seconds
Started Jul 20 05:56:15 PM PDT 24
Finished Jul 20 05:56:18 PM PDT 24
Peak memory 201468 kb
Host smart-fd0fd166-686f-407b-98bf-ff7650919b04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748463882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2748463882
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.149391619
Short name T809
Test name
Test status
Simulation time 463025742 ps
CPU time 0.85 seconds
Started Jul 20 05:56:15 PM PDT 24
Finished Jul 20 05:56:18 PM PDT 24
Peak memory 201464 kb
Host smart-847c77b0-8ad8-4d84-82ce-1964cafe8a69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149391619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.149391619
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2897805591
Short name T888
Test name
Test status
Simulation time 3607198604 ps
CPU time 2.97 seconds
Started Jul 20 05:56:15 PM PDT 24
Finished Jul 20 05:56:20 PM PDT 24
Peak memory 201764 kb
Host smart-3a9843c9-ea70-4b7e-a287-010552926499
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897805591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2897805591
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2759503999
Short name T898
Test name
Test status
Simulation time 303459342 ps
CPU time 2.42 seconds
Started Jul 20 05:56:15 PM PDT 24
Finished Jul 20 05:56:19 PM PDT 24
Peak memory 218128 kb
Host smart-c89ae5a2-ae2f-4f2f-9e4a-1cb9c3342ddc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759503999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2759503999
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1450876773
Short name T836
Test name
Test status
Simulation time 567721722 ps
CPU time 1.13 seconds
Started Jul 20 05:56:26 PM PDT 24
Finished Jul 20 05:56:28 PM PDT 24
Peak memory 201560 kb
Host smart-56daf8fe-3def-4908-9737-ebe2f4633ff8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450876773 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1450876773
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2187950930
Short name T879
Test name
Test status
Simulation time 401966239 ps
CPU time 0.97 seconds
Started Jul 20 05:56:10 PM PDT 24
Finished Jul 20 05:56:12 PM PDT 24
Peak memory 201488 kb
Host smart-59bb80a8-c98f-434e-a27c-6a7f9d37fdc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187950930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2187950930
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3102127645
Short name T821
Test name
Test status
Simulation time 367399320 ps
CPU time 0.75 seconds
Started Jul 20 05:56:14 PM PDT 24
Finished Jul 20 05:56:16 PM PDT 24
Peak memory 201448 kb
Host smart-5a9a4e4f-7cf6-440a-ad7c-12565cee632c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102127645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3102127645
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2341013745
Short name T854
Test name
Test status
Simulation time 4388178489 ps
CPU time 4.06 seconds
Started Jul 20 05:56:14 PM PDT 24
Finished Jul 20 05:56:20 PM PDT 24
Peak memory 201828 kb
Host smart-a05f1942-0e8e-4408-b077-1c0dbc896584
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341013745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2341013745
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2505085118
Short name T860
Test name
Test status
Simulation time 384791126 ps
CPU time 3.16 seconds
Started Jul 20 05:56:14 PM PDT 24
Finished Jul 20 05:56:19 PM PDT 24
Peak memory 218120 kb
Host smart-3b15141d-6703-4fff-a7ec-817470b41473
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505085118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2505085118
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.25688320
Short name T855
Test name
Test status
Simulation time 4406393128 ps
CPU time 4.09 seconds
Started Jul 20 05:56:32 PM PDT 24
Finished Jul 20 05:56:38 PM PDT 24
Peak memory 201736 kb
Host smart-ff92fba5-9eff-40ee-aeb6-9133324798d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25688320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_int
g_err.25688320
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3845597923
Short name T895
Test name
Test status
Simulation time 481068355 ps
CPU time 1.87 seconds
Started Jul 20 05:56:17 PM PDT 24
Finished Jul 20 05:56:20 PM PDT 24
Peak memory 201536 kb
Host smart-297a668f-aa78-474b-ae41-5e8e17f85622
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845597923 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3845597923
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1297234999
Short name T871
Test name
Test status
Simulation time 442699719 ps
CPU time 0.99 seconds
Started Jul 20 05:56:16 PM PDT 24
Finished Jul 20 05:56:18 PM PDT 24
Peak memory 201456 kb
Host smart-b997a768-534d-4411-bca8-a7ebd2b59508
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297234999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1297234999
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1454578897
Short name T903
Test name
Test status
Simulation time 353789710 ps
CPU time 0.81 seconds
Started Jul 20 05:56:15 PM PDT 24
Finished Jul 20 05:56:17 PM PDT 24
Peak memory 201460 kb
Host smart-30a821d0-f44f-412e-b08e-7366d38a3566
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454578897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1454578897
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2062088858
Short name T67
Test name
Test status
Simulation time 670917575 ps
CPU time 2.17 seconds
Started Jul 20 05:56:15 PM PDT 24
Finished Jul 20 05:56:19 PM PDT 24
Peak memory 201760 kb
Host smart-77005bd3-dc74-4dd7-8575-814e8fc87254
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062088858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.2062088858
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1191134838
Short name T862
Test name
Test status
Simulation time 3887760034 ps
CPU time 7.62 seconds
Started Jul 20 05:56:30 PM PDT 24
Finished Jul 20 05:56:41 PM PDT 24
Peak memory 201824 kb
Host smart-cedcbe9a-ebea-432e-a3af-9e8d46cee8d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191134838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.1191134838
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2733636226
Short name T820
Test name
Test status
Simulation time 487820943 ps
CPU time 1.25 seconds
Started Jul 20 05:56:25 PM PDT 24
Finished Jul 20 05:56:28 PM PDT 24
Peak memory 201588 kb
Host smart-5d441856-cca2-405d-96eb-4754ee5563ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733636226 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2733636226
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.4102365634
Short name T101
Test name
Test status
Simulation time 380425407 ps
CPU time 1.26 seconds
Started Jul 20 05:56:12 PM PDT 24
Finished Jul 20 05:56:15 PM PDT 24
Peak memory 201464 kb
Host smart-c9c26642-d638-4bb9-a067-1fa8824dbcb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102365634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.4102365634
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1095586648
Short name T802
Test name
Test status
Simulation time 410917137 ps
CPU time 1.6 seconds
Started Jul 20 05:56:30 PM PDT 24
Finished Jul 20 05:56:35 PM PDT 24
Peak memory 201352 kb
Host smart-e364d5d9-c56d-45ad-a525-03b121283ed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095586648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1095586648
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2787579389
Short name T47
Test name
Test status
Simulation time 3962357669 ps
CPU time 7.76 seconds
Started Jul 20 05:56:20 PM PDT 24
Finished Jul 20 05:56:29 PM PDT 24
Peak memory 201804 kb
Host smart-ba70160d-d9f6-4425-aa2b-371b8a01edbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787579389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2787579389
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1128751350
Short name T908
Test name
Test status
Simulation time 759676798 ps
CPU time 2.58 seconds
Started Jul 20 05:56:11 PM PDT 24
Finished Jul 20 05:56:14 PM PDT 24
Peak memory 211068 kb
Host smart-9d9a19d8-c8e4-4616-94f9-3b4d50bd326a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128751350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.1128751350
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2177149551
Short name T857
Test name
Test status
Simulation time 4682911966 ps
CPU time 4.39 seconds
Started Jul 20 05:56:31 PM PDT 24
Finished Jul 20 05:56:38 PM PDT 24
Peak memory 201744 kb
Host smart-68275ad5-0517-4d0d-a2bf-4cb0a2bcf6a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177149551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2177149551
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.903110479
Short name T867
Test name
Test status
Simulation time 456930968 ps
CPU time 1.52 seconds
Started Jul 20 05:56:25 PM PDT 24
Finished Jul 20 05:56:28 PM PDT 24
Peak memory 201720 kb
Host smart-31e17d32-b037-465f-8051-19942a043f34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903110479 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.903110479
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3774777654
Short name T824
Test name
Test status
Simulation time 644281984 ps
CPU time 0.82 seconds
Started Jul 20 05:56:23 PM PDT 24
Finished Jul 20 05:56:25 PM PDT 24
Peak memory 201420 kb
Host smart-9fb2d84a-14c1-4344-acbe-05077d5fafb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774777654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3774777654
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2640478966
Short name T800
Test name
Test status
Simulation time 439138488 ps
CPU time 1.14 seconds
Started Jul 20 05:56:22 PM PDT 24
Finished Jul 20 05:56:25 PM PDT 24
Peak memory 201364 kb
Host smart-59035c21-1326-4c06-8dd8-8399c31931cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640478966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2640478966
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2040264012
Short name T114
Test name
Test status
Simulation time 2529868267 ps
CPU time 6.07 seconds
Started Jul 20 05:56:20 PM PDT 24
Finished Jul 20 05:56:27 PM PDT 24
Peak memory 201572 kb
Host smart-8f33a196-fabf-4335-97e9-6efec0ba75f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040264012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.2040264012
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2516753621
Short name T826
Test name
Test status
Simulation time 545498906 ps
CPU time 4.25 seconds
Started Jul 20 05:56:28 PM PDT 24
Finished Jul 20 05:56:34 PM PDT 24
Peak memory 217688 kb
Host smart-da877ba0-5b8c-4ee2-82fa-d6bb8400ba54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516753621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2516753621
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1462803078
Short name T915
Test name
Test status
Simulation time 8459552784 ps
CPU time 6.94 seconds
Started Jul 20 05:56:30 PM PDT 24
Finished Jul 20 05:56:39 PM PDT 24
Peak memory 201760 kb
Host smart-595fb1d4-b631-441b-baed-ca30458d2606
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462803078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1462803078
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2136653868
Short name T917
Test name
Test status
Simulation time 358241784 ps
CPU time 1.21 seconds
Started Jul 20 05:56:20 PM PDT 24
Finished Jul 20 05:56:22 PM PDT 24
Peak memory 201584 kb
Host smart-dd82d9e4-3bb4-49b6-9f21-43b4cc40185a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136653868 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2136653868
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3071850319
Short name T891
Test name
Test status
Simulation time 491129515 ps
CPU time 1.13 seconds
Started Jul 20 05:56:18 PM PDT 24
Finished Jul 20 05:56:20 PM PDT 24
Peak memory 201444 kb
Host smart-03d1462f-430c-47d6-89fa-4600422a268b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071850319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3071850319
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3432864161
Short name T874
Test name
Test status
Simulation time 448924780 ps
CPU time 1.61 seconds
Started Jul 20 05:56:23 PM PDT 24
Finished Jul 20 05:56:26 PM PDT 24
Peak memory 201432 kb
Host smart-3ace8673-9697-459d-af25-6ef5407a712e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432864161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3432864161
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.734969559
Short name T848
Test name
Test status
Simulation time 2083075735 ps
CPU time 7.17 seconds
Started Jul 20 05:56:27 PM PDT 24
Finished Jul 20 05:56:35 PM PDT 24
Peak memory 201664 kb
Host smart-91d661b1-e560-422d-8f11-942308d91da3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734969559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_same_csr_outstanding.734969559
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2386752592
Short name T872
Test name
Test status
Simulation time 9606070676 ps
CPU time 3.95 seconds
Started Jul 20 05:56:21 PM PDT 24
Finished Jul 20 05:56:26 PM PDT 24
Peak memory 201796 kb
Host smart-9e95b542-b25f-4882-b102-8bc7844055d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386752592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2386752592
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.4045438151
Short name T853
Test name
Test status
Simulation time 461406018 ps
CPU time 1.34 seconds
Started Jul 20 05:56:27 PM PDT 24
Finished Jul 20 05:56:30 PM PDT 24
Peak memory 201640 kb
Host smart-6700dcd7-299a-4e4e-a6df-e1afda18ae28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045438151 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.4045438151
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3565933900
Short name T890
Test name
Test status
Simulation time 340277904 ps
CPU time 1.63 seconds
Started Jul 20 05:56:26 PM PDT 24
Finished Jul 20 05:56:29 PM PDT 24
Peak memory 201464 kb
Host smart-8f530453-5b53-4a01-bff8-d1e92440eb36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565933900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3565933900
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3580947293
Short name T814
Test name
Test status
Simulation time 502921467 ps
CPU time 1.76 seconds
Started Jul 20 05:56:19 PM PDT 24
Finished Jul 20 05:56:22 PM PDT 24
Peak memory 201380 kb
Host smart-ae6a779b-aa81-4173-9a9c-b26f5257d405
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580947293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3580947293
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.897028692
Short name T901
Test name
Test status
Simulation time 3593579290 ps
CPU time 15.57 seconds
Started Jul 20 05:56:30 PM PDT 24
Finished Jul 20 05:56:48 PM PDT 24
Peak memory 201820 kb
Host smart-6ae3c036-c401-44b0-9d3b-f8115056cf88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897028692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.897028692
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2866906380
Short name T849
Test name
Test status
Simulation time 710622205 ps
CPU time 1.41 seconds
Started Jul 20 05:56:19 PM PDT 24
Finished Jul 20 05:56:22 PM PDT 24
Peak memory 201812 kb
Host smart-4e74de54-cfd3-4ee0-aa85-6af60c98ad3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866906380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2866906380
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2844392848
Short name T54
Test name
Test status
Simulation time 4276727131 ps
CPU time 3.55 seconds
Started Jul 20 05:56:21 PM PDT 24
Finished Jul 20 05:56:27 PM PDT 24
Peak memory 201768 kb
Host smart-e307286a-d9d6-4733-808c-733ee4088897
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844392848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2844392848
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.533052108
Short name T106
Test name
Test status
Simulation time 826392302 ps
CPU time 3.38 seconds
Started Jul 20 05:56:06 PM PDT 24
Finished Jul 20 05:56:11 PM PDT 24
Peak memory 201644 kb
Host smart-ca852f51-95ea-438b-92b5-2965a93d03b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533052108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.533052108
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2499191175
Short name T100
Test name
Test status
Simulation time 49724342272 ps
CPU time 30.7 seconds
Started Jul 20 05:56:08 PM PDT 24
Finished Jul 20 05:56:41 PM PDT 24
Peak memory 201760 kb
Host smart-822310e7-cb32-4964-9ea7-5f91e64bf6ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499191175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2499191175
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.461365717
Short name T103
Test name
Test status
Simulation time 1165240544 ps
CPU time 3.62 seconds
Started Jul 20 05:56:11 PM PDT 24
Finished Jul 20 05:56:16 PM PDT 24
Peak memory 201444 kb
Host smart-39fbcb79-d15e-4d0a-8927-99465f724ed0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461365717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.461365717
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2368697079
Short name T83
Test name
Test status
Simulation time 738187888 ps
CPU time 1.42 seconds
Started Jul 20 05:56:12 PM PDT 24
Finished Jul 20 05:56:14 PM PDT 24
Peak memory 201564 kb
Host smart-f8f1ee5b-3ad1-4f8a-9d51-c98a8d164e34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368697079 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2368697079
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.465657500
Short name T870
Test name
Test status
Simulation time 476904339 ps
CPU time 1.8 seconds
Started Jul 20 05:56:03 PM PDT 24
Finished Jul 20 05:56:06 PM PDT 24
Peak memory 201460 kb
Host smart-53675be0-8733-43d8-b40c-ad5e8523af37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465657500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.465657500
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3630281586
Short name T856
Test name
Test status
Simulation time 535791520 ps
CPU time 0.76 seconds
Started Jul 20 05:56:07 PM PDT 24
Finished Jul 20 05:56:10 PM PDT 24
Peak memory 201460 kb
Host smart-231a9246-e250-46f5-864d-7c8237d0feb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630281586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3630281586
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.4151167799
Short name T864
Test name
Test status
Simulation time 2036003242 ps
CPU time 2.27 seconds
Started Jul 20 05:56:07 PM PDT 24
Finished Jul 20 05:56:11 PM PDT 24
Peak memory 201548 kb
Host smart-234135fb-aed2-43ff-81d7-8affcb520fe6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151167799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.4151167799
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1653132935
Short name T884
Test name
Test status
Simulation time 742572018 ps
CPU time 1.71 seconds
Started Jul 20 05:56:06 PM PDT 24
Finished Jul 20 05:56:09 PM PDT 24
Peak memory 201776 kb
Host smart-190591f1-fea3-44bf-a4d9-e8752f1ca84c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653132935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1653132935
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.578616524
Short name T95
Test name
Test status
Simulation time 4164379512 ps
CPU time 4.09 seconds
Started Jul 20 05:56:06 PM PDT 24
Finished Jul 20 05:56:12 PM PDT 24
Peak memory 201788 kb
Host smart-99fd1fd8-cd11-49be-9302-25b64440601a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578616524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.578616524
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2124345865
Short name T813
Test name
Test status
Simulation time 440142101 ps
CPU time 1.16 seconds
Started Jul 20 05:56:32 PM PDT 24
Finished Jul 20 05:56:36 PM PDT 24
Peak memory 201352 kb
Host smart-0b6e1467-d8d1-4c14-a442-f4770a84ce39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124345865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2124345865
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4227160260
Short name T880
Test name
Test status
Simulation time 408073788 ps
CPU time 1.2 seconds
Started Jul 20 05:56:34 PM PDT 24
Finished Jul 20 05:56:38 PM PDT 24
Peak memory 201428 kb
Host smart-98e4dbcc-c423-429c-9d81-65c6da360201
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227160260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.4227160260
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1683125218
Short name T808
Test name
Test status
Simulation time 315692033 ps
CPU time 0.81 seconds
Started Jul 20 05:56:31 PM PDT 24
Finished Jul 20 05:56:35 PM PDT 24
Peak memory 201376 kb
Host smart-acd9aaf1-4e8f-4748-a7d9-849293e1592a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683125218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1683125218
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1408469597
Short name T805
Test name
Test status
Simulation time 353416045 ps
CPU time 1.5 seconds
Started Jul 20 05:56:28 PM PDT 24
Finished Jul 20 05:56:31 PM PDT 24
Peak memory 201368 kb
Host smart-4089b8af-1334-48ed-90ba-e2c261075321
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408469597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1408469597
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2454492338
Short name T804
Test name
Test status
Simulation time 425119378 ps
CPU time 1.16 seconds
Started Jul 20 05:56:18 PM PDT 24
Finished Jul 20 05:56:20 PM PDT 24
Peak memory 201444 kb
Host smart-2f24e78f-a3f0-4367-9979-e3d7e0cb37c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454492338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2454492338
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2522904167
Short name T897
Test name
Test status
Simulation time 364921541 ps
CPU time 0.83 seconds
Started Jul 20 05:56:22 PM PDT 24
Finished Jul 20 05:56:25 PM PDT 24
Peak memory 201432 kb
Host smart-c715bd90-bbc2-4a6a-841d-18ba673ab301
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522904167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2522904167
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3308291711
Short name T876
Test name
Test status
Simulation time 424441246 ps
CPU time 1.17 seconds
Started Jul 20 05:56:22 PM PDT 24
Finished Jul 20 05:56:25 PM PDT 24
Peak memory 201444 kb
Host smart-42815403-6034-4182-af69-d44c20706d78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308291711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.3308291711
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.123457599
Short name T846
Test name
Test status
Simulation time 361003913 ps
CPU time 1.05 seconds
Started Jul 20 05:56:23 PM PDT 24
Finished Jul 20 05:56:26 PM PDT 24
Peak memory 201468 kb
Host smart-f3f509b7-c7e6-46b4-bf82-40272fea720f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123457599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.123457599
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2017256807
Short name T801
Test name
Test status
Simulation time 540195892 ps
CPU time 1.13 seconds
Started Jul 20 05:56:21 PM PDT 24
Finished Jul 20 05:56:23 PM PDT 24
Peak memory 201428 kb
Host smart-c8358501-016f-423a-8db9-75410bfb8e47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017256807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2017256807
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2533990343
Short name T913
Test name
Test status
Simulation time 355555512 ps
CPU time 1.49 seconds
Started Jul 20 05:56:30 PM PDT 24
Finished Jul 20 05:56:34 PM PDT 24
Peak memory 201352 kb
Host smart-c124c168-1fc9-4138-8d10-d1bf04d301bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533990343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2533990343
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3776578604
Short name T99
Test name
Test status
Simulation time 1035785349 ps
CPU time 4.4 seconds
Started Jul 20 05:56:08 PM PDT 24
Finished Jul 20 05:56:14 PM PDT 24
Peak memory 201648 kb
Host smart-5bffce2a-4197-4b0a-9f67-58a4c50c6f98
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776578604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3776578604
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3244156572
Short name T110
Test name
Test status
Simulation time 24558503653 ps
CPU time 84.99 seconds
Started Jul 20 05:56:08 PM PDT 24
Finished Jul 20 05:57:35 PM PDT 24
Peak memory 201708 kb
Host smart-2cbfbb9d-71ec-4275-a0ee-5c788ae405e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244156572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3244156572
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1445555711
Short name T102
Test name
Test status
Simulation time 1009632807 ps
CPU time 3.27 seconds
Started Jul 20 05:56:06 PM PDT 24
Finished Jul 20 05:56:11 PM PDT 24
Peak memory 201484 kb
Host smart-aae84f7f-543d-4deb-895c-e332223a24af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445555711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1445555711
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4231455016
Short name T845
Test name
Test status
Simulation time 505693228 ps
CPU time 1.13 seconds
Started Jul 20 05:56:12 PM PDT 24
Finished Jul 20 05:56:14 PM PDT 24
Peak memory 201524 kb
Host smart-dfa2a468-525c-48b1-9cd4-6d2e0132d3dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231455016 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.4231455016
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.891383898
Short name T893
Test name
Test status
Simulation time 468498882 ps
CPU time 1.77 seconds
Started Jul 20 05:56:06 PM PDT 24
Finished Jul 20 05:56:10 PM PDT 24
Peak memory 201436 kb
Host smart-df121b16-5cc8-441d-89f6-1ff63efea29f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891383898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.891383898
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2082340354
Short name T896
Test name
Test status
Simulation time 322673288 ps
CPU time 1.02 seconds
Started Jul 20 05:56:11 PM PDT 24
Finished Jul 20 05:56:13 PM PDT 24
Peak memory 201436 kb
Host smart-53550d57-bd75-4daa-9384-473ad6d60fab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082340354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2082340354
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3171828226
Short name T899
Test name
Test status
Simulation time 4622931402 ps
CPU time 5.72 seconds
Started Jul 20 05:56:10 PM PDT 24
Finished Jul 20 05:56:16 PM PDT 24
Peak memory 201792 kb
Host smart-363b125b-dbc6-4fc8-b5d4-37da02c32dc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171828226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3171828226
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.187908278
Short name T889
Test name
Test status
Simulation time 363537153 ps
CPU time 2.23 seconds
Started Jul 20 05:56:05 PM PDT 24
Finished Jul 20 05:56:09 PM PDT 24
Peak memory 201832 kb
Host smart-f1c6dec7-e8ed-4bc6-bad4-4ca66a45a8c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187908278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.187908278
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.119700460
Short name T52
Test name
Test status
Simulation time 4341734383 ps
CPU time 11.9 seconds
Started Jul 20 05:56:07 PM PDT 24
Finished Jul 20 05:56:21 PM PDT 24
Peak memory 201724 kb
Host smart-9153d469-b449-4e78-b587-d00749d7766c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119700460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.119700460
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3390457389
Short name T900
Test name
Test status
Simulation time 347693898 ps
CPU time 0.86 seconds
Started Jul 20 05:56:22 PM PDT 24
Finished Jul 20 05:56:24 PM PDT 24
Peak memory 201376 kb
Host smart-d6223f34-5bf3-442b-966f-bdd6dde1265e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390457389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3390457389
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1716555004
Short name T858
Test name
Test status
Simulation time 437865868 ps
CPU time 0.92 seconds
Started Jul 20 05:56:24 PM PDT 24
Finished Jul 20 05:56:27 PM PDT 24
Peak memory 201484 kb
Host smart-69246ab2-7fcf-4f8e-be33-ad3b788a26b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716555004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1716555004
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.462333369
Short name T811
Test name
Test status
Simulation time 502575729 ps
CPU time 0.85 seconds
Started Jul 20 05:56:29 PM PDT 24
Finished Jul 20 05:56:32 PM PDT 24
Peak memory 201428 kb
Host smart-a05aee13-b16e-458b-a00c-d9294f9f669c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462333369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.462333369
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1740487222
Short name T822
Test name
Test status
Simulation time 523790216 ps
CPU time 0.76 seconds
Started Jul 20 05:56:20 PM PDT 24
Finished Jul 20 05:56:21 PM PDT 24
Peak memory 201416 kb
Host smart-2e0267a7-95ae-4f82-aab7-f135288012ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740487222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1740487222
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.4280243517
Short name T812
Test name
Test status
Simulation time 402423581 ps
CPU time 1.39 seconds
Started Jul 20 05:56:23 PM PDT 24
Finished Jul 20 05:56:26 PM PDT 24
Peak memory 201428 kb
Host smart-99f58eb3-908a-4e41-b404-db6472016411
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280243517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.4280243517
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2834196946
Short name T798
Test name
Test status
Simulation time 472972555 ps
CPU time 1.26 seconds
Started Jul 20 05:56:24 PM PDT 24
Finished Jul 20 05:56:28 PM PDT 24
Peak memory 201480 kb
Host smart-bfa614bb-aa23-4b98-8cf5-05fe297996a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834196946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2834196946
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1231483472
Short name T832
Test name
Test status
Simulation time 390536871 ps
CPU time 0.82 seconds
Started Jul 20 05:56:27 PM PDT 24
Finished Jul 20 05:56:30 PM PDT 24
Peak memory 201392 kb
Host smart-f35b8bd5-10fd-4038-a062-db99e013b840
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231483472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1231483472
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.730693691
Short name T825
Test name
Test status
Simulation time 422035869 ps
CPU time 1.65 seconds
Started Jul 20 05:56:31 PM PDT 24
Finished Jul 20 05:56:36 PM PDT 24
Peak memory 201440 kb
Host smart-19a2c090-69d6-4e0c-8f96-796508a7f48a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730693691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.730693691
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1750630912
Short name T806
Test name
Test status
Simulation time 429093428 ps
CPU time 1.51 seconds
Started Jul 20 05:56:21 PM PDT 24
Finished Jul 20 05:56:24 PM PDT 24
Peak memory 201456 kb
Host smart-126cd8fd-a347-46fa-8673-8f45ed2ec8fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750630912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1750630912
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.742641271
Short name T799
Test name
Test status
Simulation time 407991476 ps
CPU time 1.04 seconds
Started Jul 20 05:56:32 PM PDT 24
Finished Jul 20 05:56:36 PM PDT 24
Peak memory 201460 kb
Host smart-95212b4a-1e1d-424a-b59f-02f0f185dc97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742641271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.742641271
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.276765987
Short name T111
Test name
Test status
Simulation time 677212544 ps
CPU time 3.72 seconds
Started Jul 20 05:56:03 PM PDT 24
Finished Jul 20 05:56:08 PM PDT 24
Peak memory 201644 kb
Host smart-caf66c0b-4d18-477d-bf30-c134058517b6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276765987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.276765987
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3008168293
Short name T113
Test name
Test status
Simulation time 42547246067 ps
CPU time 53.12 seconds
Started Jul 20 05:56:08 PM PDT 24
Finished Jul 20 05:57:03 PM PDT 24
Peak memory 201736 kb
Host smart-e59cade6-6cf3-42c5-8f8e-442e204edd5f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008168293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3008168293
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.354209833
Short name T117
Test name
Test status
Simulation time 1285423747 ps
CPU time 2.33 seconds
Started Jul 20 05:56:05 PM PDT 24
Finished Jul 20 05:56:08 PM PDT 24
Peak memory 201384 kb
Host smart-21f928de-63fa-4964-a128-215817ef8c47
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354209833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_re
set.354209833
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3131701782
Short name T911
Test name
Test status
Simulation time 544119265 ps
CPU time 1.35 seconds
Started Jul 20 05:56:07 PM PDT 24
Finished Jul 20 05:56:11 PM PDT 24
Peak memory 201528 kb
Host smart-76be0696-8916-4be4-935d-2d5ccf27cfe6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131701782 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3131701782
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2313241457
Short name T904
Test name
Test status
Simulation time 391614950 ps
CPU time 1.1 seconds
Started Jul 20 05:56:23 PM PDT 24
Finished Jul 20 05:56:26 PM PDT 24
Peak memory 201400 kb
Host smart-8edb3b79-35fc-460a-8222-8a562de54364
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313241457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.2313241457
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.545226195
Short name T861
Test name
Test status
Simulation time 440280692 ps
CPU time 1.7 seconds
Started Jul 20 05:56:13 PM PDT 24
Finished Jul 20 05:56:16 PM PDT 24
Peak memory 201392 kb
Host smart-6e75ae16-64c5-4d04-8509-2cf6de6059f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545226195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.545226195
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.140971992
Short name T910
Test name
Test status
Simulation time 2720706547 ps
CPU time 7.05 seconds
Started Jul 20 05:56:06 PM PDT 24
Finished Jul 20 05:56:15 PM PDT 24
Peak memory 201572 kb
Host smart-f52f9b0d-acbe-46c3-91be-e8f59dab107d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140971992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.140971992
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1579036553
Short name T875
Test name
Test status
Simulation time 527440204 ps
CPU time 1.75 seconds
Started Jul 20 05:56:07 PM PDT 24
Finished Jul 20 05:56:11 PM PDT 24
Peak memory 201804 kb
Host smart-3f959fa3-8add-4499-9718-0f472a7cc903
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579036553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1579036553
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1898241782
Short name T69
Test name
Test status
Simulation time 8528970932 ps
CPU time 5.99 seconds
Started Jul 20 05:56:10 PM PDT 24
Finished Jul 20 05:56:22 PM PDT 24
Peak memory 201788 kb
Host smart-9de645b9-7850-45f2-82a1-dfb117130903
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898241782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1898241782
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3029688836
Short name T909
Test name
Test status
Simulation time 540075197 ps
CPU time 0.96 seconds
Started Jul 20 05:56:20 PM PDT 24
Finished Jul 20 05:56:22 PM PDT 24
Peak memory 201416 kb
Host smart-393152e1-6cb3-4431-aea0-c171d8f44765
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029688836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3029688836
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.859619607
Short name T868
Test name
Test status
Simulation time 423574755 ps
CPU time 0.88 seconds
Started Jul 20 05:56:21 PM PDT 24
Finished Jul 20 05:56:24 PM PDT 24
Peak memory 201420 kb
Host smart-a70bf523-fb26-48ba-b6c1-643e39e8d41b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859619607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.859619607
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3842090312
Short name T914
Test name
Test status
Simulation time 618094985 ps
CPU time 0.79 seconds
Started Jul 20 05:56:26 PM PDT 24
Finished Jul 20 05:56:28 PM PDT 24
Peak memory 201428 kb
Host smart-91b1c99a-3b49-4967-8313-89ca1e583c22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842090312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3842090312
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.369845665
Short name T905
Test name
Test status
Simulation time 422422293 ps
CPU time 1.17 seconds
Started Jul 20 05:56:22 PM PDT 24
Finished Jul 20 05:56:25 PM PDT 24
Peak memory 201464 kb
Host smart-41cbd304-4251-46f5-b9f9-c97637a1e9ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369845665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.369845665
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3633122049
Short name T817
Test name
Test status
Simulation time 436741768 ps
CPU time 1.63 seconds
Started Jul 20 05:56:30 PM PDT 24
Finished Jul 20 05:56:34 PM PDT 24
Peak memory 201456 kb
Host smart-66edf905-a72f-49da-99f2-6d90e05db882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633122049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3633122049
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2212969157
Short name T831
Test name
Test status
Simulation time 336397356 ps
CPU time 0.77 seconds
Started Jul 20 05:56:28 PM PDT 24
Finished Jul 20 05:56:30 PM PDT 24
Peak memory 201396 kb
Host smart-ea5eb862-c7f3-4d5e-b774-94b06e1ed540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212969157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2212969157
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3474612687
Short name T815
Test name
Test status
Simulation time 505434743 ps
CPU time 1.8 seconds
Started Jul 20 05:56:32 PM PDT 24
Finished Jul 20 05:56:37 PM PDT 24
Peak memory 201432 kb
Host smart-7f6ebdfd-8609-4524-833b-d741e5260905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474612687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3474612687
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3941084880
Short name T819
Test name
Test status
Simulation time 592095878 ps
CPU time 0.75 seconds
Started Jul 20 05:56:31 PM PDT 24
Finished Jul 20 05:56:35 PM PDT 24
Peak memory 201428 kb
Host smart-da6c862d-fdee-4be0-a5bd-29dc051139b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941084880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3941084880
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3481230922
Short name T823
Test name
Test status
Simulation time 301775431 ps
CPU time 0.84 seconds
Started Jul 20 05:56:21 PM PDT 24
Finished Jul 20 05:56:23 PM PDT 24
Peak memory 201416 kb
Host smart-70e679eb-f815-4506-bb84-d46fe077b0fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481230922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3481230922
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3278893245
Short name T842
Test name
Test status
Simulation time 375074715 ps
CPU time 1.49 seconds
Started Jul 20 05:56:21 PM PDT 24
Finished Jul 20 05:56:24 PM PDT 24
Peak memory 201424 kb
Host smart-87b667ba-b2de-4bea-9086-0629d12380e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278893245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3278893245
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2942527695
Short name T850
Test name
Test status
Simulation time 440919022 ps
CPU time 1.68 seconds
Started Jul 20 05:56:06 PM PDT 24
Finished Jul 20 05:56:09 PM PDT 24
Peak memory 201588 kb
Host smart-ee52b42d-9064-40d1-88e7-1c918b9a6e0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942527695 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2942527695
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2270396302
Short name T918
Test name
Test status
Simulation time 571779386 ps
CPU time 1.14 seconds
Started Jul 20 05:56:03 PM PDT 24
Finished Jul 20 05:56:05 PM PDT 24
Peak memory 201400 kb
Host smart-181caea1-9f9d-41d7-a5e6-6d545612fc87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270396302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2270396302
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.141324329
Short name T818
Test name
Test status
Simulation time 480204359 ps
CPU time 1.81 seconds
Started Jul 20 05:56:17 PM PDT 24
Finished Jul 20 05:56:20 PM PDT 24
Peak memory 201392 kb
Host smart-6827e805-60a3-4f98-8623-d1e1f4727406
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141324329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.141324329
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.4223432923
Short name T847
Test name
Test status
Simulation time 2052101390 ps
CPU time 2.74 seconds
Started Jul 20 05:56:07 PM PDT 24
Finished Jul 20 05:56:12 PM PDT 24
Peak memory 201500 kb
Host smart-d9612440-290c-494d-95b7-6d343868569f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223432923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.4223432923
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3593854237
Short name T902
Test name
Test status
Simulation time 718693744 ps
CPU time 1.77 seconds
Started Jul 20 05:56:05 PM PDT 24
Finished Jul 20 05:56:08 PM PDT 24
Peak memory 201700 kb
Host smart-4e5745f5-7c48-47bd-bb15-d185ebfed3e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593854237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3593854237
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.472527890
Short name T58
Test name
Test status
Simulation time 8107049474 ps
CPU time 20.17 seconds
Started Jul 20 05:56:13 PM PDT 24
Finished Jul 20 05:56:34 PM PDT 24
Peak memory 201756 kb
Host smart-b696385d-f6c9-41e6-9aff-4aacd0d6075a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472527890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.472527890
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.412944824
Short name T84
Test name
Test status
Simulation time 602885364 ps
CPU time 1.59 seconds
Started Jul 20 05:56:04 PM PDT 24
Finished Jul 20 05:56:06 PM PDT 24
Peak memory 201712 kb
Host smart-6fd7087b-63d1-4874-883e-7c9dfa961ae3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412944824 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.412944824
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.864794777
Short name T837
Test name
Test status
Simulation time 363152190 ps
CPU time 0.82 seconds
Started Jul 20 05:56:09 PM PDT 24
Finished Jul 20 05:56:11 PM PDT 24
Peak memory 201372 kb
Host smart-d744c0cd-f659-4dc7-9bdb-77696dea8f64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864794777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.864794777
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1729740099
Short name T866
Test name
Test status
Simulation time 302422944 ps
CPU time 0.82 seconds
Started Jul 20 05:56:08 PM PDT 24
Finished Jul 20 05:56:11 PM PDT 24
Peak memory 201424 kb
Host smart-abebb607-45af-48dc-8f1c-2ff8d32db5df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729740099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1729740099
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3688321365
Short name T44
Test name
Test status
Simulation time 2543440653 ps
CPU time 3.13 seconds
Started Jul 20 05:56:06 PM PDT 24
Finished Jul 20 05:56:12 PM PDT 24
Peak memory 201556 kb
Host smart-cdc01355-cda2-4ef4-bf63-85b022ff45c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688321365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3688321365
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1004467038
Short name T68
Test name
Test status
Simulation time 559133607 ps
CPU time 1.78 seconds
Started Jul 20 05:56:06 PM PDT 24
Finished Jul 20 05:56:09 PM PDT 24
Peak memory 201760 kb
Host smart-cd4a3a26-c457-4e63-9728-d8d3f755933e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004467038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1004467038
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3762228276
Short name T53
Test name
Test status
Simulation time 4405535347 ps
CPU time 4.04 seconds
Started Jul 20 05:56:05 PM PDT 24
Finished Jul 20 05:56:11 PM PDT 24
Peak memory 201804 kb
Host smart-334b4941-c5d5-4499-9e2e-7c42041e2e88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762228276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3762228276
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3056386106
Short name T873
Test name
Test status
Simulation time 456844624 ps
CPU time 1.51 seconds
Started Jul 20 05:56:15 PM PDT 24
Finished Jul 20 05:56:18 PM PDT 24
Peak memory 201588 kb
Host smart-fa90b596-bda2-483d-a0d9-3329c5fa8879
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056386106 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3056386106
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1060365322
Short name T105
Test name
Test status
Simulation time 380080978 ps
CPU time 1.72 seconds
Started Jul 20 05:56:13 PM PDT 24
Finished Jul 20 05:56:16 PM PDT 24
Peak memory 201432 kb
Host smart-fd4e2fed-faed-40d4-aec2-925cd9efbbd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060365322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1060365322
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1906979989
Short name T878
Test name
Test status
Simulation time 407994948 ps
CPU time 0.71 seconds
Started Jul 20 05:56:18 PM PDT 24
Finished Jul 20 05:56:20 PM PDT 24
Peak memory 201496 kb
Host smart-ea2bce27-367d-4fe2-9cb2-839292218479
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906979989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1906979989
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.972930592
Short name T116
Test name
Test status
Simulation time 4238431027 ps
CPU time 10.71 seconds
Started Jul 20 05:56:11 PM PDT 24
Finished Jul 20 05:56:23 PM PDT 24
Peak memory 201760 kb
Host smart-eab464bf-6721-4a59-9acb-754bc58c5d08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972930592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct
rl_same_csr_outstanding.972930592
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1674267102
Short name T66
Test name
Test status
Simulation time 381387616 ps
CPU time 1.86 seconds
Started Jul 20 05:56:06 PM PDT 24
Finished Jul 20 05:56:09 PM PDT 24
Peak memory 201740 kb
Host smart-88772baa-8d42-4358-bdda-caeb3f18b3a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674267102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1674267102
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1577948611
Short name T93
Test name
Test status
Simulation time 4311695992 ps
CPU time 4.27 seconds
Started Jul 20 05:56:13 PM PDT 24
Finished Jul 20 05:56:19 PM PDT 24
Peak memory 201756 kb
Host smart-cd88dc08-c601-422b-954d-290be51913ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577948611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1577948611
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.216838087
Short name T894
Test name
Test status
Simulation time 430658032 ps
CPU time 1.94 seconds
Started Jul 20 05:56:17 PM PDT 24
Finished Jul 20 05:56:20 PM PDT 24
Peak memory 201604 kb
Host smart-dffb0a2a-f89a-4018-9030-d2cf55c55450
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216838087 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.216838087
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.918669790
Short name T919
Test name
Test status
Simulation time 381969250 ps
CPU time 1.79 seconds
Started Jul 20 05:56:17 PM PDT 24
Finished Jul 20 05:56:20 PM PDT 24
Peak memory 201464 kb
Host smart-764c0acd-d786-4de2-9499-2f4bef0647a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918669790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.918669790
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3981727876
Short name T807
Test name
Test status
Simulation time 557180277 ps
CPU time 0.94 seconds
Started Jul 20 05:56:12 PM PDT 24
Finished Jul 20 05:56:15 PM PDT 24
Peak memory 201428 kb
Host smart-5ad6079a-fa81-49b7-a7b0-e9da3b4388cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981727876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3981727876
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.4049237747
Short name T841
Test name
Test status
Simulation time 2420649765 ps
CPU time 8.5 seconds
Started Jul 20 05:56:12 PM PDT 24
Finished Jul 20 05:56:22 PM PDT 24
Peak memory 201576 kb
Host smart-37944ad4-c3b9-454d-a3d6-609f172d92c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049237747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.4049237747
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1398376919
Short name T886
Test name
Test status
Simulation time 517080081 ps
CPU time 1.72 seconds
Started Jul 20 05:56:16 PM PDT 24
Finished Jul 20 05:56:19 PM PDT 24
Peak memory 201768 kb
Host smart-68bf56d7-4d74-4878-9fef-03224456c6bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398376919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1398376919
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.482193252
Short name T830
Test name
Test status
Simulation time 8550195594 ps
CPU time 22.23 seconds
Started Jul 20 05:56:13 PM PDT 24
Finished Jul 20 05:56:37 PM PDT 24
Peak memory 201676 kb
Host smart-671d3c34-9cbd-4b36-807c-f0bd88c4aa0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482193252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_int
g_err.482193252
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2099562841
Short name T859
Test name
Test status
Simulation time 500060640 ps
CPU time 2.12 seconds
Started Jul 20 05:56:11 PM PDT 24
Finished Jul 20 05:56:14 PM PDT 24
Peak memory 201580 kb
Host smart-f495654c-4618-4149-b708-0f12c33f28df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099562841 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2099562841
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4073932115
Short name T881
Test name
Test status
Simulation time 465459018 ps
CPU time 1.03 seconds
Started Jul 20 05:56:11 PM PDT 24
Finished Jul 20 05:56:14 PM PDT 24
Peak memory 201460 kb
Host smart-ba72e818-2d81-4554-9a49-ff2975298189
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073932115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.4073932115
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3847652548
Short name T810
Test name
Test status
Simulation time 533469844 ps
CPU time 0.76 seconds
Started Jul 20 05:56:17 PM PDT 24
Finished Jul 20 05:56:19 PM PDT 24
Peak memory 201432 kb
Host smart-c1be9577-b9c8-43d6-af65-584680db7828
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847652548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3847652548
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2947391715
Short name T46
Test name
Test status
Simulation time 3181608591 ps
CPU time 7.86 seconds
Started Jul 20 05:56:13 PM PDT 24
Finished Jul 20 05:56:22 PM PDT 24
Peak memory 201736 kb
Host smart-02d23367-46ad-4791-a30d-c63ff264c57c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947391715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2947391715
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1776575963
Short name T916
Test name
Test status
Simulation time 493403777 ps
CPU time 2.24 seconds
Started Jul 20 05:56:15 PM PDT 24
Finished Jul 20 05:56:18 PM PDT 24
Peak memory 201820 kb
Host smart-2b29c0ae-419e-4f67-aa2a-60d70e69b30b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776575963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1776575963
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3676771212
Short name T833
Test name
Test status
Simulation time 3776983280 ps
CPU time 9.45 seconds
Started Jul 20 05:56:17 PM PDT 24
Finished Jul 20 05:56:27 PM PDT 24
Peak memory 201792 kb
Host smart-8845b66d-5592-4baf-a508-025b133d364e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676771212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3676771212
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1865067702
Short name T787
Test name
Test status
Simulation time 482353222 ps
CPU time 1.79 seconds
Started Jul 20 05:56:30 PM PDT 24
Finished Jul 20 05:56:35 PM PDT 24
Peak memory 201536 kb
Host smart-8bade5cf-d1e9-495f-be37-3323e29ca45b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865067702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1865067702
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.810281143
Short name T218
Test name
Test status
Simulation time 503721335672 ps
CPU time 295.73 seconds
Started Jul 20 05:56:34 PM PDT 24
Finished Jul 20 06:01:33 PM PDT 24
Peak memory 201820 kb
Host smart-b3d2dfa9-2719-48e4-8b95-9d80a3f8f561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810281143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.810281143
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.4040912473
Short name T722
Test name
Test status
Simulation time 165745966036 ps
CPU time 52.86 seconds
Started Jul 20 05:56:30 PM PDT 24
Finished Jul 20 05:57:25 PM PDT 24
Peak memory 201724 kb
Host smart-ce8b90d3-9855-4dde-b9fd-6552c541cbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040912473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.4040912473
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3824266375
Short name T693
Test name
Test status
Simulation time 498088642050 ps
CPU time 95.34 seconds
Started Jul 20 05:56:20 PM PDT 24
Finished Jul 20 05:57:56 PM PDT 24
Peak memory 201716 kb
Host smart-98d5376a-ee20-4bf5-80d1-b866253e4438
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824266375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.3824266375
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3144784770
Short name T634
Test name
Test status
Simulation time 329203101823 ps
CPU time 744.73 seconds
Started Jul 20 05:56:24 PM PDT 24
Finished Jul 20 06:08:51 PM PDT 24
Peak memory 201752 kb
Host smart-787948a4-9832-479a-9ffe-8ad1fb8f3dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144784770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3144784770
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3422127710
Short name T177
Test name
Test status
Simulation time 487999213639 ps
CPU time 414.06 seconds
Started Jul 20 05:56:31 PM PDT 24
Finished Jul 20 06:03:28 PM PDT 24
Peak memory 201612 kb
Host smart-4e74c2ae-848d-434d-85e6-afda243def57
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422127710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3422127710
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1807766831
Short name T11
Test name
Test status
Simulation time 230175567479 ps
CPU time 505.99 seconds
Started Jul 20 05:56:28 PM PDT 24
Finished Jul 20 06:04:55 PM PDT 24
Peak memory 201640 kb
Host smart-9e704ca1-2ba4-43e1-9094-26c3bad5cd72
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807766831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1807766831
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2981795682
Short name T623
Test name
Test status
Simulation time 196995316335 ps
CPU time 126.97 seconds
Started Jul 20 05:56:22 PM PDT 24
Finished Jul 20 05:58:31 PM PDT 24
Peak memory 201700 kb
Host smart-1cb8949d-fc70-40dc-8519-58db76732313
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981795682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2981795682
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1468135527
Short name T742
Test name
Test status
Simulation time 90486285921 ps
CPU time 503.76 seconds
Started Jul 20 05:56:30 PM PDT 24
Finished Jul 20 06:04:57 PM PDT 24
Peak memory 202116 kb
Host smart-fb06bd1b-b1f1-460e-88ad-688532b9f258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468135527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1468135527
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2957511463
Short name T627
Test name
Test status
Simulation time 33598869809 ps
CPU time 30.02 seconds
Started Jul 20 05:56:28 PM PDT 24
Finished Jul 20 05:56:59 PM PDT 24
Peak memory 201584 kb
Host smart-ab0c64c1-5dc7-4a36-ab2f-f0f55d1ecf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957511463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2957511463
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3756707410
Short name T434
Test name
Test status
Simulation time 4341363704 ps
CPU time 11.51 seconds
Started Jul 20 05:56:25 PM PDT 24
Finished Jul 20 05:56:38 PM PDT 24
Peak memory 201564 kb
Host smart-83cb03d7-fb13-4606-b731-44d74705db7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756707410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3756707410
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1944096169
Short name T4
Test name
Test status
Simulation time 5756051181 ps
CPU time 16.24 seconds
Started Jul 20 05:56:33 PM PDT 24
Finished Jul 20 05:56:52 PM PDT 24
Peak memory 201544 kb
Host smart-2bfbd442-d785-45c3-8921-f0055de54724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944096169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1944096169
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2563895824
Short name T514
Test name
Test status
Simulation time 200579788632 ps
CPU time 259.69 seconds
Started Jul 20 05:56:27 PM PDT 24
Finished Jul 20 06:00:48 PM PDT 24
Peak memory 201728 kb
Host smart-045a8599-c653-4f35-9243-a59088b04949
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563895824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2563895824
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2753813541
Short name T657
Test name
Test status
Simulation time 326943738 ps
CPU time 0.86 seconds
Started Jul 20 05:56:39 PM PDT 24
Finished Jul 20 05:56:41 PM PDT 24
Peak memory 201540 kb
Host smart-df29b2d8-8eba-4662-9f55-06511e279ca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753813541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2753813541
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.808965135
Short name T132
Test name
Test status
Simulation time 377750127824 ps
CPU time 232.44 seconds
Started Jul 20 05:56:38 PM PDT 24
Finished Jul 20 06:00:32 PM PDT 24
Peak memory 201732 kb
Host smart-b31fafc1-1079-4109-a6bc-243e3d4c98bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808965135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.808965135
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.870789354
Short name T353
Test name
Test status
Simulation time 164292402168 ps
CPU time 105.96 seconds
Started Jul 20 05:56:29 PM PDT 24
Finished Jul 20 05:58:17 PM PDT 24
Peak memory 201716 kb
Host smart-5889c6d5-1da8-4bb1-9a32-c4834e0434ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=870789354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt
_fixed.870789354
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1713510568
Short name T330
Test name
Test status
Simulation time 493435488217 ps
CPU time 1028.49 seconds
Started Jul 20 05:56:32 PM PDT 24
Finished Jul 20 06:13:44 PM PDT 24
Peak memory 201652 kb
Host smart-1af89710-2458-46f0-8944-d82b3f4a89c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713510568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1713510568
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2237320755
Short name T549
Test name
Test status
Simulation time 329459501027 ps
CPU time 400 seconds
Started Jul 20 05:56:23 PM PDT 24
Finished Jul 20 06:03:05 PM PDT 24
Peak memory 201792 kb
Host smart-77e5441a-321c-4be4-9837-fa3be8acd549
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237320755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2237320755
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.127365116
Short name T612
Test name
Test status
Simulation time 170821109092 ps
CPU time 378.76 seconds
Started Jul 20 05:56:22 PM PDT 24
Finished Jul 20 06:02:42 PM PDT 24
Peak memory 201620 kb
Host smart-97da3120-27b3-43d7-ad5f-172d0ae012bc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127365116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.127365116
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2685177212
Short name T592
Test name
Test status
Simulation time 190614285766 ps
CPU time 394.51 seconds
Started Jul 20 05:56:33 PM PDT 24
Finished Jul 20 06:03:10 PM PDT 24
Peak memory 201724 kb
Host smart-9aca9315-a62e-494c-bf4c-ffe2a386d2c0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685177212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2685177212
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3847672237
Short name T796
Test name
Test status
Simulation time 71761915607 ps
CPU time 215.1 seconds
Started Jul 20 05:56:35 PM PDT 24
Finished Jul 20 06:00:13 PM PDT 24
Peak memory 202112 kb
Host smart-9f16e56e-1fa5-40eb-8513-7a073c1fec89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847672237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3847672237
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.3586326669
Short name T579
Test name
Test status
Simulation time 36899098976 ps
CPU time 45.34 seconds
Started Jul 20 05:56:36 PM PDT 24
Finished Jul 20 05:57:24 PM PDT 24
Peak memory 201592 kb
Host smart-dd4cf2d7-4bd4-4471-9c43-e3a53c951100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586326669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3586326669
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2669496841
Short name T428
Test name
Test status
Simulation time 5467510479 ps
CPU time 12.01 seconds
Started Jul 20 05:56:42 PM PDT 24
Finished Jul 20 05:56:55 PM PDT 24
Peak memory 201604 kb
Host smart-da8b652b-3d39-4946-81d7-b49f5dfd9e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669496841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2669496841
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3486163060
Short name T59
Test name
Test status
Simulation time 3845930009 ps
CPU time 9.14 seconds
Started Jul 20 05:56:30 PM PDT 24
Finished Jul 20 05:56:42 PM PDT 24
Peak memory 217224 kb
Host smart-4147b541-e881-45ca-b722-41e0cee6daf3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486163060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3486163060
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.4056476185
Short name T646
Test name
Test status
Simulation time 5546799689 ps
CPU time 5.07 seconds
Started Jul 20 05:56:25 PM PDT 24
Finished Jul 20 05:56:31 PM PDT 24
Peak memory 201576 kb
Host smart-2e164295-0558-46d9-af20-e22b611cca99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056476185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.4056476185
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1339585086
Short name T447
Test name
Test status
Simulation time 32928516762 ps
CPU time 20.47 seconds
Started Jul 20 05:56:36 PM PDT 24
Finished Jul 20 05:56:59 PM PDT 24
Peak memory 201600 kb
Host smart-85a03208-7619-4563-a9b1-9bdd7902aab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339585086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1339585086
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1344616385
Short name T55
Test name
Test status
Simulation time 59848730384 ps
CPU time 38.39 seconds
Started Jul 20 05:56:33 PM PDT 24
Finished Jul 20 05:57:14 PM PDT 24
Peak memory 210036 kb
Host smart-6d55c5fa-9973-44db-8e44-5f5b255287bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344616385 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1344616385
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1154829315
Short name T644
Test name
Test status
Simulation time 523110338 ps
CPU time 1.16 seconds
Started Jul 20 05:56:45 PM PDT 24
Finished Jul 20 05:56:47 PM PDT 24
Peak memory 201668 kb
Host smart-04221be5-9dc1-4cfd-a2fd-cd3841861ec4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154829315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1154829315
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2841620915
Short name T211
Test name
Test status
Simulation time 213862302159 ps
CPU time 118.84 seconds
Started Jul 20 05:56:41 PM PDT 24
Finished Jul 20 05:58:41 PM PDT 24
Peak memory 201816 kb
Host smart-1859c558-ca0d-42c8-a33d-2b7a81d38765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841620915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2841620915
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1722276440
Short name T570
Test name
Test status
Simulation time 165260074470 ps
CPU time 368.39 seconds
Started Jul 20 05:56:47 PM PDT 24
Finished Jul 20 06:02:58 PM PDT 24
Peak memory 201744 kb
Host smart-cf5f07a1-b9ff-4a19-b8e1-47cae8ff70c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722276440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1722276440
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2657972117
Short name T669
Test name
Test status
Simulation time 163991403720 ps
CPU time 103.86 seconds
Started Jul 20 05:56:48 PM PDT 24
Finished Jul 20 05:58:34 PM PDT 24
Peak memory 201712 kb
Host smart-1e62040f-63a3-4da4-a621-7270414b087f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657972117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2657972117
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.1668898596
Short name T505
Test name
Test status
Simulation time 163706048272 ps
CPU time 92.22 seconds
Started Jul 20 05:56:47 PM PDT 24
Finished Jul 20 05:58:22 PM PDT 24
Peak memory 201740 kb
Host smart-616b65c1-5df7-4749-bf86-96cd31982c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668898596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1668898596
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.269428209
Short name T437
Test name
Test status
Simulation time 160804405768 ps
CPU time 94.42 seconds
Started Jul 20 05:56:44 PM PDT 24
Finished Jul 20 05:58:19 PM PDT 24
Peak memory 201796 kb
Host smart-13cc6710-833e-452a-bb36-fd4f11ee254e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=269428209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.269428209
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.794743435
Short name T91
Test name
Test status
Simulation time 531697231515 ps
CPU time 607.54 seconds
Started Jul 20 05:56:42 PM PDT 24
Finished Jul 20 06:06:51 PM PDT 24
Peak memory 201728 kb
Host smart-d467b81b-c031-4b2a-aabc-b2ccf5451bea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794743435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.794743435
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1971811004
Short name T665
Test name
Test status
Simulation time 406861263304 ps
CPU time 926.55 seconds
Started Jul 20 05:56:47 PM PDT 24
Finished Jul 20 06:12:15 PM PDT 24
Peak memory 201744 kb
Host smart-56ab1f9a-1f23-47f0-8781-e6e63fe5ccb8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971811004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1971811004
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.63539958
Short name T482
Test name
Test status
Simulation time 115596450443 ps
CPU time 348.12 seconds
Started Jul 20 05:56:46 PM PDT 24
Finished Jul 20 06:02:36 PM PDT 24
Peak memory 201888 kb
Host smart-ecc52127-c875-4dad-8c28-2bd8c9dee5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63539958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.63539958
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2530356835
Short name T29
Test name
Test status
Simulation time 27158434858 ps
CPU time 62.99 seconds
Started Jul 20 05:56:47 PM PDT 24
Finished Jul 20 05:57:52 PM PDT 24
Peak memory 201608 kb
Host smart-6640fa8d-f6ee-41e9-8840-48a68e55698d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530356835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2530356835
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2717731603
Short name T708
Test name
Test status
Simulation time 3944333924 ps
CPU time 10 seconds
Started Jul 20 05:56:44 PM PDT 24
Finished Jul 20 05:56:55 PM PDT 24
Peak memory 201600 kb
Host smart-20a62ca5-3df6-407d-b511-cff2c6a00112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717731603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2717731603
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.1076232880
Short name T779
Test name
Test status
Simulation time 5766711604 ps
CPU time 2.33 seconds
Started Jul 20 05:56:42 PM PDT 24
Finished Jul 20 05:56:45 PM PDT 24
Peak memory 201596 kb
Host smart-105050d7-6553-49f8-8b64-b2f4eee17e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076232880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1076232880
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1528705570
Short name T228
Test name
Test status
Simulation time 206293691129 ps
CPU time 482.75 seconds
Started Jul 20 05:56:51 PM PDT 24
Finished Jul 20 06:04:55 PM PDT 24
Peak memory 201732 kb
Host smart-fc4f17ba-f6d1-4b66-8650-c0f4b5758946
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528705570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1528705570
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.4021784899
Short name T314
Test name
Test status
Simulation time 164141425459 ps
CPU time 89.05 seconds
Started Jul 20 05:56:46 PM PDT 24
Finished Jul 20 05:58:16 PM PDT 24
Peak memory 201916 kb
Host smart-f897650f-fb09-4183-833d-953640122e18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021784899 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.4021784899
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3980119334
Short name T385
Test name
Test status
Simulation time 408301366 ps
CPU time 1.55 seconds
Started Jul 20 05:56:50 PM PDT 24
Finished Jul 20 05:56:53 PM PDT 24
Peak memory 201540 kb
Host smart-f613e71e-0880-40a2-864b-faa0bd1b584f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980119334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3980119334
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2875903816
Short name T333
Test name
Test status
Simulation time 493740195358 ps
CPU time 239.94 seconds
Started Jul 20 05:56:49 PM PDT 24
Finished Jul 20 06:00:50 PM PDT 24
Peak memory 201720 kb
Host smart-66a6914d-b4e1-42a9-96c9-6c873af306b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875903816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2875903816
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3943210015
Short name T145
Test name
Test status
Simulation time 503383318024 ps
CPU time 134.68 seconds
Started Jul 20 05:56:48 PM PDT 24
Finished Jul 20 05:59:05 PM PDT 24
Peak memory 201740 kb
Host smart-837cf63e-9087-4944-a6a7-3276ae728fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943210015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3943210015
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1308079025
Short name T86
Test name
Test status
Simulation time 489140771478 ps
CPU time 1096.28 seconds
Started Jul 20 05:56:45 PM PDT 24
Finished Jul 20 06:15:02 PM PDT 24
Peak memory 201624 kb
Host smart-5b5077f5-c8e7-49dc-8267-6fdc08494ea9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308079025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1308079025
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.700865572
Short name T770
Test name
Test status
Simulation time 492292662834 ps
CPU time 943.53 seconds
Started Jul 20 05:56:50 PM PDT 24
Finished Jul 20 06:12:34 PM PDT 24
Peak memory 201780 kb
Host smart-b07f2d47-3347-43d6-9961-3d139b490130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700865572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.700865572
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.4249408257
Short name T163
Test name
Test status
Simulation time 162945800832 ps
CPU time 102.24 seconds
Started Jul 20 05:56:50 PM PDT 24
Finished Jul 20 05:58:33 PM PDT 24
Peak memory 201688 kb
Host smart-9d1de1f5-594b-4c4d-9940-27f2574b589b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249408257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.4249408257
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3392746349
Short name T8
Test name
Test status
Simulation time 372481366292 ps
CPU time 454.58 seconds
Started Jul 20 05:56:48 PM PDT 24
Finished Jul 20 06:04:25 PM PDT 24
Peak memory 201748 kb
Host smart-a002a587-0c7c-4e05-8273-a83cde990bd2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392746349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3392746349
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1587301450
Short name T591
Test name
Test status
Simulation time 610920880100 ps
CPU time 1523.61 seconds
Started Jul 20 05:56:46 PM PDT 24
Finished Jul 20 06:22:11 PM PDT 24
Peak memory 201732 kb
Host smart-c2228d5e-92e9-40ce-b869-1a107734d861
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587301450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1587301450
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3550252674
Short name T645
Test name
Test status
Simulation time 124234038332 ps
CPU time 691.84 seconds
Started Jul 20 05:56:49 PM PDT 24
Finished Jul 20 06:08:23 PM PDT 24
Peak memory 202156 kb
Host smart-037da450-86a3-423d-9fe6-96b1ce3b8049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550252674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3550252674
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.461904667
Short name T347
Test name
Test status
Simulation time 39626614395 ps
CPU time 24.79 seconds
Started Jul 20 05:56:49 PM PDT 24
Finished Jul 20 05:57:16 PM PDT 24
Peak memory 201592 kb
Host smart-bb76b419-1a41-4eac-a12d-ee69e727a28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461904667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.461904667
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.306784004
Short name T539
Test name
Test status
Simulation time 3776925019 ps
CPU time 5.29 seconds
Started Jul 20 05:56:47 PM PDT 24
Finished Jul 20 05:56:54 PM PDT 24
Peak memory 201636 kb
Host smart-188887d6-9d96-4ac2-be72-26099f637fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306784004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.306784004
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3243529758
Short name T402
Test name
Test status
Simulation time 5910071727 ps
CPU time 8.58 seconds
Started Jul 20 05:56:48 PM PDT 24
Finished Jul 20 05:56:59 PM PDT 24
Peak memory 201624 kb
Host smart-659d1e12-6e7d-4a83-b006-33e45ae6ebc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243529758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3243529758
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.108813050
Short name T783
Test name
Test status
Simulation time 165150273048 ps
CPU time 372.83 seconds
Started Jul 20 05:56:45 PM PDT 24
Finished Jul 20 06:02:59 PM PDT 24
Peak memory 201784 kb
Host smart-98e30283-0ac0-47a3-87e3-92f2881dfeb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108813050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
108813050
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.8395537
Short name T511
Test name
Test status
Simulation time 385365893 ps
CPU time 0.87 seconds
Started Jul 20 05:56:57 PM PDT 24
Finished Jul 20 05:56:58 PM PDT 24
Peak memory 201520 kb
Host smart-71d93e7c-7acf-45b2-b1f7-9e75aa513036
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8395537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.8395537
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2764357181
Short name T212
Test name
Test status
Simulation time 404086060789 ps
CPU time 213.54 seconds
Started Jul 20 05:56:50 PM PDT 24
Finished Jul 20 06:00:24 PM PDT 24
Peak memory 201736 kb
Host smart-5f131c46-a983-422d-b789-9616843dc8f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764357181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2764357181
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.633055847
Short name T308
Test name
Test status
Simulation time 332016661134 ps
CPU time 97.96 seconds
Started Jul 20 05:56:47 PM PDT 24
Finished Jul 20 05:58:27 PM PDT 24
Peak memory 201740 kb
Host smart-64744fcf-1bbd-4538-8ae3-346c6fcb01c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633055847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.633055847
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3594737567
Short name T729
Test name
Test status
Simulation time 167846868658 ps
CPU time 108.65 seconds
Started Jul 20 05:56:48 PM PDT 24
Finished Jul 20 05:58:39 PM PDT 24
Peak memory 201664 kb
Host smart-49a46548-da2c-474c-b600-7e648cbfce03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594737567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3594737567
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1956697007
Short name T438
Test name
Test status
Simulation time 166104830066 ps
CPU time 101.55 seconds
Started Jul 20 05:56:46 PM PDT 24
Finished Jul 20 05:58:30 PM PDT 24
Peak memory 201656 kb
Host smart-61eb0073-a1e3-4c7f-af1b-68de5686d53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956697007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1956697007
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1735258307
Short name T360
Test name
Test status
Simulation time 490444081124 ps
CPU time 1129.27 seconds
Started Jul 20 05:56:45 PM PDT 24
Finished Jul 20 06:15:35 PM PDT 24
Peak memory 201744 kb
Host smart-9524352c-0c8f-4049-851b-1571e03fd480
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735258307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1735258307
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.4149288588
Short name T775
Test name
Test status
Simulation time 606663032806 ps
CPU time 1356.72 seconds
Started Jul 20 05:56:48 PM PDT 24
Finished Jul 20 06:19:27 PM PDT 24
Peak memory 201724 kb
Host smart-d20870ac-b332-4cdb-9d5a-ec55829a1321
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149288588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.4149288588
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.740425809
Short name T741
Test name
Test status
Simulation time 93157589130 ps
CPU time 381.55 seconds
Started Jul 20 05:56:58 PM PDT 24
Finished Jul 20 06:03:21 PM PDT 24
Peak memory 202108 kb
Host smart-37defd30-b7ac-42b6-8c7d-65a98e9298dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740425809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.740425809
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.170540571
Short name T2
Test name
Test status
Simulation time 25623958298 ps
CPU time 56.32 seconds
Started Jul 20 05:57:07 PM PDT 24
Finished Jul 20 05:58:04 PM PDT 24
Peak memory 201600 kb
Host smart-fdcb1080-69a4-4d67-a678-090eb1cb0362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170540571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.170540571
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2067865685
Short name T365
Test name
Test status
Simulation time 4838977958 ps
CPU time 3.58 seconds
Started Jul 20 05:57:03 PM PDT 24
Finished Jul 20 05:57:08 PM PDT 24
Peak memory 201564 kb
Host smart-cf4fecd9-2230-40a2-85c5-f886ea0b0fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067865685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2067865685
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3292260042
Short name T624
Test name
Test status
Simulation time 5793419475 ps
CPU time 13.06 seconds
Started Jul 20 05:56:47 PM PDT 24
Finished Jul 20 05:57:03 PM PDT 24
Peak memory 201596 kb
Host smart-9b64312c-0de7-4128-96db-4aa17a765b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292260042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3292260042
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1257557275
Short name T317
Test name
Test status
Simulation time 546644062109 ps
CPU time 659.5 seconds
Started Jul 20 05:57:06 PM PDT 24
Finished Jul 20 06:08:06 PM PDT 24
Peak memory 201736 kb
Host smart-6f61b720-d252-42e2-a0fe-de57e18ac4f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257557275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1257557275
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1417250573
Short name T20
Test name
Test status
Simulation time 23841947874 ps
CPU time 102.42 seconds
Started Jul 20 05:56:56 PM PDT 24
Finished Jul 20 05:58:39 PM PDT 24
Peak memory 210436 kb
Host smart-c0851c1e-01f6-4b0a-be52-ba966518f62f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417250573 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1417250573
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.783021744
Short name T545
Test name
Test status
Simulation time 432698768 ps
CPU time 1.13 seconds
Started Jul 20 05:56:57 PM PDT 24
Finished Jul 20 05:56:58 PM PDT 24
Peak memory 201676 kb
Host smart-84c1a72b-7936-416c-8fcd-691abf848a74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783021744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.783021744
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.460612262
Short name T710
Test name
Test status
Simulation time 191098482077 ps
CPU time 130.88 seconds
Started Jul 20 05:56:56 PM PDT 24
Finished Jul 20 05:59:08 PM PDT 24
Peak memory 201812 kb
Host smart-461418c3-6d90-4cdc-a3a1-c425ba616094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460612262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.460612262
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2637100783
Short name T642
Test name
Test status
Simulation time 167129424490 ps
CPU time 202.97 seconds
Started Jul 20 05:57:03 PM PDT 24
Finished Jul 20 06:00:27 PM PDT 24
Peak memory 201744 kb
Host smart-ebf47bea-e1e8-45f8-b20d-e6c7a2cefd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637100783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2637100783
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2880188794
Short name T486
Test name
Test status
Simulation time 330412428009 ps
CPU time 130.61 seconds
Started Jul 20 05:56:59 PM PDT 24
Finished Jul 20 05:59:11 PM PDT 24
Peak memory 201720 kb
Host smart-22a8558e-16b3-421b-a185-06cc92cbdc56
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880188794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2880188794
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3022062280
Short name T748
Test name
Test status
Simulation time 159793945804 ps
CPU time 27.46 seconds
Started Jul 20 05:56:59 PM PDT 24
Finished Jul 20 05:57:28 PM PDT 24
Peak memory 201780 kb
Host smart-8b5320fe-e5c5-4174-a7a8-3fd50c9078db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022062280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3022062280
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.767584168
Short name T217
Test name
Test status
Simulation time 385037437375 ps
CPU time 902.72 seconds
Started Jul 20 05:57:03 PM PDT 24
Finished Jul 20 06:12:07 PM PDT 24
Peak memory 201748 kb
Host smart-68e1f342-3ead-4eb7-a6df-e80ec6033558
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767584168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.767584168
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3230620885
Short name T643
Test name
Test status
Simulation time 596526012017 ps
CPU time 1454.15 seconds
Started Jul 20 05:56:59 PM PDT 24
Finished Jul 20 06:21:15 PM PDT 24
Peak memory 201732 kb
Host smart-5d13056c-8803-4679-9804-f5d42d2c4e91
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230620885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3230620885
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3818772325
Short name T507
Test name
Test status
Simulation time 102621989084 ps
CPU time 546.24 seconds
Started Jul 20 05:56:57 PM PDT 24
Finished Jul 20 06:06:05 PM PDT 24
Peak memory 202104 kb
Host smart-fb6cd955-3eed-4608-9bcd-bc3c6f1c866a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818772325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3818772325
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3627702072
Short name T363
Test name
Test status
Simulation time 29239505733 ps
CPU time 61.79 seconds
Started Jul 20 05:57:02 PM PDT 24
Finished Jul 20 05:58:04 PM PDT 24
Peak memory 201600 kb
Host smart-359c06b9-78fb-4cbe-a4c4-5cd9f0bdbcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627702072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3627702072
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.667166113
Short name T355
Test name
Test status
Simulation time 4324773795 ps
CPU time 3.25 seconds
Started Jul 20 05:56:58 PM PDT 24
Finished Jul 20 05:57:03 PM PDT 24
Peak memory 201552 kb
Host smart-fb6b0da1-6bed-424a-bacd-005ae5172f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667166113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.667166113
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2669466832
Short name T6
Test name
Test status
Simulation time 5938487224 ps
CPU time 11.77 seconds
Started Jul 20 05:56:58 PM PDT 24
Finished Jul 20 05:57:12 PM PDT 24
Peak memory 201612 kb
Host smart-d24f5dc5-109d-4907-b855-06f13a3dc840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669466832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2669466832
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2065255550
Short name T310
Test name
Test status
Simulation time 491930705350 ps
CPU time 353.18 seconds
Started Jul 20 05:57:02 PM PDT 24
Finished Jul 20 06:02:57 PM PDT 24
Peak memory 201736 kb
Host smart-1676894e-496b-44e8-a246-cecf06c3ff36
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065255550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2065255550
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1258919056
Short name T149
Test name
Test status
Simulation time 336875735943 ps
CPU time 75.74 seconds
Started Jul 20 05:56:58 PM PDT 24
Finished Jul 20 05:58:15 PM PDT 24
Peak memory 201744 kb
Host smart-759e162b-1aaf-414d-97fb-382c77a92475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258919056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1258919056
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.583377999
Short name T656
Test name
Test status
Simulation time 163701573183 ps
CPU time 64.37 seconds
Started Jul 20 05:56:58 PM PDT 24
Finished Jul 20 05:58:04 PM PDT 24
Peak memory 201740 kb
Host smart-611b050d-836d-4762-b4c2-42a6f1ffe05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583377999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.583377999
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.109193468
Short name T587
Test name
Test status
Simulation time 495293011688 ps
CPU time 1095.36 seconds
Started Jul 20 05:57:03 PM PDT 24
Finished Jul 20 06:15:20 PM PDT 24
Peak memory 201696 kb
Host smart-26b67f6e-16a3-4f13-9750-f54010b763d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=109193468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.109193468
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1303739071
Short name T147
Test name
Test status
Simulation time 336643932585 ps
CPU time 806.71 seconds
Started Jul 20 05:56:59 PM PDT 24
Finished Jul 20 06:10:27 PM PDT 24
Peak memory 201732 kb
Host smart-9b2a145f-fb61-4119-9732-c969a9286c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303739071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1303739071
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2986518208
Short name T686
Test name
Test status
Simulation time 500305510796 ps
CPU time 293.92 seconds
Started Jul 20 05:56:57 PM PDT 24
Finished Jul 20 06:01:53 PM PDT 24
Peak memory 201716 kb
Host smart-567f1830-7c7a-4601-bb6c-142323768f31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986518208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2986518208
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.581946006
Short name T478
Test name
Test status
Simulation time 606285663024 ps
CPU time 215.91 seconds
Started Jul 20 05:57:02 PM PDT 24
Finished Jul 20 06:00:39 PM PDT 24
Peak memory 201688 kb
Host smart-802bf16c-bed7-4cb4-8404-110410e94044
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581946006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
adc_ctrl_filters_wakeup_fixed.581946006
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1763521890
Short name T199
Test name
Test status
Simulation time 135463554473 ps
CPU time 681.36 seconds
Started Jul 20 05:57:04 PM PDT 24
Finished Jul 20 06:08:26 PM PDT 24
Peak memory 202152 kb
Host smart-52b69ba9-327b-48a5-a134-4bc41a794cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763521890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1763521890
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2774403401
Short name T531
Test name
Test status
Simulation time 27505257587 ps
CPU time 58.33 seconds
Started Jul 20 05:56:55 PM PDT 24
Finished Jul 20 05:57:53 PM PDT 24
Peak memory 201732 kb
Host smart-e0afb584-5095-4ed8-8eb2-c71fd58efc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774403401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2774403401
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1507274170
Short name T405
Test name
Test status
Simulation time 5240545944 ps
CPU time 3.87 seconds
Started Jul 20 05:56:59 PM PDT 24
Finished Jul 20 05:57:04 PM PDT 24
Peak memory 201604 kb
Host smart-f7e1f5ac-7f3f-49a9-ac81-7117973ff966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507274170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1507274170
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2586298743
Short name T674
Test name
Test status
Simulation time 5855441268 ps
CPU time 7.85 seconds
Started Jul 20 05:57:04 PM PDT 24
Finished Jul 20 05:57:13 PM PDT 24
Peak memory 201604 kb
Host smart-e609954c-9180-473f-801d-592554ac6c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586298743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2586298743
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.499294809
Short name T566
Test name
Test status
Simulation time 73229066989 ps
CPU time 29.7 seconds
Started Jul 20 05:57:01 PM PDT 24
Finished Jul 20 05:57:32 PM PDT 24
Peak memory 210072 kb
Host smart-f5267c95-9451-42c2-b0ab-93dc1b9792fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499294809 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.499294809
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1376582935
Short name T471
Test name
Test status
Simulation time 453310931 ps
CPU time 0.85 seconds
Started Jul 20 05:56:58 PM PDT 24
Finished Jul 20 05:57:00 PM PDT 24
Peak memory 201560 kb
Host smart-b7433d45-c426-489c-a93f-bfdbbe6a7262
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376582935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1376582935
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1014534100
Short name T133
Test name
Test status
Simulation time 162696663614 ps
CPU time 394.41 seconds
Started Jul 20 05:57:03 PM PDT 24
Finished Jul 20 06:03:39 PM PDT 24
Peak memory 201776 kb
Host smart-f2ac8316-c8cd-4278-9f68-ccc24daaad4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014534100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1014534100
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3295017455
Short name T626
Test name
Test status
Simulation time 325215412048 ps
CPU time 47.15 seconds
Started Jul 20 05:57:07 PM PDT 24
Finished Jul 20 05:57:55 PM PDT 24
Peak memory 201720 kb
Host smart-6385807c-379f-4114-b8d2-cb9e11b8ef02
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295017455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3295017455
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3587630061
Short name T639
Test name
Test status
Simulation time 166313044851 ps
CPU time 126.91 seconds
Started Jul 20 05:57:05 PM PDT 24
Finished Jul 20 05:59:13 PM PDT 24
Peak memory 201752 kb
Host smart-f977a57f-f430-4bda-a19e-8cf61421bebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587630061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3587630061
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3135007962
Short name T420
Test name
Test status
Simulation time 325683570769 ps
CPU time 354.62 seconds
Started Jul 20 05:57:02 PM PDT 24
Finished Jul 20 06:02:59 PM PDT 24
Peak memory 201716 kb
Host smart-140bf939-109d-44cf-814c-f71e2a85d111
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135007962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3135007962
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.1221819604
Short name T299
Test name
Test status
Simulation time 322783886489 ps
CPU time 745.22 seconds
Started Jul 20 05:57:05 PM PDT 24
Finished Jul 20 06:09:31 PM PDT 24
Peak memory 201812 kb
Host smart-0705c8b1-6ebb-4f4b-b712-0e6ab73ff5f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221819604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.1221819604
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3757486849
Short name T735
Test name
Test status
Simulation time 590469122695 ps
CPU time 1357.67 seconds
Started Jul 20 05:56:57 PM PDT 24
Finished Jul 20 06:19:35 PM PDT 24
Peak memory 201732 kb
Host smart-a3deab3b-da54-442c-b604-5f872cc46029
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757486849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3757486849
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3768483243
Short name T725
Test name
Test status
Simulation time 110731235950 ps
CPU time 368.78 seconds
Started Jul 20 05:57:03 PM PDT 24
Finished Jul 20 06:03:13 PM PDT 24
Peak memory 202096 kb
Host smart-c5e51cd7-5a63-4c39-af4f-6ef0304b2a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768483243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3768483243
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3380921650
Short name T425
Test name
Test status
Simulation time 24287556769 ps
CPU time 56.73 seconds
Started Jul 20 05:57:05 PM PDT 24
Finished Jul 20 05:58:02 PM PDT 24
Peak memory 201608 kb
Host smart-13219a93-8ff3-4203-9589-5deeaf41b8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380921650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3380921650
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.2331916686
Short name T352
Test name
Test status
Simulation time 5161464295 ps
CPU time 7.27 seconds
Started Jul 20 05:56:59 PM PDT 24
Finished Jul 20 05:57:08 PM PDT 24
Peak memory 201512 kb
Host smart-57077d76-5c39-4261-ba92-dcbc4bd9739f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331916686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2331916686
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3147208954
Short name T403
Test name
Test status
Simulation time 5771748702 ps
CPU time 2.63 seconds
Started Jul 20 05:56:55 PM PDT 24
Finished Jul 20 05:56:58 PM PDT 24
Peak memory 201500 kb
Host smart-7b96e6bb-9d3d-455b-bd3c-5de5d2d3dd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147208954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3147208954
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1464635834
Short name T174
Test name
Test status
Simulation time 224714354839 ps
CPU time 261.78 seconds
Started Jul 20 05:57:01 PM PDT 24
Finished Jul 20 06:01:23 PM PDT 24
Peak memory 201792 kb
Host smart-8510156d-4589-4ce8-b850-a8876b166697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464635834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1464635834
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3952720796
Short name T337
Test name
Test status
Simulation time 82810249065 ps
CPU time 226.82 seconds
Started Jul 20 05:56:58 PM PDT 24
Finished Jul 20 06:00:47 PM PDT 24
Peak memory 210496 kb
Host smart-1a85a867-b632-4c81-bc63-c5c081658959
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952720796 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3952720796
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3921947530
Short name T392
Test name
Test status
Simulation time 393624460 ps
CPU time 1.46 seconds
Started Jul 20 05:57:06 PM PDT 24
Finished Jul 20 05:57:09 PM PDT 24
Peak memory 201536 kb
Host smart-720766ba-3aee-4656-89be-b315f381837e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921947530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3921947530
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3288921751
Short name T207
Test name
Test status
Simulation time 371108449022 ps
CPU time 199.47 seconds
Started Jul 20 05:57:01 PM PDT 24
Finished Jul 20 06:00:21 PM PDT 24
Peak memory 201652 kb
Host smart-d0a60c81-88d1-4833-95d9-12b4714c51c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288921751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3288921751
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.737914985
Short name T90
Test name
Test status
Simulation time 162080542761 ps
CPU time 371.93 seconds
Started Jul 20 05:57:02 PM PDT 24
Finished Jul 20 06:03:16 PM PDT 24
Peak memory 201828 kb
Host smart-85fde02f-2a1f-40e9-b444-1330842d7717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737914985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.737914985
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.4024839050
Short name T394
Test name
Test status
Simulation time 339669664335 ps
CPU time 716.63 seconds
Started Jul 20 05:56:58 PM PDT 24
Finished Jul 20 06:08:56 PM PDT 24
Peak memory 201720 kb
Host smart-7360a4a2-368d-449f-8825-48710d9ff4d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024839050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.4024839050
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2040312567
Short name T577
Test name
Test status
Simulation time 328538723011 ps
CPU time 788.96 seconds
Started Jul 20 05:56:53 PM PDT 24
Finished Jul 20 06:10:03 PM PDT 24
Peak memory 201636 kb
Host smart-b6085092-6091-4855-8edf-46603b90c05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040312567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2040312567
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2638727164
Short name T765
Test name
Test status
Simulation time 158324904218 ps
CPU time 87.69 seconds
Started Jul 20 05:56:58 PM PDT 24
Finished Jul 20 05:58:27 PM PDT 24
Peak memory 201696 kb
Host smart-6feb592e-1318-4d16-8f0b-e9231de2ead3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638727164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2638727164
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1156337835
Short name T524
Test name
Test status
Simulation time 196977018408 ps
CPU time 450.85 seconds
Started Jul 20 05:57:00 PM PDT 24
Finished Jul 20 06:04:32 PM PDT 24
Peak memory 201756 kb
Host smart-159d0dea-fda5-4100-be63-991a8af2ad7c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156337835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1156337835
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.994151906
Short name T648
Test name
Test status
Simulation time 592770120720 ps
CPU time 493.06 seconds
Started Jul 20 05:56:56 PM PDT 24
Finished Jul 20 06:05:09 PM PDT 24
Peak memory 201720 kb
Host smart-437eeb88-9d2d-4822-bd1f-9837c9c681da
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994151906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.994151906
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.1936019018
Short name T692
Test name
Test status
Simulation time 103557294331 ps
CPU time 548.53 seconds
Started Jul 20 05:57:04 PM PDT 24
Finished Jul 20 06:06:14 PM PDT 24
Peak memory 202064 kb
Host smart-705d0575-c9dc-4322-8269-162d777b3edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936019018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.1936019018
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.851084769
Short name T421
Test name
Test status
Simulation time 28826125091 ps
CPU time 16.91 seconds
Started Jul 20 05:57:16 PM PDT 24
Finished Jul 20 05:57:33 PM PDT 24
Peak memory 201584 kb
Host smart-fcaa915b-2caa-45e8-9654-11745de7aa86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851084769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.851084769
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2897104073
Short name T359
Test name
Test status
Simulation time 4391264655 ps
CPU time 9.57 seconds
Started Jul 20 05:57:09 PM PDT 24
Finished Jul 20 05:57:19 PM PDT 24
Peak memory 201552 kb
Host smart-59e87ebc-184d-4f4e-95e8-4a7d49e9c447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897104073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2897104073
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1917162681
Short name T395
Test name
Test status
Simulation time 5867226954 ps
CPU time 4.21 seconds
Started Jul 20 05:57:02 PM PDT 24
Finished Jul 20 05:57:08 PM PDT 24
Peak memory 201536 kb
Host smart-cfb878fe-5362-4dcb-8003-a88a70d59b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917162681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1917162681
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.1082633888
Short name T247
Test name
Test status
Simulation time 544801910022 ps
CPU time 1254.18 seconds
Started Jul 20 05:57:09 PM PDT 24
Finished Jul 20 06:18:04 PM PDT 24
Peak memory 201792 kb
Host smart-5040b44f-5da9-4904-a473-80f1979b0442
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082633888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.1082633888
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2845519101
Short name T25
Test name
Test status
Simulation time 142637549103 ps
CPU time 349.38 seconds
Started Jul 20 05:57:08 PM PDT 24
Finished Jul 20 06:02:58 PM PDT 24
Peak memory 217936 kb
Host smart-03a66e3e-b156-4488-ad99-2a983d3ba8c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845519101 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2845519101
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3160827535
Short name T85
Test name
Test status
Simulation time 508511430 ps
CPU time 0.92 seconds
Started Jul 20 05:57:02 PM PDT 24
Finished Jul 20 05:57:04 PM PDT 24
Peak memory 201544 kb
Host smart-9e59e9cc-aec9-4f30-a61d-0e6c17de34b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160827535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3160827535
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3515085754
Short name T740
Test name
Test status
Simulation time 159454880437 ps
CPU time 288.41 seconds
Started Jul 20 05:57:12 PM PDT 24
Finished Jul 20 06:02:01 PM PDT 24
Peak memory 201660 kb
Host smart-0399cc7f-2ce0-441f-95ed-0cb1cc8d6f88
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515085754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3515085754
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.4088947403
Short name T206
Test name
Test status
Simulation time 319878469588 ps
CPU time 698.6 seconds
Started Jul 20 05:57:13 PM PDT 24
Finished Jul 20 06:08:53 PM PDT 24
Peak memory 201752 kb
Host smart-38a740b2-82e7-4671-8185-64e73286436f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088947403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.4088947403
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.877696315
Short name T702
Test name
Test status
Simulation time 332309459841 ps
CPU time 610.49 seconds
Started Jul 20 05:57:05 PM PDT 24
Finished Jul 20 06:07:16 PM PDT 24
Peak memory 201792 kb
Host smart-e18c76a9-ad7b-4442-8f5b-55713a56c74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877696315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.877696315
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.4000583405
Short name T464
Test name
Test status
Simulation time 336373629691 ps
CPU time 364.77 seconds
Started Jul 20 05:57:05 PM PDT 24
Finished Jul 20 06:03:10 PM PDT 24
Peak memory 201724 kb
Host smart-1d8b31f4-807b-4918-8f0b-a76e345e3d59
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000583405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.4000583405
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2526692335
Short name T187
Test name
Test status
Simulation time 502956572724 ps
CPU time 297.9 seconds
Started Jul 20 05:57:09 PM PDT 24
Finished Jul 20 06:02:08 PM PDT 24
Peak memory 201744 kb
Host smart-35439e5a-9ba1-414b-ae8c-d4156826582d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526692335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2526692335
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2768615389
Short name T595
Test name
Test status
Simulation time 325651148397 ps
CPU time 52.44 seconds
Started Jul 20 05:57:04 PM PDT 24
Finished Jul 20 05:57:57 PM PDT 24
Peak memory 201752 kb
Host smart-f254cf6e-7a27-431e-9bf3-6abdbb09a3ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768615389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2768615389
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2958700486
Short name T794
Test name
Test status
Simulation time 386891982364 ps
CPU time 916.96 seconds
Started Jul 20 05:57:06 PM PDT 24
Finished Jul 20 06:12:24 PM PDT 24
Peak memory 201744 kb
Host smart-fb98078d-4e09-4f90-bca2-3097e5134253
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958700486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2958700486
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3557752719
Short name T731
Test name
Test status
Simulation time 190368153189 ps
CPU time 448.54 seconds
Started Jul 20 05:57:09 PM PDT 24
Finished Jul 20 06:04:39 PM PDT 24
Peak memory 201728 kb
Host smart-cec96ffc-f9a4-4cfd-be90-9d54955bc6e0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557752719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3557752719
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1803954847
Short name T510
Test name
Test status
Simulation time 114432942530 ps
CPU time 483.85 seconds
Started Jul 20 05:57:07 PM PDT 24
Finished Jul 20 06:05:12 PM PDT 24
Peak memory 202112 kb
Host smart-42435a42-4718-41c3-b127-f9badd5f1394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803954847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1803954847
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1993454889
Short name T356
Test name
Test status
Simulation time 23030067361 ps
CPU time 53.68 seconds
Started Jul 20 05:57:11 PM PDT 24
Finished Jul 20 05:58:05 PM PDT 24
Peak memory 201616 kb
Host smart-0384a2ce-2864-4c7b-b6a4-75d7b6a81ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993454889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1993454889
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.398757077
Short name T638
Test name
Test status
Simulation time 5762046532 ps
CPU time 4.54 seconds
Started Jul 20 05:57:07 PM PDT 24
Finished Jul 20 05:57:12 PM PDT 24
Peak memory 201604 kb
Host smart-3f250733-0d45-4b3d-b3d6-3694d4c46f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398757077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.398757077
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.4009842308
Short name T526
Test name
Test status
Simulation time 5560614999 ps
CPU time 4.22 seconds
Started Jul 20 05:57:10 PM PDT 24
Finished Jul 20 05:57:15 PM PDT 24
Peak memory 201584 kb
Host smart-4087ca7f-dd4f-402d-bd9b-00581753216c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009842308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.4009842308
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3212632109
Short name T19
Test name
Test status
Simulation time 109239082436 ps
CPU time 180.12 seconds
Started Jul 20 05:57:09 PM PDT 24
Finished Jul 20 06:00:10 PM PDT 24
Peak memory 210436 kb
Host smart-3fbe8829-d47b-4e78-a866-f605c69a472d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212632109 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3212632109
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.488854042
Short name T377
Test name
Test status
Simulation time 487477397 ps
CPU time 1.64 seconds
Started Jul 20 05:57:06 PM PDT 24
Finished Jul 20 05:57:08 PM PDT 24
Peak memory 201500 kb
Host smart-bfd4c31c-ba53-4092-b00b-01e843772739
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488854042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.488854042
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.728572440
Short name T409
Test name
Test status
Simulation time 201864300787 ps
CPU time 112.66 seconds
Started Jul 20 05:57:08 PM PDT 24
Finished Jul 20 05:59:01 PM PDT 24
Peak memory 201664 kb
Host smart-09e683e9-37b2-4ba9-bb80-6c8a34bceaa6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728572440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.728572440
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1311840506
Short name T251
Test name
Test status
Simulation time 196146657391 ps
CPU time 420.29 seconds
Started Jul 20 05:57:07 PM PDT 24
Finished Jul 20 06:04:08 PM PDT 24
Peak memory 201804 kb
Host smart-a2d8c801-9288-4216-a482-98b7154dfb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311840506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1311840506
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2684718117
Short name T157
Test name
Test status
Simulation time 325819901594 ps
CPU time 207.55 seconds
Started Jul 20 05:57:05 PM PDT 24
Finished Jul 20 06:00:33 PM PDT 24
Peak memory 201816 kb
Host smart-1949dd60-9443-4b10-bfa7-c8a3a6ee66b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684718117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2684718117
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1117920218
Short name T668
Test name
Test status
Simulation time 332366370344 ps
CPU time 708.83 seconds
Started Jul 20 05:57:16 PM PDT 24
Finished Jul 20 06:09:05 PM PDT 24
Peak memory 201704 kb
Host smart-7910a81a-0658-4d29-ab7e-2f563730f8e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117920218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1117920218
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.120848064
Short name T383
Test name
Test status
Simulation time 164219380097 ps
CPU time 352.82 seconds
Started Jul 20 05:57:08 PM PDT 24
Finished Jul 20 06:03:01 PM PDT 24
Peak memory 201756 kb
Host smart-0b520a9a-6389-4f09-ac3d-96ade52d7f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120848064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.120848064
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3601884806
Short name T675
Test name
Test status
Simulation time 163295040304 ps
CPU time 81.05 seconds
Started Jul 20 05:57:09 PM PDT 24
Finished Jul 20 05:58:30 PM PDT 24
Peak memory 201640 kb
Host smart-0b6d7daf-9716-42ff-b3b4-db83f9abed21
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601884806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3601884806
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3043506033
Short name T249
Test name
Test status
Simulation time 181548542033 ps
CPU time 116.47 seconds
Started Jul 20 05:57:18 PM PDT 24
Finished Jul 20 05:59:15 PM PDT 24
Peak memory 201784 kb
Host smart-d03d2a01-6e4e-433e-a89b-553f0a5b2b17
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043506033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3043506033
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.4025187589
Short name T717
Test name
Test status
Simulation time 401412187932 ps
CPU time 265.85 seconds
Started Jul 20 05:57:08 PM PDT 24
Finished Jul 20 06:01:34 PM PDT 24
Peak memory 201660 kb
Host smart-d09ce524-e8c4-4822-9e02-791fcae9160f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025187589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.4025187589
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2794591395
Short name T672
Test name
Test status
Simulation time 97561599400 ps
CPU time 356 seconds
Started Jul 20 05:57:02 PM PDT 24
Finished Jul 20 06:02:59 PM PDT 24
Peak memory 202080 kb
Host smart-09e1ecb3-289d-4ba2-b925-77cb6c291007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794591395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2794591395
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.4144242510
Short name T641
Test name
Test status
Simulation time 26116663344 ps
CPU time 7.09 seconds
Started Jul 20 05:57:17 PM PDT 24
Finished Jul 20 05:57:25 PM PDT 24
Peak memory 201596 kb
Host smart-63881396-8348-4c5b-998c-02086d09a161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144242510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.4144242510
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2716870653
Short name T706
Test name
Test status
Simulation time 4962988270 ps
CPU time 2.66 seconds
Started Jul 20 05:57:10 PM PDT 24
Finished Jul 20 05:57:13 PM PDT 24
Peak memory 201596 kb
Host smart-f7f4ff04-6e8e-4fa7-bb89-d1a0db6e07e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716870653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2716870653
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.4214528787
Short name T446
Test name
Test status
Simulation time 5695557249 ps
CPU time 14.83 seconds
Started Jul 20 05:57:04 PM PDT 24
Finished Jul 20 05:57:20 PM PDT 24
Peak memory 201612 kb
Host smart-bc91af97-907e-42cb-a3df-d5050796d4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214528787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.4214528787
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2099586116
Short name T575
Test name
Test status
Simulation time 394980243161 ps
CPU time 932.26 seconds
Started Jul 20 05:57:04 PM PDT 24
Finished Jul 20 06:12:37 PM PDT 24
Peak memory 201740 kb
Host smart-e8de6c62-f5ed-4e80-aa3c-e23233e52508
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099586116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2099586116
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1298318677
Short name T23
Test name
Test status
Simulation time 279055777908 ps
CPU time 273.57 seconds
Started Jul 20 05:57:09 PM PDT 24
Finished Jul 20 06:01:44 PM PDT 24
Peak memory 210420 kb
Host smart-7942c74e-dc50-4655-ba9c-e31a85b3e8be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298318677 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.1298318677
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2207941775
Short name T792
Test name
Test status
Simulation time 493804925 ps
CPU time 1.21 seconds
Started Jul 20 05:57:12 PM PDT 24
Finished Jul 20 05:57:14 PM PDT 24
Peak memory 201528 kb
Host smart-7064ed66-1f86-45a2-aa46-dadd91a04865
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207941775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2207941775
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.4288542097
Short name T778
Test name
Test status
Simulation time 540356110199 ps
CPU time 594.01 seconds
Started Jul 20 05:57:17 PM PDT 24
Finished Jul 20 06:07:12 PM PDT 24
Peak memory 201788 kb
Host smart-61cb9c63-1451-410c-8650-2600c9379e2c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288542097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.4288542097
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.610889976
Short name T96
Test name
Test status
Simulation time 163723916774 ps
CPU time 358.57 seconds
Started Jul 20 05:57:06 PM PDT 24
Finished Jul 20 06:03:06 PM PDT 24
Peak memory 201876 kb
Host smart-5d42cb5b-4483-4b39-8e38-980a8b67225d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610889976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.610889976
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1667947296
Short name T10
Test name
Test status
Simulation time 320519424263 ps
CPU time 574.58 seconds
Started Jul 20 05:57:06 PM PDT 24
Finished Jul 20 06:06:41 PM PDT 24
Peak memory 201664 kb
Host smart-46bdc1d2-d93e-475b-942b-b4977b219132
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667947296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1667947296
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.2371804434
Short name T501
Test name
Test status
Simulation time 161825462605 ps
CPU time 90.85 seconds
Started Jul 20 05:57:13 PM PDT 24
Finished Jul 20 05:58:44 PM PDT 24
Peak memory 201744 kb
Host smart-f6ad501c-977f-4b03-bf9b-d3037db0d9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371804434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2371804434
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3922037930
Short name T714
Test name
Test status
Simulation time 161780219079 ps
CPU time 180.49 seconds
Started Jul 20 05:57:18 PM PDT 24
Finished Jul 20 06:00:20 PM PDT 24
Peak memory 201712 kb
Host smart-46db95f3-c4b0-41e1-ab5f-1f4931b176cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922037930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3922037930
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3482869034
Short name T40
Test name
Test status
Simulation time 594005339956 ps
CPU time 1448.73 seconds
Started Jul 20 05:57:14 PM PDT 24
Finished Jul 20 06:21:23 PM PDT 24
Peak memory 201740 kb
Host smart-f608008b-fbee-44bf-8664-c110568198a7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482869034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3482869034
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3728600417
Short name T34
Test name
Test status
Simulation time 93937094627 ps
CPU time 401.92 seconds
Started Jul 20 05:57:14 PM PDT 24
Finished Jul 20 06:03:56 PM PDT 24
Peak memory 202092 kb
Host smart-3c1a64a6-ae76-4581-b9c4-579a02d42dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728600417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3728600417
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.4077675228
Short name T429
Test name
Test status
Simulation time 24218533391 ps
CPU time 23.62 seconds
Started Jul 20 05:57:14 PM PDT 24
Finished Jul 20 05:57:38 PM PDT 24
Peak memory 201560 kb
Host smart-58a16668-4bc1-42c2-9c54-28be9387b720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077675228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.4077675228
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3441470894
Short name T398
Test name
Test status
Simulation time 4184677395 ps
CPU time 5.47 seconds
Started Jul 20 05:57:11 PM PDT 24
Finished Jul 20 05:57:17 PM PDT 24
Peak memory 201600 kb
Host smart-c64bee3a-7fb4-43f5-85c5-3ec4db48a9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441470894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3441470894
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3772791440
Short name T399
Test name
Test status
Simulation time 5885627084 ps
CPU time 4.98 seconds
Started Jul 20 05:57:13 PM PDT 24
Finished Jul 20 05:57:19 PM PDT 24
Peak memory 201448 kb
Host smart-20945de4-9499-4d99-925d-dfe93161109e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772791440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3772791440
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.4244175520
Short name T574
Test name
Test status
Simulation time 588371548964 ps
CPU time 481.39 seconds
Started Jul 20 05:57:09 PM PDT 24
Finished Jul 20 06:05:11 PM PDT 24
Peak memory 202096 kb
Host smart-251e7798-91ad-44fb-9ea9-c667a897ad00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244175520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.4244175520
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2558975562
Short name T761
Test name
Test status
Simulation time 70072275066 ps
CPU time 98.58 seconds
Started Jul 20 05:57:06 PM PDT 24
Finished Jul 20 05:58:45 PM PDT 24
Peak memory 201864 kb
Host smart-69b287b7-0089-4da3-a43e-d84c9ee9dace
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558975562 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.2558975562
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.114892635
Short name T413
Test name
Test status
Simulation time 421442052 ps
CPU time 1.65 seconds
Started Jul 20 05:56:34 PM PDT 24
Finished Jul 20 05:56:39 PM PDT 24
Peak memory 201536 kb
Host smart-11b62186-9ec2-4879-bb03-8172d5b1c409
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114892635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.114892635
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3626346985
Short name T169
Test name
Test status
Simulation time 349622404822 ps
CPU time 115.37 seconds
Started Jul 20 05:56:35 PM PDT 24
Finished Jul 20 05:58:33 PM PDT 24
Peak memory 201668 kb
Host smart-1f807e32-1962-4968-964f-e191f8184ca0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626346985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3626346985
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.2278637145
Short name T155
Test name
Test status
Simulation time 554898706734 ps
CPU time 97.82 seconds
Started Jul 20 05:56:32 PM PDT 24
Finished Jul 20 05:58:13 PM PDT 24
Peak memory 201756 kb
Host smart-051e42f4-c909-4dec-89b4-ee05c6ab4397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278637145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.2278637145
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.509853989
Short name T160
Test name
Test status
Simulation time 159222090893 ps
CPU time 108.42 seconds
Started Jul 20 05:56:31 PM PDT 24
Finished Jul 20 05:58:22 PM PDT 24
Peak memory 201636 kb
Host smart-9ad9d6bb-626d-45c9-92b2-9c8fd4b33162
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=509853989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt
_fixed.509853989
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1369682391
Short name T788
Test name
Test status
Simulation time 320361125467 ps
CPU time 398.89 seconds
Started Jul 20 05:56:31 PM PDT 24
Finished Jul 20 06:03:13 PM PDT 24
Peak memory 201828 kb
Host smart-37324825-feb0-49f2-be28-c730577fcb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369682391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1369682391
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3976737787
Short name T759
Test name
Test status
Simulation time 327563798734 ps
CPU time 691.16 seconds
Started Jul 20 05:56:29 PM PDT 24
Finished Jul 20 06:08:02 PM PDT 24
Peak memory 201872 kb
Host smart-f3accbe8-3b08-4fe5-80dc-00a75518b28a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976737787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.3976737787
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1204318312
Short name T150
Test name
Test status
Simulation time 543443501943 ps
CPU time 275.21 seconds
Started Jul 20 05:56:29 PM PDT 24
Finished Jul 20 06:01:06 PM PDT 24
Peak memory 201748 kb
Host smart-ab554826-19d8-4b4c-8f4d-4c4aec4a2960
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204318312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1204318312
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3595964749
Short name T572
Test name
Test status
Simulation time 403434281646 ps
CPU time 844.42 seconds
Started Jul 20 05:56:34 PM PDT 24
Finished Jul 20 06:10:41 PM PDT 24
Peak memory 201740 kb
Host smart-22b56da4-6c63-4d1c-a6bf-63b3ae68ae2d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595964749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.3595964749
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3834815017
Short name T195
Test name
Test status
Simulation time 93860957913 ps
CPU time 340.78 seconds
Started Jul 20 05:56:38 PM PDT 24
Finished Jul 20 06:02:20 PM PDT 24
Peak memory 202112 kb
Host smart-6d7fe3c4-6469-4c0e-af42-a7f9ac0f7a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834815017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3834815017
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.802646670
Short name T406
Test name
Test status
Simulation time 26834587749 ps
CPU time 61.44 seconds
Started Jul 20 05:56:32 PM PDT 24
Finished Jul 20 05:57:37 PM PDT 24
Peak memory 201604 kb
Host smart-d3e0b813-5993-4643-9b66-f03c72f3bd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802646670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.802646670
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2978410673
Short name T379
Test name
Test status
Simulation time 4948395935 ps
CPU time 6.1 seconds
Started Jul 20 05:56:35 PM PDT 24
Finished Jul 20 05:56:44 PM PDT 24
Peak memory 201600 kb
Host smart-1e899f74-5b72-4fa3-93e0-980d2f44a2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978410673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2978410673
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3352529708
Short name T60
Test name
Test status
Simulation time 7878545929 ps
CPU time 5.6 seconds
Started Jul 20 05:56:30 PM PDT 24
Finished Jul 20 05:56:38 PM PDT 24
Peak memory 217388 kb
Host smart-7023afe0-f098-4b50-b6c9-ee91590613dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352529708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3352529708
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.218541860
Short name T567
Test name
Test status
Simulation time 5996141143 ps
CPU time 4.1 seconds
Started Jul 20 05:56:38 PM PDT 24
Finished Jul 20 05:56:44 PM PDT 24
Peak memory 201604 kb
Host smart-d9bf3fa1-6a85-4f78-bdfe-00271ac6070e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218541860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.218541860
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.4122227365
Short name T277
Test name
Test status
Simulation time 178627392359 ps
CPU time 434.89 seconds
Started Jul 20 05:56:34 PM PDT 24
Finished Jul 20 06:03:52 PM PDT 24
Peak memory 201840 kb
Host smart-5050e709-1dec-480b-acce-84d34b67c8e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122227365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
4122227365
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2968510001
Short name T191
Test name
Test status
Simulation time 230638488206 ps
CPU time 260.72 seconds
Started Jul 20 05:56:38 PM PDT 24
Finished Jul 20 06:01:01 PM PDT 24
Peak memory 210060 kb
Host smart-9bfe8d1a-e0fa-4bde-9ab1-03a6660637ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968510001 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2968510001
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.11127075
Short name T473
Test name
Test status
Simulation time 474625954 ps
CPU time 0.87 seconds
Started Jul 20 05:57:20 PM PDT 24
Finished Jul 20 05:57:21 PM PDT 24
Peak memory 201536 kb
Host smart-960e307d-8300-4474-8bfa-8a7998815cb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11127075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.11127075
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.4205395185
Short name T275
Test name
Test status
Simulation time 353141125451 ps
CPU time 421.27 seconds
Started Jul 20 05:57:11 PM PDT 24
Finished Jul 20 06:04:13 PM PDT 24
Peak memory 201696 kb
Host smart-2c83a5d1-ad06-447f-887d-95b7f42c472b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205395185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.4205395185
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.1596020970
Short name T224
Test name
Test status
Simulation time 161229559776 ps
CPU time 85.48 seconds
Started Jul 20 05:57:14 PM PDT 24
Finished Jul 20 05:58:40 PM PDT 24
Peak memory 201804 kb
Host smart-41156a4b-5804-4c63-8150-cbb5e7e3b4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596020970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.1596020970
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.162342051
Short name T504
Test name
Test status
Simulation time 496866893429 ps
CPU time 275.38 seconds
Started Jul 20 05:57:09 PM PDT 24
Finished Jul 20 06:01:45 PM PDT 24
Peak memory 201720 kb
Host smart-b0bea8a7-c11e-4ae3-8747-d3b4706af295
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=162342051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.162342051
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.157409531
Short name T267
Test name
Test status
Simulation time 322680808036 ps
CPU time 376.31 seconds
Started Jul 20 05:57:14 PM PDT 24
Finished Jul 20 06:03:31 PM PDT 24
Peak memory 201824 kb
Host smart-efe40062-4d6f-468d-a183-03bbdf28b447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157409531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.157409531
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.4047145303
Short name T488
Test name
Test status
Simulation time 499653605273 ps
CPU time 307.84 seconds
Started Jul 20 05:57:02 PM PDT 24
Finished Jul 20 06:02:11 PM PDT 24
Peak memory 201728 kb
Host smart-bb804ea6-1cb6-47c3-b325-6a91c34b0fc1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047145303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.4047145303
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.1424127490
Short name T167
Test name
Test status
Simulation time 419447727489 ps
CPU time 236.01 seconds
Started Jul 20 05:57:14 PM PDT 24
Finished Jul 20 06:01:11 PM PDT 24
Peak memory 201712 kb
Host smart-023f2132-d8c2-4a3f-b82d-13ce3b53e1a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424127490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.1424127490
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1406142044
Short name T700
Test name
Test status
Simulation time 38356480325 ps
CPU time 21.89 seconds
Started Jul 20 05:57:16 PM PDT 24
Finished Jul 20 05:57:39 PM PDT 24
Peak memory 201564 kb
Host smart-aed93d03-6870-48dd-a164-9ef666294f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406142044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1406142044
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.3886228976
Short name T43
Test name
Test status
Simulation time 4325545770 ps
CPU time 3.39 seconds
Started Jul 20 05:57:15 PM PDT 24
Finished Jul 20 05:57:19 PM PDT 24
Peak memory 201612 kb
Host smart-5a7056e4-760a-4ecc-b1b1-f147a04b442f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886228976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3886228976
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3273021676
Short name T344
Test name
Test status
Simulation time 5658446825 ps
CPU time 14.15 seconds
Started Jul 20 05:57:21 PM PDT 24
Finished Jul 20 05:57:35 PM PDT 24
Peak memory 201584 kb
Host smart-bffdd286-cb55-4b68-bd0f-88adadc56c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273021676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3273021676
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1413965578
Short name T705
Test name
Test status
Simulation time 243995917151 ps
CPU time 789.28 seconds
Started Jul 20 05:57:14 PM PDT 24
Finished Jul 20 06:10:24 PM PDT 24
Peak memory 210300 kb
Host smart-ece32690-bea7-4573-8e3a-36de360f79ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413965578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1413965578
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.270989299
Short name T633
Test name
Test status
Simulation time 211293162004 ps
CPU time 109.98 seconds
Started Jul 20 05:57:17 PM PDT 24
Finished Jul 20 05:59:08 PM PDT 24
Peak memory 210132 kb
Host smart-088e4b1d-90b6-4369-96ae-2dac548fba2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270989299 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.270989299
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3207979173
Short name T374
Test name
Test status
Simulation time 523127921 ps
CPU time 1.22 seconds
Started Jul 20 05:57:17 PM PDT 24
Finished Jul 20 05:57:19 PM PDT 24
Peak memory 201536 kb
Host smart-148139a2-28ef-4432-a6b3-2aafc10a367f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207979173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3207979173
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1224242119
Short name T138
Test name
Test status
Simulation time 477973396883 ps
CPU time 279.77 seconds
Started Jul 20 05:57:15 PM PDT 24
Finished Jul 20 06:01:56 PM PDT 24
Peak memory 201716 kb
Host smart-749a39f0-f3e9-4b2c-914c-e78f0ff13adc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224242119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1224242119
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1313576888
Short name T274
Test name
Test status
Simulation time 167643561073 ps
CPU time 397.7 seconds
Started Jul 20 05:57:17 PM PDT 24
Finished Jul 20 06:03:56 PM PDT 24
Peak memory 201748 kb
Host smart-19d6e3e6-d98e-4d61-a81e-cfed1b5dec2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313576888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1313576888
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1786950826
Short name T14
Test name
Test status
Simulation time 492437419654 ps
CPU time 259.23 seconds
Started Jul 20 05:57:16 PM PDT 24
Finished Jul 20 06:01:36 PM PDT 24
Peak memory 201652 kb
Host smart-0ff174e9-dc4d-4747-915a-6a658df23e2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786950826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1786950826
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.25271229
Short name T533
Test name
Test status
Simulation time 178833164186 ps
CPU time 23.98 seconds
Started Jul 20 05:57:16 PM PDT 24
Finished Jul 20 05:57:41 PM PDT 24
Peak memory 201748 kb
Host smart-ea597e77-9d7c-4269-a077-01977312ef77
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25271229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_w
akeup.25271229
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2162881443
Short name T678
Test name
Test status
Simulation time 403430817495 ps
CPU time 279.7 seconds
Started Jul 20 05:57:13 PM PDT 24
Finished Jul 20 06:01:53 PM PDT 24
Peak memory 201740 kb
Host smart-f74e82c7-a510-43a9-ac3e-645cc8690e71
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162881443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2162881443
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2259390714
Short name T553
Test name
Test status
Simulation time 23970487615 ps
CPU time 30.16 seconds
Started Jul 20 05:57:14 PM PDT 24
Finished Jul 20 05:57:45 PM PDT 24
Peak memory 201600 kb
Host smart-8615b9f0-eef5-49a7-8c4a-64a0c8103035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259390714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2259390714
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2734884588
Short name T465
Test name
Test status
Simulation time 5199465800 ps
CPU time 12.18 seconds
Started Jul 20 05:57:11 PM PDT 24
Finished Jul 20 05:57:24 PM PDT 24
Peak memory 201652 kb
Host smart-1211ac72-60bc-4364-ab2b-963365e02592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734884588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2734884588
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.185476667
Short name T354
Test name
Test status
Simulation time 6122356217 ps
CPU time 14.32 seconds
Started Jul 20 05:57:18 PM PDT 24
Finished Jul 20 05:57:33 PM PDT 24
Peak memory 201504 kb
Host smart-ecc5f82c-d178-49e8-a357-69ec7462ffae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185476667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.185476667
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2469601322
Short name T547
Test name
Test status
Simulation time 286952361333 ps
CPU time 148.21 seconds
Started Jul 20 05:57:19 PM PDT 24
Finished Jul 20 05:59:48 PM PDT 24
Peak memory 201804 kb
Host smart-bb4289f7-a6e1-4c9f-873f-d79dec866f84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469601322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2469601322
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.990905976
Short name T522
Test name
Test status
Simulation time 68061118441 ps
CPU time 143.24 seconds
Started Jul 20 05:57:17 PM PDT 24
Finished Jul 20 05:59:41 PM PDT 24
Peak memory 218704 kb
Host smart-b2ae4c4c-1cfa-4ccf-8531-367e66dc60b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990905976 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.990905976
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.2238544301
Short name T676
Test name
Test status
Simulation time 450372498 ps
CPU time 1.11 seconds
Started Jul 20 05:57:21 PM PDT 24
Finished Jul 20 05:57:23 PM PDT 24
Peak memory 201536 kb
Host smart-62334c07-a509-443b-a12f-1f8c7d71e2f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238544301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2238544301
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1897518514
Short name T295
Test name
Test status
Simulation time 354093587349 ps
CPU time 397.65 seconds
Started Jul 20 05:57:19 PM PDT 24
Finished Jul 20 06:03:57 PM PDT 24
Peak memory 201732 kb
Host smart-0eedd39f-0734-4e2d-96b9-c5544b82510a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897518514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1897518514
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3891650834
Short name T527
Test name
Test status
Simulation time 169961770973 ps
CPU time 391.28 seconds
Started Jul 20 05:57:21 PM PDT 24
Finished Jul 20 06:03:53 PM PDT 24
Peak memory 201752 kb
Host smart-443124a2-5b2c-417d-aad3-50c0778c5283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891650834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3891650834
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3671206208
Short name T28
Test name
Test status
Simulation time 168687856206 ps
CPU time 202.49 seconds
Started Jul 20 05:57:21 PM PDT 24
Finished Jul 20 06:00:44 PM PDT 24
Peak memory 201740 kb
Host smart-8e1af00b-3067-45b2-940f-1e203262b706
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671206208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.3671206208
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.395140987
Short name T266
Test name
Test status
Simulation time 326632809315 ps
CPU time 722.12 seconds
Started Jul 20 05:57:16 PM PDT 24
Finished Jul 20 06:09:19 PM PDT 24
Peak memory 201788 kb
Host smart-3e9c1c11-2820-406f-b60b-b3bf38ded299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395140987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.395140987
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2225044766
Short name T188
Test name
Test status
Simulation time 170061034146 ps
CPU time 102.57 seconds
Started Jul 20 05:57:17 PM PDT 24
Finished Jul 20 05:59:00 PM PDT 24
Peak memory 201732 kb
Host smart-73d03b52-b433-45f2-b44c-6f76415c9bc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225044766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2225044766
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3679713606
Short name T156
Test name
Test status
Simulation time 550903107879 ps
CPU time 328.36 seconds
Started Jul 20 05:57:14 PM PDT 24
Finished Jul 20 06:02:43 PM PDT 24
Peak memory 201808 kb
Host smart-4aea0b04-bcc9-4ceb-b65f-39a7dc5cf9b3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679713606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3679713606
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2654214657
Short name T600
Test name
Test status
Simulation time 597821409673 ps
CPU time 334.93 seconds
Started Jul 20 05:57:15 PM PDT 24
Finished Jul 20 06:02:51 PM PDT 24
Peak memory 201644 kb
Host smart-e1dafa25-ab25-43a2-927e-d1ebacdf3341
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654214657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2654214657
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.895298933
Short name T551
Test name
Test status
Simulation time 78978513634 ps
CPU time 286.8 seconds
Started Jul 20 05:57:27 PM PDT 24
Finished Jul 20 06:02:15 PM PDT 24
Peak memory 202096 kb
Host smart-cd7ab064-681b-4a21-b9f3-f73cb666b47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895298933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.895298933
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3555233577
Short name T393
Test name
Test status
Simulation time 34698110139 ps
CPU time 74.28 seconds
Started Jul 20 05:57:12 PM PDT 24
Finished Jul 20 05:58:27 PM PDT 24
Peak memory 201732 kb
Host smart-5a52cd1d-fe6b-432d-8268-11f612aac9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555233577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3555233577
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2944007221
Short name T691
Test name
Test status
Simulation time 3628287792 ps
CPU time 4.68 seconds
Started Jul 20 05:57:17 PM PDT 24
Finished Jul 20 05:57:22 PM PDT 24
Peak memory 201516 kb
Host smart-f4b2d2c6-3f79-4795-ae01-fe3f30609432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944007221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2944007221
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1261240482
Short name T528
Test name
Test status
Simulation time 5739511585 ps
CPU time 14.92 seconds
Started Jul 20 05:57:13 PM PDT 24
Finished Jul 20 05:57:29 PM PDT 24
Peak memory 201604 kb
Host smart-f4172109-8a57-43b1-9739-1141e2b6ad79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261240482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1261240482
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.495204865
Short name T253
Test name
Test status
Simulation time 506696984959 ps
CPU time 377.24 seconds
Started Jul 20 05:57:23 PM PDT 24
Finished Jul 20 06:03:41 PM PDT 24
Peak memory 201732 kb
Host smart-116d4d27-32f4-4149-89ec-1112689c4480
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495204865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.
495204865
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1811711265
Short name T246
Test name
Test status
Simulation time 831953691475 ps
CPU time 472.19 seconds
Started Jul 20 05:57:22 PM PDT 24
Finished Jul 20 06:05:15 PM PDT 24
Peak memory 210452 kb
Host smart-e9569152-808a-4b15-9dc8-7a6f1f0ee540
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811711265 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1811711265
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1900538936
Short name T436
Test name
Test status
Simulation time 498367383 ps
CPU time 0.88 seconds
Started Jul 20 05:57:24 PM PDT 24
Finished Jul 20 05:57:26 PM PDT 24
Peak memory 201540 kb
Host smart-e97e3078-9eb9-4cd0-9abd-2cc70d2dd7a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900538936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1900538936
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1565542252
Short name T140
Test name
Test status
Simulation time 175945587176 ps
CPU time 10.15 seconds
Started Jul 20 05:57:23 PM PDT 24
Finished Jul 20 05:57:33 PM PDT 24
Peak memory 201744 kb
Host smart-90ac22b5-738d-413b-b369-f3e98b7a20a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565542252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1565542252
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3797997063
Short name T516
Test name
Test status
Simulation time 160966299421 ps
CPU time 90.57 seconds
Started Jul 20 05:57:25 PM PDT 24
Finished Jul 20 05:58:56 PM PDT 24
Peak memory 201732 kb
Host smart-0040b280-273a-494f-b9db-634392333866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797997063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3797997063
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2208205094
Short name T703
Test name
Test status
Simulation time 166699395743 ps
CPU time 414.24 seconds
Started Jul 20 05:57:25 PM PDT 24
Finished Jul 20 06:04:19 PM PDT 24
Peak memory 201736 kb
Host smart-14607a1e-0f63-48ff-b1eb-c1c088990460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208205094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2208205094
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3534467842
Short name T435
Test name
Test status
Simulation time 330456787066 ps
CPU time 240.43 seconds
Started Jul 20 05:57:26 PM PDT 24
Finished Jul 20 06:01:27 PM PDT 24
Peak memory 201772 kb
Host smart-45448dfc-d9e6-49fa-90cf-5a6d691759e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534467842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.3534467842
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.601144501
Short name T637
Test name
Test status
Simulation time 486352199722 ps
CPU time 302.13 seconds
Started Jul 20 05:57:21 PM PDT 24
Finished Jul 20 06:02:24 PM PDT 24
Peak memory 201744 kb
Host smart-bb732f78-58e1-46a4-9886-36869ff51f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601144501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.601144501
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1366586758
Short name T588
Test name
Test status
Simulation time 323748725830 ps
CPU time 64.79 seconds
Started Jul 20 05:57:25 PM PDT 24
Finished Jul 20 05:58:30 PM PDT 24
Peak memory 201712 kb
Host smart-b6814cc5-fd03-4a13-9ddc-599d09921335
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366586758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1366586758
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1472015758
Short name T451
Test name
Test status
Simulation time 178731348850 ps
CPU time 189.98 seconds
Started Jul 20 05:57:22 PM PDT 24
Finished Jul 20 06:00:32 PM PDT 24
Peak memory 201820 kb
Host smart-aca175cf-d1bc-4c29-9758-4f94e04a57c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472015758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1472015758
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1573973015
Short name T593
Test name
Test status
Simulation time 191856026402 ps
CPU time 112.22 seconds
Started Jul 20 05:57:21 PM PDT 24
Finished Jul 20 05:59:14 PM PDT 24
Peak memory 201632 kb
Host smart-62551c63-0d53-4cfd-8b45-2262fa1a2604
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573973015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1573973015
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.1850773402
Short name T458
Test name
Test status
Simulation time 77731588771 ps
CPU time 339.52 seconds
Started Jul 20 05:57:19 PM PDT 24
Finished Jul 20 06:02:59 PM PDT 24
Peak memory 202108 kb
Host smart-ac6b44a2-3405-4b54-9cbe-9c8a8a6c192c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850773402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.1850773402
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1719840877
Short name T610
Test name
Test status
Simulation time 42705201538 ps
CPU time 27.29 seconds
Started Jul 20 05:57:24 PM PDT 24
Finished Jul 20 05:57:52 PM PDT 24
Peak memory 201584 kb
Host smart-49829ea9-796e-463d-ac1e-a8786482ab30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719840877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1719840877
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.629030586
Short name T9
Test name
Test status
Simulation time 4933146287 ps
CPU time 1.53 seconds
Started Jul 20 05:57:25 PM PDT 24
Finished Jul 20 05:57:27 PM PDT 24
Peak memory 201596 kb
Host smart-f24eaada-c622-43b1-af1e-541500fc7d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629030586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.629030586
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.932585390
Short name T658
Test name
Test status
Simulation time 6138309780 ps
CPU time 4.34 seconds
Started Jul 20 05:57:19 PM PDT 24
Finished Jul 20 05:57:24 PM PDT 24
Peak memory 201616 kb
Host smart-6e383f14-afae-4dc8-8fcd-07d8d1f5d501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932585390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.932585390
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.375291624
Short name T721
Test name
Test status
Simulation time 74897929014 ps
CPU time 161.36 seconds
Started Jul 20 05:57:25 PM PDT 24
Finished Jul 20 06:00:07 PM PDT 24
Peak memory 201780 kb
Host smart-d7a24495-01f1-41de-bc8a-93725cf34137
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375291624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
375291624
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2533464498
Short name T65
Test name
Test status
Simulation time 435910169 ps
CPU time 1.1 seconds
Started Jul 20 05:57:31 PM PDT 24
Finished Jul 20 05:57:32 PM PDT 24
Peak memory 201552 kb
Host smart-e160e3db-a136-4ec6-8092-894b557effb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533464498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2533464498
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3468197604
Short name T236
Test name
Test status
Simulation time 553499204751 ps
CPU time 600.85 seconds
Started Jul 20 05:57:27 PM PDT 24
Finished Jul 20 06:07:29 PM PDT 24
Peak memory 201684 kb
Host smart-9f001c93-0e53-453f-a379-7850454dd214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468197604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3468197604
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.1092641573
Short name T269
Test name
Test status
Simulation time 323550964411 ps
CPU time 791.88 seconds
Started Jul 20 05:57:25 PM PDT 24
Finished Jul 20 06:10:37 PM PDT 24
Peak memory 201736 kb
Host smart-576193d8-97dd-4055-ba4b-f1f373fc1d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092641573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1092641573
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.551973771
Short name T509
Test name
Test status
Simulation time 485403414720 ps
CPU time 531.13 seconds
Started Jul 20 05:57:28 PM PDT 24
Finished Jul 20 06:06:20 PM PDT 24
Peak memory 201596 kb
Host smart-351e9fdf-33b9-4054-be7c-bf60dbd6e1eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=551973771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.551973771
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2309289361
Short name T650
Test name
Test status
Simulation time 504452529555 ps
CPU time 584.32 seconds
Started Jul 20 05:57:22 PM PDT 24
Finished Jul 20 06:07:07 PM PDT 24
Peak memory 201812 kb
Host smart-09b08dcb-bd4a-4ef6-ba00-f52d497fac54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309289361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2309289361
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.3176925935
Short name T411
Test name
Test status
Simulation time 331900063389 ps
CPU time 762.3 seconds
Started Jul 20 05:57:23 PM PDT 24
Finished Jul 20 06:10:06 PM PDT 24
Peak memory 201688 kb
Host smart-fbf1036f-982e-4fe3-9ca0-eaf02ac153b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176925935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.3176925935
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.226186001
Short name T569
Test name
Test status
Simulation time 346381763968 ps
CPU time 771.15 seconds
Started Jul 20 05:57:22 PM PDT 24
Finished Jul 20 06:10:14 PM PDT 24
Peak memory 201756 kb
Host smart-6d53b89e-07b0-4b94-a573-c54bc4a4b144
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226186001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.226186001
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.4095032967
Short name T552
Test name
Test status
Simulation time 405628347009 ps
CPU time 270.54 seconds
Started Jul 20 05:57:21 PM PDT 24
Finished Jul 20 06:01:52 PM PDT 24
Peak memory 201700 kb
Host smart-9352a5ce-b00c-4407-a51b-b672e4e5e104
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095032967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.4095032967
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.644268973
Short name T611
Test name
Test status
Simulation time 113655548288 ps
CPU time 379.7 seconds
Started Jul 20 05:57:23 PM PDT 24
Finished Jul 20 06:03:43 PM PDT 24
Peak memory 202108 kb
Host smart-97c08bbc-105b-4b8b-8db4-1f94e48bf6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644268973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.644268973
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.605277909
Short name T362
Test name
Test status
Simulation time 25895314145 ps
CPU time 6.54 seconds
Started Jul 20 05:57:28 PM PDT 24
Finished Jul 20 05:57:35 PM PDT 24
Peak memory 201548 kb
Host smart-3b6da0d4-5947-46d3-a3a1-f571e2ec5570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605277909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.605277909
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2780567708
Short name T349
Test name
Test status
Simulation time 2865540496 ps
CPU time 2.32 seconds
Started Jul 20 05:57:23 PM PDT 24
Finished Jul 20 05:57:26 PM PDT 24
Peak memory 201596 kb
Host smart-75fa0aef-d216-4b67-a2eb-0eaf0c3bd354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780567708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2780567708
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3733102633
Short name T709
Test name
Test status
Simulation time 5490984962 ps
CPU time 3.47 seconds
Started Jul 20 05:57:28 PM PDT 24
Finished Jul 20 05:57:32 PM PDT 24
Peak memory 201484 kb
Host smart-02b556a8-5e87-4444-a473-bb6a4768cabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733102633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3733102633
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3679769623
Short name T602
Test name
Test status
Simulation time 530376608575 ps
CPU time 56.77 seconds
Started Jul 20 05:57:22 PM PDT 24
Finished Jul 20 05:58:19 PM PDT 24
Peak memory 201732 kb
Host smart-a67c97dd-803e-450e-a9ff-b50d4013bd3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679769623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3679769623
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.218767362
Short name T196
Test name
Test status
Simulation time 331412854469 ps
CPU time 296.14 seconds
Started Jul 20 05:57:19 PM PDT 24
Finished Jul 20 06:02:16 PM PDT 24
Peak memory 210392 kb
Host smart-4e64c512-4160-49c4-bd37-db8e87cfbb18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218767362 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.218767362
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3501724959
Short name T64
Test name
Test status
Simulation time 488896289 ps
CPU time 0.91 seconds
Started Jul 20 05:57:29 PM PDT 24
Finished Jul 20 05:57:30 PM PDT 24
Peak memory 201444 kb
Host smart-99fa41b8-6b15-4bd1-9b06-ef366858cf6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501724959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3501724959
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.2323830083
Short name T313
Test name
Test status
Simulation time 571507237080 ps
CPU time 496.82 seconds
Started Jul 20 05:57:30 PM PDT 24
Finished Jul 20 06:05:47 PM PDT 24
Peak memory 201752 kb
Host smart-697b91dd-faec-41ae-8935-d99802aba981
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323830083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.2323830083
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3240648528
Short name T296
Test name
Test status
Simulation time 161931695106 ps
CPU time 285.91 seconds
Started Jul 20 05:57:30 PM PDT 24
Finished Jul 20 06:02:17 PM PDT 24
Peak memory 201700 kb
Host smart-52c604b2-4ada-45be-9db0-ce505b26ec7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240648528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3240648528
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2224152947
Short name T390
Test name
Test status
Simulation time 167982239983 ps
CPU time 88.51 seconds
Started Jul 20 05:57:27 PM PDT 24
Finished Jul 20 05:58:56 PM PDT 24
Peak memory 201720 kb
Host smart-c798b66e-fe93-4041-8d39-aae40327062c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224152947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2224152947
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3628941046
Short name T430
Test name
Test status
Simulation time 160925250982 ps
CPU time 68.96 seconds
Started Jul 20 05:57:33 PM PDT 24
Finished Jul 20 05:58:42 PM PDT 24
Peak memory 201744 kb
Host smart-9ee5f4df-be7e-4e63-81b4-4bfabc848147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628941046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3628941046
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3605445669
Short name T491
Test name
Test status
Simulation time 490938580350 ps
CPU time 297.72 seconds
Started Jul 20 05:57:30 PM PDT 24
Finished Jul 20 06:02:29 PM PDT 24
Peak memory 201740 kb
Host smart-67c47068-c4db-4f27-856f-d87da3738678
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605445669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3605445669
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3206540603
Short name T431
Test name
Test status
Simulation time 194900363320 ps
CPU time 446.08 seconds
Started Jul 20 05:57:31 PM PDT 24
Finished Jul 20 06:04:57 PM PDT 24
Peak memory 201788 kb
Host smart-b4af72f3-e565-4614-af3b-10a122f9edf8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206540603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3206540603
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.211668548
Short name T695
Test name
Test status
Simulation time 95212203817 ps
CPU time 312.29 seconds
Started Jul 20 05:57:31 PM PDT 24
Finished Jul 20 06:02:43 PM PDT 24
Peak memory 202120 kb
Host smart-db257238-4eec-45fa-9b46-65b2210ad341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211668548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.211668548
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1391063616
Short name T529
Test name
Test status
Simulation time 42232117603 ps
CPU time 103.68 seconds
Started Jul 20 05:57:31 PM PDT 24
Finished Jul 20 05:59:16 PM PDT 24
Peak memory 201604 kb
Host smart-1afc1bb5-016e-48ae-bf68-fe270b3baeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391063616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1391063616
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.2638567289
Short name T540
Test name
Test status
Simulation time 3309694168 ps
CPU time 2 seconds
Started Jul 20 05:57:32 PM PDT 24
Finished Jul 20 05:57:34 PM PDT 24
Peak memory 201576 kb
Host smart-e60c8b90-7c18-4ed6-9b38-2500ca8200df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638567289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.2638567289
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2377409555
Short name T607
Test name
Test status
Simulation time 6077149631 ps
CPU time 15.39 seconds
Started Jul 20 05:57:28 PM PDT 24
Finished Jul 20 05:57:45 PM PDT 24
Peak memory 201608 kb
Host smart-2928f51f-767c-459d-8264-f6be7a776f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377409555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2377409555
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1076203058
Short name T698
Test name
Test status
Simulation time 163670887148 ps
CPU time 598.88 seconds
Started Jul 20 05:57:31 PM PDT 24
Finished Jul 20 06:07:31 PM PDT 24
Peak memory 210304 kb
Host smart-58c5a804-3696-4ae4-ae81-cbb9bcd3704d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076203058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1076203058
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3100167333
Short name T244
Test name
Test status
Simulation time 28661365466 ps
CPU time 42.56 seconds
Started Jul 20 05:57:31 PM PDT 24
Finished Jul 20 05:58:15 PM PDT 24
Peak memory 201872 kb
Host smart-53cf3181-6d06-43d6-ad76-8bea1c0cc908
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100167333 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3100167333
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.2261666551
Short name T697
Test name
Test status
Simulation time 471528587 ps
CPU time 1.69 seconds
Started Jul 20 05:57:40 PM PDT 24
Finished Jul 20 05:57:43 PM PDT 24
Peak memory 201532 kb
Host smart-126858f1-fb54-4d89-8912-dd91bb58a0b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261666551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.2261666551
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2431744317
Short name T687
Test name
Test status
Simulation time 175936270402 ps
CPU time 93.46 seconds
Started Jul 20 05:57:37 PM PDT 24
Finished Jul 20 05:59:11 PM PDT 24
Peak memory 201772 kb
Host smart-e53d92bc-1cde-497d-a56d-a4c0f9fabb16
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431744317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2431744317
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.787513546
Short name T255
Test name
Test status
Simulation time 162058655694 ps
CPU time 377.9 seconds
Started Jul 20 05:57:40 PM PDT 24
Finished Jul 20 06:03:59 PM PDT 24
Peak memory 201744 kb
Host smart-1cd20cf5-af15-46a5-919f-574030db85ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787513546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.787513546
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3310506407
Short name T617
Test name
Test status
Simulation time 167664278243 ps
CPU time 372.97 seconds
Started Jul 20 05:57:30 PM PDT 24
Finished Jul 20 06:03:44 PM PDT 24
Peak memory 201744 kb
Host smart-af65aa23-8cca-433e-b80b-c261782b8b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310506407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3310506407
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.833181321
Short name T380
Test name
Test status
Simulation time 162115424907 ps
CPU time 68.01 seconds
Started Jul 20 05:57:40 PM PDT 24
Finished Jul 20 05:58:48 PM PDT 24
Peak memory 201712 kb
Host smart-77c29cab-7fed-481c-962a-158252c9e2f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=833181321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.833181321
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2703861707
Short name T166
Test name
Test status
Simulation time 485835130013 ps
CPU time 264.81 seconds
Started Jul 20 05:57:31 PM PDT 24
Finished Jul 20 06:01:57 PM PDT 24
Peak memory 201732 kb
Host smart-d2be7072-7a55-43d1-a38e-862f6ef87b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703861707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2703861707
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1525220858
Short name T444
Test name
Test status
Simulation time 494343072769 ps
CPU time 208.32 seconds
Started Jul 20 05:57:31 PM PDT 24
Finished Jul 20 06:01:01 PM PDT 24
Peak memory 201736 kb
Host smart-f8b1c2d4-3a90-4c43-b02d-c74ec66d26d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525220858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1525220858
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3416115487
Short name T561
Test name
Test status
Simulation time 585852001393 ps
CPU time 685.59 seconds
Started Jul 20 05:57:38 PM PDT 24
Finished Jul 20 06:09:04 PM PDT 24
Peak memory 201760 kb
Host smart-44353439-cdca-4ad8-8f9b-5d1e015acaeb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416115487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3416115487
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2002505314
Short name T463
Test name
Test status
Simulation time 122830947164 ps
CPU time 456.74 seconds
Started Jul 20 05:57:37 PM PDT 24
Finished Jul 20 06:05:14 PM PDT 24
Peak memory 202236 kb
Host smart-91dbb057-0d77-4d4a-ab24-6f04c6502d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002505314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2002505314
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1586624370
Short name T632
Test name
Test status
Simulation time 25746210871 ps
CPU time 31.54 seconds
Started Jul 20 05:57:40 PM PDT 24
Finished Jul 20 05:58:13 PM PDT 24
Peak memory 201580 kb
Host smart-dd9749ea-b79e-4476-83a1-4c1419b207f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586624370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1586624370
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3956110408
Short name T161
Test name
Test status
Simulation time 3275347729 ps
CPU time 2.19 seconds
Started Jul 20 05:57:37 PM PDT 24
Finished Jul 20 05:57:40 PM PDT 24
Peak memory 201732 kb
Host smart-3cbc8b45-719d-49a6-a21c-b6393efc9072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956110408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3956110408
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.4095811444
Short name T543
Test name
Test status
Simulation time 5845852781 ps
CPU time 3.76 seconds
Started Jul 20 05:57:31 PM PDT 24
Finished Jul 20 05:57:36 PM PDT 24
Peak memory 201596 kb
Host smart-303b6765-15a0-4141-a952-f1ba74c1ffe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095811444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.4095811444
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1242848607
Short name T758
Test name
Test status
Simulation time 249059165427 ps
CPU time 407.51 seconds
Started Jul 20 05:57:40 PM PDT 24
Finished Jul 20 06:04:28 PM PDT 24
Peak memory 201800 kb
Host smart-1b68d827-3224-4012-bb05-81d532ba326b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242848607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1242848607
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.53905826
Short name T331
Test name
Test status
Simulation time 12891596895 ps
CPU time 31.77 seconds
Started Jul 20 05:57:39 PM PDT 24
Finished Jul 20 05:58:11 PM PDT 24
Peak memory 210076 kb
Host smart-cef465ce-1e44-4cf0-b0f5-1dc1d10148ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53905826 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.53905826
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2558593297
Short name T603
Test name
Test status
Simulation time 344681725 ps
CPU time 1.03 seconds
Started Jul 20 05:57:48 PM PDT 24
Finished Jul 20 05:57:49 PM PDT 24
Peak memory 201544 kb
Host smart-7e95cdcb-0e60-45a6-9eb5-b7d47dd23004
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558593297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2558593297
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.365286946
Short name T250
Test name
Test status
Simulation time 330850863512 ps
CPU time 201.25 seconds
Started Jul 20 05:57:40 PM PDT 24
Finished Jul 20 06:01:02 PM PDT 24
Peak memory 201748 kb
Host smart-bf3fcf6c-7191-4114-aa78-b41816905fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365286946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.365286946
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1732461810
Short name T455
Test name
Test status
Simulation time 161635071226 ps
CPU time 171.61 seconds
Started Jul 20 05:57:41 PM PDT 24
Finished Jul 20 06:00:33 PM PDT 24
Peak memory 201732 kb
Host smart-ef28821e-ee11-4955-8cac-b24dd8352efb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732461810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.1732461810
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3058581478
Short name T15
Test name
Test status
Simulation time 494095247546 ps
CPU time 558.57 seconds
Started Jul 20 05:57:39 PM PDT 24
Finished Jul 20 06:06:58 PM PDT 24
Peak memory 201800 kb
Host smart-744675ec-d882-4d5f-b689-faebb872a5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058581478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3058581478
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.72809604
Short name T485
Test name
Test status
Simulation time 487245292478 ps
CPU time 1173.14 seconds
Started Jul 20 05:57:36 PM PDT 24
Finished Jul 20 06:17:09 PM PDT 24
Peak memory 201720 kb
Host smart-63de2cdb-2970-4f5a-8bd0-7986f4212841
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=72809604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixed
.72809604
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1932561846
Short name T784
Test name
Test status
Simulation time 413490559837 ps
CPU time 166.75 seconds
Started Jul 20 05:57:39 PM PDT 24
Finished Jul 20 06:00:26 PM PDT 24
Peak memory 201732 kb
Host smart-ae63de00-d6ec-44b9-a046-1333c9e03d62
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932561846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1932561846
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1649485616
Short name T596
Test name
Test status
Simulation time 593408096603 ps
CPU time 1315.75 seconds
Started Jul 20 05:57:40 PM PDT 24
Finished Jul 20 06:19:37 PM PDT 24
Peak memory 201712 kb
Host smart-576f63e6-5455-45ba-bd3b-033f4d9f5713
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649485616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.1649485616
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3392432708
Short name T701
Test name
Test status
Simulation time 107542081569 ps
CPU time 374.14 seconds
Started Jul 20 05:57:48 PM PDT 24
Finished Jul 20 06:04:03 PM PDT 24
Peak memory 202080 kb
Host smart-b0675afc-5632-45b2-a035-ed3f42cc3f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392432708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3392432708
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.749752470
Short name T412
Test name
Test status
Simulation time 35615240401 ps
CPU time 20.31 seconds
Started Jul 20 05:57:48 PM PDT 24
Finished Jul 20 05:58:09 PM PDT 24
Peak memory 201612 kb
Host smart-d9245dd5-0b2d-47e8-842f-811bc3f17bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749752470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.749752470
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2799114842
Short name T699
Test name
Test status
Simulation time 3304065140 ps
CPU time 2.71 seconds
Started Jul 20 05:57:49 PM PDT 24
Finished Jul 20 05:57:52 PM PDT 24
Peak memory 201608 kb
Host smart-5eabe193-205e-474e-a15e-56993cda68d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799114842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2799114842
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.823594935
Short name T690
Test name
Test status
Simulation time 5971544358 ps
CPU time 1.74 seconds
Started Jul 20 05:57:39 PM PDT 24
Finished Jul 20 05:57:41 PM PDT 24
Peak memory 201600 kb
Host smart-70deec26-83f5-4b35-95d9-4f60873f980d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823594935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.823594935
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1526958576
Short name T746
Test name
Test status
Simulation time 181249299753 ps
CPU time 395.45 seconds
Started Jul 20 05:57:46 PM PDT 24
Finished Jul 20 06:04:22 PM PDT 24
Peak memory 201636 kb
Host smart-faafc86b-38e0-4c98-a95d-7e9c9f7c5f16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526958576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1526958576
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2708118465
Short name T144
Test name
Test status
Simulation time 147989249853 ps
CPU time 291.34 seconds
Started Jul 20 05:57:49 PM PDT 24
Finished Jul 20 06:02:41 PM PDT 24
Peak memory 210400 kb
Host smart-fe6b63ac-1607-40c4-958e-076c8d492fd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708118465 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2708118465
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1662960840
Short name T736
Test name
Test status
Simulation time 433795223 ps
CPU time 0.74 seconds
Started Jul 20 05:57:54 PM PDT 24
Finished Jul 20 05:57:55 PM PDT 24
Peak memory 201536 kb
Host smart-af5cef57-6b5f-4fd8-ab5d-c702c6ea974f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662960840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1662960840
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.2523084692
Short name T640
Test name
Test status
Simulation time 187168571137 ps
CPU time 416.92 seconds
Started Jul 20 05:57:57 PM PDT 24
Finished Jul 20 06:04:54 PM PDT 24
Peak memory 201740 kb
Host smart-b8059169-da9b-4475-9d8b-f7a3b992b536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523084692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2523084692
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2395859686
Short name T635
Test name
Test status
Simulation time 164615183195 ps
CPU time 194.9 seconds
Started Jul 20 05:57:58 PM PDT 24
Finished Jul 20 06:01:13 PM PDT 24
Peak memory 201744 kb
Host smart-8aa61ea0-b965-43c9-b7ab-51b93c5c6988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395859686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2395859686
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1538906813
Short name T606
Test name
Test status
Simulation time 492693309291 ps
CPU time 556.2 seconds
Started Jul 20 05:57:59 PM PDT 24
Finished Jul 20 06:07:16 PM PDT 24
Peak memory 201704 kb
Host smart-fd5de396-7165-4f65-898c-7e6214cad023
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538906813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1538906813
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3596871345
Short name T158
Test name
Test status
Simulation time 163372947861 ps
CPU time 398.31 seconds
Started Jul 20 05:57:47 PM PDT 24
Finished Jul 20 06:04:26 PM PDT 24
Peak memory 201736 kb
Host smart-cb851646-646f-42f4-8be5-090728ecaaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596871345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3596871345
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3646072110
Short name T558
Test name
Test status
Simulation time 166043658799 ps
CPU time 21.72 seconds
Started Jul 20 05:57:59 PM PDT 24
Finished Jul 20 05:58:21 PM PDT 24
Peak memory 201716 kb
Host smart-ee58fc68-fe26-4438-8fd2-2eacfb47df21
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646072110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3646072110
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.203941005
Short name T590
Test name
Test status
Simulation time 355307991546 ps
CPU time 427.36 seconds
Started Jul 20 05:57:55 PM PDT 24
Finished Jul 20 06:05:03 PM PDT 24
Peak memory 201740 kb
Host smart-d2f8ccd8-e631-4514-a599-635698c83ac8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203941005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.203941005
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3222296547
Short name T159
Test name
Test status
Simulation time 601882136832 ps
CPU time 1427.06 seconds
Started Jul 20 05:57:56 PM PDT 24
Finished Jul 20 06:21:44 PM PDT 24
Peak memory 201712 kb
Host smart-80bdb530-af45-428b-b580-b50ac720fefc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222296547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3222296547
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.414403109
Short name T481
Test name
Test status
Simulation time 118471777743 ps
CPU time 354.16 seconds
Started Jul 20 05:57:57 PM PDT 24
Finished Jul 20 06:03:51 PM PDT 24
Peak memory 202052 kb
Host smart-5cac2506-e024-4403-8b5a-ff3dffbfbc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414403109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.414403109
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3898869536
Short name T654
Test name
Test status
Simulation time 44739491039 ps
CPU time 43.68 seconds
Started Jul 20 05:57:55 PM PDT 24
Finished Jul 20 05:58:39 PM PDT 24
Peak memory 201600 kb
Host smart-74f8f287-6ffa-413c-851b-cabf8bfd9a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898869536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3898869536
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1479868753
Short name T375
Test name
Test status
Simulation time 3017148324 ps
CPU time 2.41 seconds
Started Jul 20 05:57:56 PM PDT 24
Finished Jul 20 05:57:59 PM PDT 24
Peak memory 201552 kb
Host smart-9ed708f0-3cf6-49d4-9ea3-ea5086e38c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479868753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1479868753
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.4133622914
Short name T751
Test name
Test status
Simulation time 5689217519 ps
CPU time 13.79 seconds
Started Jul 20 05:57:45 PM PDT 24
Finished Jul 20 05:57:59 PM PDT 24
Peak memory 201576 kb
Host smart-1ca37042-3b99-4741-a8e2-4963346460aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133622914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.4133622914
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3513756276
Short name T204
Test name
Test status
Simulation time 271492487094 ps
CPU time 871.48 seconds
Started Jul 20 05:57:53 PM PDT 24
Finished Jul 20 06:12:25 PM PDT 24
Peak memory 202028 kb
Host smart-3287198a-11c9-4ff9-9b1b-ae1434505648
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513756276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3513756276
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3588116426
Short name T79
Test name
Test status
Simulation time 128262999068 ps
CPU time 92.51 seconds
Started Jul 20 05:57:58 PM PDT 24
Finished Jul 20 05:59:31 PM PDT 24
Peak memory 210756 kb
Host smart-7d53ea18-d4e9-42f5-859f-f6e33850ec81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588116426 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3588116426
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1849946375
Short name T670
Test name
Test status
Simulation time 466884171 ps
CPU time 0.66 seconds
Started Jul 20 05:58:04 PM PDT 24
Finished Jul 20 05:58:05 PM PDT 24
Peak memory 201544 kb
Host smart-ad46d908-9490-455a-b7b4-1fd7f5d2a396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849946375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1849946375
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3339029431
Short name T300
Test name
Test status
Simulation time 400564510831 ps
CPU time 305.3 seconds
Started Jul 20 05:58:03 PM PDT 24
Finished Jul 20 06:03:09 PM PDT 24
Peak memory 201800 kb
Host smart-072b1496-64de-4ef4-8634-58f247fd460b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339029431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3339029431
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.4254744212
Short name T535
Test name
Test status
Simulation time 159801321828 ps
CPU time 377.04 seconds
Started Jul 20 05:58:03 PM PDT 24
Finished Jul 20 06:04:21 PM PDT 24
Peak memory 201764 kb
Host smart-3b8103b2-71c7-4a16-83db-6ede091318c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254744212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.4254744212
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3788043337
Short name T288
Test name
Test status
Simulation time 331650673566 ps
CPU time 64.64 seconds
Started Jul 20 05:58:06 PM PDT 24
Finished Jul 20 05:59:11 PM PDT 24
Peak memory 201812 kb
Host smart-b4c91062-3900-471e-90c5-513159ebfc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788043337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3788043337
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2468784043
Short name T467
Test name
Test status
Simulation time 325712961084 ps
CPU time 189.62 seconds
Started Jul 20 05:58:00 PM PDT 24
Finished Jul 20 06:01:10 PM PDT 24
Peak memory 201732 kb
Host smart-d0b67502-957e-4630-81c3-161d1acc851d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468784043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2468784043
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2102182214
Short name T126
Test name
Test status
Simulation time 327155285458 ps
CPU time 180.8 seconds
Started Jul 20 05:57:53 PM PDT 24
Finished Jul 20 06:00:54 PM PDT 24
Peak memory 201708 kb
Host smart-8795d62a-7dd3-4034-9f0f-64cf7016869d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102182214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2102182214
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.2663456041
Short name T766
Test name
Test status
Simulation time 163658198669 ps
CPU time 197.65 seconds
Started Jul 20 05:57:57 PM PDT 24
Finished Jul 20 06:01:16 PM PDT 24
Peak memory 201712 kb
Host smart-fe25719d-3efc-482e-a7b6-be98612b694d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663456041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.2663456041
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1147110086
Short name T284
Test name
Test status
Simulation time 167200025882 ps
CPU time 352.96 seconds
Started Jul 20 05:58:01 PM PDT 24
Finished Jul 20 06:03:54 PM PDT 24
Peak memory 201792 kb
Host smart-2ff39c3b-04cf-4480-a057-69209a640d8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147110086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1147110086
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2432641533
Short name T565
Test name
Test status
Simulation time 383308329716 ps
CPU time 686.93 seconds
Started Jul 20 05:58:01 PM PDT 24
Finished Jul 20 06:09:28 PM PDT 24
Peak memory 201780 kb
Host smart-0ad0c3f6-d225-4570-8415-bdb79b9de1cf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432641533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2432641533
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.753774123
Short name T200
Test name
Test status
Simulation time 81796901811 ps
CPU time 474.19 seconds
Started Jul 20 05:58:04 PM PDT 24
Finished Jul 20 06:05:59 PM PDT 24
Peak memory 202156 kb
Host smart-4c6b03b4-8a63-4b68-b60f-a58ac575a0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753774123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.753774123
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1701399710
Short name T534
Test name
Test status
Simulation time 32562673245 ps
CPU time 27.09 seconds
Started Jul 20 05:58:04 PM PDT 24
Finished Jul 20 05:58:31 PM PDT 24
Peak memory 201584 kb
Host smart-580fa3c8-ea5b-4832-9aea-5e3235c3d0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701399710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1701399710
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.820736248
Short name T396
Test name
Test status
Simulation time 5167319564 ps
CPU time 12.95 seconds
Started Jul 20 05:58:06 PM PDT 24
Finished Jul 20 05:58:19 PM PDT 24
Peak memory 201600 kb
Host smart-d92571af-8b88-472d-9493-ad8144b7bdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820736248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.820736248
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3636482158
Short name T713
Test name
Test status
Simulation time 5923607920 ps
CPU time 13.43 seconds
Started Jul 20 05:57:55 PM PDT 24
Finished Jul 20 05:58:08 PM PDT 24
Peak memory 201608 kb
Host smart-de180880-36a4-4794-83fa-2d8c8a7bccfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636482158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3636482158
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.101007989
Short name T260
Test name
Test status
Simulation time 170995375188 ps
CPU time 131.91 seconds
Started Jul 20 05:58:03 PM PDT 24
Finished Jul 20 06:00:15 PM PDT 24
Peak memory 201788 kb
Host smart-05074526-7451-4c9f-a6ab-9f2763e0d182
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101007989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
101007989
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.4220784516
Short name T37
Test name
Test status
Simulation time 27306694325 ps
CPU time 56.97 seconds
Started Jul 20 05:58:04 PM PDT 24
Finished Jul 20 05:59:01 PM PDT 24
Peak memory 210480 kb
Host smart-c7f65592-04a0-4ab0-bd04-675fb22d9377
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220784516 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.4220784516
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1864466093
Short name T608
Test name
Test status
Simulation time 470547757 ps
CPU time 1.43 seconds
Started Jul 20 05:56:34 PM PDT 24
Finished Jul 20 05:56:38 PM PDT 24
Peak memory 201456 kb
Host smart-d4c8623a-1044-486a-82e6-4f43dee029cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864466093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1864466093
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3178289835
Short name T329
Test name
Test status
Simulation time 518982450590 ps
CPU time 176.13 seconds
Started Jul 20 05:56:37 PM PDT 24
Finished Jul 20 05:59:35 PM PDT 24
Peak memory 201676 kb
Host smart-80b4fbad-2a62-4e4e-a2d0-ce97a93ff4c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178289835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3178289835
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3260780734
Short name T325
Test name
Test status
Simulation time 327499555450 ps
CPU time 113.31 seconds
Started Jul 20 05:56:28 PM PDT 24
Finished Jul 20 05:58:23 PM PDT 24
Peak memory 201740 kb
Host smart-0c5413db-1488-4a46-95ab-7b1c02fb3897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260780734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3260780734
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2369480287
Short name T305
Test name
Test status
Simulation time 331371528329 ps
CPU time 398.01 seconds
Started Jul 20 05:56:34 PM PDT 24
Finished Jul 20 06:03:15 PM PDT 24
Peak memory 201800 kb
Host smart-d40b2aa7-cd66-43af-811a-9602bc50b870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369480287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2369480287
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.21353609
Short name T581
Test name
Test status
Simulation time 165135385922 ps
CPU time 370.21 seconds
Started Jul 20 05:56:37 PM PDT 24
Finished Jul 20 06:02:49 PM PDT 24
Peak memory 201716 kb
Host smart-0dbeb197-c190-40e0-a748-42429a6ba514
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=21353609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt_
fixed.21353609
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1693380751
Short name T554
Test name
Test status
Simulation time 166788260366 ps
CPU time 103.8 seconds
Started Jul 20 05:56:33 PM PDT 24
Finished Jul 20 05:58:20 PM PDT 24
Peak memory 201684 kb
Host smart-66ecfe0c-d684-4afe-bf80-6683536e9bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693380751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1693380751
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1662232344
Short name T502
Test name
Test status
Simulation time 162661720467 ps
CPU time 77.88 seconds
Started Jul 20 05:56:32 PM PDT 24
Finished Jul 20 05:57:53 PM PDT 24
Peak memory 201680 kb
Host smart-dac135c0-9971-450b-82d6-e827f42a5b76
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662232344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1662232344
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3076780691
Short name T372
Test name
Test status
Simulation time 404642111693 ps
CPU time 443.36 seconds
Started Jul 20 05:56:36 PM PDT 24
Finished Jul 20 06:04:02 PM PDT 24
Peak memory 201444 kb
Host smart-b8ff968a-a0e2-4dc7-aa9d-b4beeb91b73c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076780691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3076780691
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1236748529
Short name T180
Test name
Test status
Simulation time 95146749557 ps
CPU time 385.44 seconds
Started Jul 20 05:56:31 PM PDT 24
Finished Jul 20 06:02:59 PM PDT 24
Peak memory 202000 kb
Host smart-bfa7a740-0e01-4bdc-8578-bbf3b3bb41d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236748529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1236748529
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.1064541328
Short name T773
Test name
Test status
Simulation time 24841114512 ps
CPU time 59.34 seconds
Started Jul 20 05:56:32 PM PDT 24
Finished Jul 20 05:57:34 PM PDT 24
Peak memory 201600 kb
Host smart-d447616f-e2b1-41d3-9d31-e336d7f044b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064541328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.1064541328
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.4120329286
Short name T622
Test name
Test status
Simulation time 4985031548 ps
CPU time 6.98 seconds
Started Jul 20 05:56:33 PM PDT 24
Finished Jul 20 05:56:43 PM PDT 24
Peak memory 201596 kb
Host smart-27cd46ae-bde2-4f39-bacd-dd1fd922411b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120329286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.4120329286
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.2944651754
Short name T71
Test name
Test status
Simulation time 4640265473 ps
CPU time 3.59 seconds
Started Jul 20 05:56:30 PM PDT 24
Finished Jul 20 05:56:36 PM PDT 24
Peak memory 217216 kb
Host smart-5678637e-c541-42dc-a3e5-b1d66e71ed8d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944651754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2944651754
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.261069932
Short name T378
Test name
Test status
Simulation time 5731926814 ps
CPU time 14.65 seconds
Started Jul 20 05:56:34 PM PDT 24
Finished Jul 20 05:56:51 PM PDT 24
Peak memory 201552 kb
Host smart-7dd6251b-2caa-4e15-9211-f15d12a0f038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261069932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.261069932
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.4180494877
Short name T36
Test name
Test status
Simulation time 155908851747 ps
CPU time 375.52 seconds
Started Jul 20 05:56:40 PM PDT 24
Finished Jul 20 06:02:56 PM PDT 24
Peak memory 210440 kb
Host smart-75853d05-aa2f-480f-90e2-be2347886adb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180494877 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.4180494877
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3584881563
Short name T382
Test name
Test status
Simulation time 615848873 ps
CPU time 0.69 seconds
Started Jul 20 05:58:13 PM PDT 24
Finished Jul 20 05:58:14 PM PDT 24
Peak memory 201540 kb
Host smart-bedec10c-83d4-4772-b4d1-7d250301e375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584881563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3584881563
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3243151297
Short name T262
Test name
Test status
Simulation time 563348806206 ps
CPU time 891.87 seconds
Started Jul 20 05:58:12 PM PDT 24
Finished Jul 20 06:13:05 PM PDT 24
Peak memory 201656 kb
Host smart-53c6757d-0769-455e-afc7-c28bdbd533b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243151297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3243151297
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1108933463
Short name T513
Test name
Test status
Simulation time 487330038367 ps
CPU time 1165.8 seconds
Started Jul 20 05:58:12 PM PDT 24
Finished Jul 20 06:17:38 PM PDT 24
Peak memory 201624 kb
Host smart-ded8f516-a0ad-4b97-b4e2-ec8268808266
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108933463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1108933463
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.1280136388
Short name T119
Test name
Test status
Simulation time 495048616373 ps
CPU time 1055.95 seconds
Started Jul 20 05:58:11 PM PDT 24
Finished Jul 20 06:15:47 PM PDT 24
Peak memory 201716 kb
Host smart-27b611d4-68cc-4cee-a228-d346e5053826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280136388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1280136388
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3267167114
Short name T426
Test name
Test status
Simulation time 165825751964 ps
CPU time 374.61 seconds
Started Jul 20 05:58:13 PM PDT 24
Finished Jul 20 06:04:28 PM PDT 24
Peak memory 201756 kb
Host smart-a239e0a0-1b00-46e8-bc7b-1f116fd92290
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267167114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3267167114
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2568759101
Short name T219
Test name
Test status
Simulation time 262830471280 ps
CPU time 313.15 seconds
Started Jul 20 05:58:15 PM PDT 24
Finished Jul 20 06:03:29 PM PDT 24
Peak memory 201736 kb
Host smart-f6746e46-66f6-418b-a7b9-acfa098c3ac0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568759101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2568759101
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2823273508
Short name T663
Test name
Test status
Simulation time 604530775143 ps
CPU time 1318.11 seconds
Started Jul 20 05:58:11 PM PDT 24
Finished Jul 20 06:20:09 PM PDT 24
Peak memory 201608 kb
Host smart-3b4e3104-79e9-4f22-be1a-56d0be5fc00b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823273508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2823273508
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.552578442
Short name T563
Test name
Test status
Simulation time 109499490007 ps
CPU time 592.25 seconds
Started Jul 20 05:58:15 PM PDT 24
Finished Jul 20 06:08:08 PM PDT 24
Peak memory 202172 kb
Host smart-4df19a1d-44e8-4a87-ae64-b128d6efa89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552578442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.552578442
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3955695555
Short name T631
Test name
Test status
Simulation time 22567268696 ps
CPU time 50.8 seconds
Started Jul 20 05:58:12 PM PDT 24
Finished Jul 20 05:59:03 PM PDT 24
Peak memory 201600 kb
Host smart-9270ed13-03fd-4bb4-a74b-d95216183a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955695555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3955695555
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.2676597014
Short name T343
Test name
Test status
Simulation time 4976986885 ps
CPU time 11.79 seconds
Started Jul 20 05:58:11 PM PDT 24
Finished Jul 20 05:58:24 PM PDT 24
Peak memory 201604 kb
Host smart-089a148b-73ae-493c-b9d8-384561464e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676597014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2676597014
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.568667282
Short name T479
Test name
Test status
Simulation time 6118441614 ps
CPU time 14.44 seconds
Started Jul 20 05:58:03 PM PDT 24
Finished Jul 20 05:58:18 PM PDT 24
Peak memory 201600 kb
Host smart-814d9ba8-3e48-4a8c-9fdd-addd5452e08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568667282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.568667282
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1486292120
Short name T747
Test name
Test status
Simulation time 622889788414 ps
CPU time 552.52 seconds
Started Jul 20 05:58:13 PM PDT 24
Finished Jul 20 06:07:26 PM PDT 24
Peak memory 210300 kb
Host smart-fedf8d61-dd94-4a7c-9d54-cb4325a96e1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486292120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1486292120
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.79601359
Short name T82
Test name
Test status
Simulation time 37534283078 ps
CPU time 46.86 seconds
Started Jul 20 05:58:11 PM PDT 24
Finished Jul 20 05:58:59 PM PDT 24
Peak memory 210496 kb
Host smart-863cebc0-1ba7-419d-9d72-59ea6dc207ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79601359 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.79601359
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.1595882451
Short name T560
Test name
Test status
Simulation time 427870821 ps
CPU time 1.53 seconds
Started Jul 20 05:58:24 PM PDT 24
Finished Jul 20 05:58:26 PM PDT 24
Peak memory 201556 kb
Host smart-cf168ac6-08e9-4cf4-acf3-eec343406fd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595882451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1595882451
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1027297826
Short name T760
Test name
Test status
Simulation time 340716464690 ps
CPU time 542.26 seconds
Started Jul 20 05:58:21 PM PDT 24
Finished Jul 20 06:07:24 PM PDT 24
Peak memory 201740 kb
Host smart-6b5a992e-3376-4dab-8df9-7d55acf36515
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027297826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1027297826
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.171986155
Short name T762
Test name
Test status
Simulation time 333572430286 ps
CPU time 200.66 seconds
Started Jul 20 05:58:20 PM PDT 24
Finished Jul 20 06:01:40 PM PDT 24
Peak memory 201928 kb
Host smart-0ea85395-3110-473b-aefd-d0a3493437b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171986155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.171986155
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.839253813
Short name T416
Test name
Test status
Simulation time 156522605757 ps
CPU time 106.37 seconds
Started Jul 20 05:58:23 PM PDT 24
Finished Jul 20 06:00:10 PM PDT 24
Peak memory 201716 kb
Host smart-32085431-d323-43d8-a61f-23ed706c9be2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=839253813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.839253813
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2436937849
Short name T679
Test name
Test status
Simulation time 158878001597 ps
CPU time 187.95 seconds
Started Jul 20 05:58:10 PM PDT 24
Finished Jul 20 06:01:18 PM PDT 24
Peak memory 201808 kb
Host smart-c93e0eb4-c7d3-4462-9f86-04fb97acf0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436937849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2436937849
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3458234524
Short name T3
Test name
Test status
Simulation time 488934590471 ps
CPU time 1021.95 seconds
Started Jul 20 05:58:12 PM PDT 24
Finished Jul 20 06:15:14 PM PDT 24
Peak memory 201736 kb
Host smart-2e1b8de7-39b1-40fc-a799-f797aae219d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458234524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3458234524
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3217059636
Short name T183
Test name
Test status
Simulation time 177956023112 ps
CPU time 396.71 seconds
Started Jul 20 05:58:20 PM PDT 24
Finished Jul 20 06:04:57 PM PDT 24
Peak memory 201648 kb
Host smart-3ca0b8b7-1c83-4299-9652-d57c2569595a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217059636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3217059636
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2508942911
Short name T503
Test name
Test status
Simulation time 399960755359 ps
CPU time 218.79 seconds
Started Jul 20 05:58:23 PM PDT 24
Finished Jul 20 06:02:02 PM PDT 24
Peak memory 201784 kb
Host smart-29eb1909-2477-4efe-b34b-4806236aea7c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508942911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.2508942911
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.4140021261
Short name T401
Test name
Test status
Simulation time 120601183651 ps
CPU time 453.99 seconds
Started Jul 20 05:58:23 PM PDT 24
Finished Jul 20 06:05:58 PM PDT 24
Peak memory 202156 kb
Host smart-975b0231-3613-4b59-a627-30b0b03c71ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140021261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.4140021261
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3493529621
Short name T440
Test name
Test status
Simulation time 41671232318 ps
CPU time 93.08 seconds
Started Jul 20 05:58:23 PM PDT 24
Finished Jul 20 05:59:56 PM PDT 24
Peak memory 201600 kb
Host smart-14186b09-b9b4-4ea2-8cd8-c9645962059d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493529621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3493529621
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3270776543
Short name T541
Test name
Test status
Simulation time 3859768154 ps
CPU time 10.04 seconds
Started Jul 20 05:58:22 PM PDT 24
Finished Jul 20 05:58:32 PM PDT 24
Peak memory 201596 kb
Host smart-f814c5cd-061b-41a1-95f7-9fe51ae84503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270776543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3270776543
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.810250747
Short name T492
Test name
Test status
Simulation time 5854559241 ps
CPU time 3.94 seconds
Started Jul 20 05:58:13 PM PDT 24
Finished Jul 20 05:58:18 PM PDT 24
Peak memory 201600 kb
Host smart-636a2313-f0c2-463a-9a45-afa5da3325cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810250747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.810250747
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1565740653
Short name T24
Test name
Test status
Simulation time 495138084579 ps
CPU time 822.42 seconds
Started Jul 20 05:58:22 PM PDT 24
Finished Jul 20 06:12:04 PM PDT 24
Peak memory 210584 kb
Host smart-094fba58-b596-4ca1-8a0f-0c318a686256
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565740653 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1565740653
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1513750511
Short name T680
Test name
Test status
Simulation time 379983757 ps
CPU time 0.72 seconds
Started Jul 20 05:58:37 PM PDT 24
Finished Jul 20 05:58:38 PM PDT 24
Peak memory 201548 kb
Host smart-61f73e4f-1622-44bf-a117-34547c34b5e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513750511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1513750511
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.2456214245
Short name T306
Test name
Test status
Simulation time 177506805328 ps
CPU time 205.96 seconds
Started Jul 20 05:58:28 PM PDT 24
Finished Jul 20 06:01:54 PM PDT 24
Peak memory 201696 kb
Host smart-de58b08b-f215-4385-9582-d2ba695312bc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456214245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.2456214245
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.935805531
Short name T614
Test name
Test status
Simulation time 157673346998 ps
CPU time 50.74 seconds
Started Jul 20 05:58:31 PM PDT 24
Finished Jul 20 05:59:22 PM PDT 24
Peak memory 201704 kb
Host smart-8e722501-0598-4b9b-a90c-d7cdd0844931
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=935805531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.935805531
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1082519343
Short name T33
Test name
Test status
Simulation time 156865505796 ps
CPU time 59.13 seconds
Started Jul 20 05:58:30 PM PDT 24
Finished Jul 20 05:59:29 PM PDT 24
Peak memory 201800 kb
Host smart-8cae223c-ad50-4126-bcd9-f42b3df406f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082519343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1082519343
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.920626789
Short name T139
Test name
Test status
Simulation time 485303840588 ps
CPU time 244.74 seconds
Started Jul 20 05:58:29 PM PDT 24
Finished Jul 20 06:02:34 PM PDT 24
Peak memory 201752 kb
Host smart-80a5de29-da69-4a88-be0b-cf78ba0dd38d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=920626789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.920626789
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1428108477
Short name T441
Test name
Test status
Simulation time 191123716306 ps
CPU time 454.26 seconds
Started Jul 20 05:58:28 PM PDT 24
Finished Jul 20 06:06:02 PM PDT 24
Peak memory 201748 kb
Host smart-f7316c23-4d12-4abb-9f35-0f61c4736604
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428108477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1428108477
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3656706561
Short name T517
Test name
Test status
Simulation time 599049053215 ps
CPU time 1355.02 seconds
Started Jul 20 05:58:30 PM PDT 24
Finished Jul 20 06:21:05 PM PDT 24
Peak memory 201740 kb
Host smart-8b3d37a4-b0dc-457c-a4e0-548765f19c68
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656706561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3656706561
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.1696894993
Short name T537
Test name
Test status
Simulation time 121058471027 ps
CPU time 448.53 seconds
Started Jul 20 05:58:36 PM PDT 24
Finished Jul 20 06:06:05 PM PDT 24
Peak memory 202096 kb
Host smart-e75d3915-8664-4ffe-8bb1-f625dfe1448c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696894993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1696894993
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3680914949
Short name T752
Test name
Test status
Simulation time 29347508482 ps
CPU time 32.8 seconds
Started Jul 20 05:58:38 PM PDT 24
Finished Jul 20 05:59:12 PM PDT 24
Peak memory 201604 kb
Host smart-b545b101-cf15-471d-95b6-3320589e927a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680914949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3680914949
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1514460660
Short name T662
Test name
Test status
Simulation time 3568187510 ps
CPU time 3.14 seconds
Started Jul 20 05:58:39 PM PDT 24
Finished Jul 20 05:58:43 PM PDT 24
Peak memory 201552 kb
Host smart-63323764-dbf3-4f82-aff6-e3730177558a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514460660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1514460660
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.247934913
Short name T767
Test name
Test status
Simulation time 5895871668 ps
CPU time 2.04 seconds
Started Jul 20 05:58:29 PM PDT 24
Finished Jul 20 05:58:32 PM PDT 24
Peak memory 201556 kb
Host smart-ada385bc-d19e-4d2a-bea1-109ed4046deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247934913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.247934913
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3632276888
Short name T506
Test name
Test status
Simulation time 152239158860 ps
CPU time 496.29 seconds
Started Jul 20 05:58:35 PM PDT 24
Finished Jul 20 06:06:52 PM PDT 24
Peak memory 210424 kb
Host smart-790edf2e-bf72-4a12-8bab-fe42efd19735
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632276888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3632276888
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3662993493
Short name T671
Test name
Test status
Simulation time 51422454916 ps
CPU time 124.87 seconds
Started Jul 20 05:58:38 PM PDT 24
Finished Jul 20 06:00:43 PM PDT 24
Peak memory 218604 kb
Host smart-8535e46a-90e5-4ed9-a45f-34c50499fba1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662993493 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3662993493
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2455076838
Short name T776
Test name
Test status
Simulation time 488887918 ps
CPU time 1.71 seconds
Started Jul 20 05:58:54 PM PDT 24
Finished Jul 20 05:58:57 PM PDT 24
Peak memory 201548 kb
Host smart-0900cec7-61b8-442c-9ca7-eeb98f934bb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455076838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2455076838
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.1954275001
Short name T261
Test name
Test status
Simulation time 349569754040 ps
CPU time 123.16 seconds
Started Jul 20 05:58:47 PM PDT 24
Finished Jul 20 06:00:51 PM PDT 24
Peak memory 201732 kb
Host smart-338bf531-68bc-4d56-8e80-14f4209dae1f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954275001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.1954275001
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1618874497
Short name T499
Test name
Test status
Simulation time 165512173529 ps
CPU time 377.18 seconds
Started Jul 20 05:58:45 PM PDT 24
Finished Jul 20 06:05:02 PM PDT 24
Peak memory 201736 kb
Host smart-577eedd6-da54-44f3-b7c2-fcba4f4e223e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618874497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1618874497
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1966327545
Short name T92
Test name
Test status
Simulation time 494417891410 ps
CPU time 1117.29 seconds
Started Jul 20 05:58:48 PM PDT 24
Finished Jul 20 06:17:26 PM PDT 24
Peak memory 201724 kb
Host smart-b56ef444-ed7d-4937-b454-334806e3b7e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966327545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1966327545
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2844177676
Short name T88
Test name
Test status
Simulation time 333182727134 ps
CPU time 100.45 seconds
Started Jul 20 05:58:39 PM PDT 24
Finished Jul 20 06:00:20 PM PDT 24
Peak memory 201740 kb
Host smart-308e53ec-2f14-4313-9aee-28e3bb34f1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844177676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2844177676
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.820947110
Short name T348
Test name
Test status
Simulation time 484045969668 ps
CPU time 1079.31 seconds
Started Jul 20 05:58:37 PM PDT 24
Finished Jul 20 06:16:37 PM PDT 24
Peak memory 201732 kb
Host smart-4e72dc67-b800-4068-b60d-1c7061a2dc91
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=820947110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.820947110
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.411361820
Short name T235
Test name
Test status
Simulation time 199656073437 ps
CPU time 451.17 seconds
Started Jul 20 05:58:46 PM PDT 24
Finished Jul 20 06:06:18 PM PDT 24
Peak memory 201808 kb
Host smart-b00298bd-8459-476e-a20a-c801ddf0ed23
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411361820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_
wakeup.411361820
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1632685973
Short name T578
Test name
Test status
Simulation time 198126713872 ps
CPU time 118.08 seconds
Started Jul 20 05:58:48 PM PDT 24
Finished Jul 20 06:00:46 PM PDT 24
Peak memory 201740 kb
Host smart-7e062b5f-470f-4e68-99f5-3407419719b5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632685973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1632685973
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2144044368
Short name T580
Test name
Test status
Simulation time 91688248748 ps
CPU time 485.4 seconds
Started Jul 20 05:58:46 PM PDT 24
Finished Jul 20 06:06:52 PM PDT 24
Peak memory 202128 kb
Host smart-a3439fe3-e53c-4c41-b1c0-c4a39538275e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144044368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2144044368
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.472648893
Short name T476
Test name
Test status
Simulation time 31953176907 ps
CPU time 50.92 seconds
Started Jul 20 05:58:44 PM PDT 24
Finished Jul 20 05:59:35 PM PDT 24
Peak memory 201592 kb
Host smart-181ed22b-643e-4bc6-bd66-dff1df80c94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472648893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.472648893
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.92680486
Short name T381
Test name
Test status
Simulation time 3208348269 ps
CPU time 7.77 seconds
Started Jul 20 05:58:46 PM PDT 24
Finished Jul 20 05:58:55 PM PDT 24
Peak memory 201604 kb
Host smart-67c179f6-4873-4b59-9c16-aae66d9d3bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92680486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.92680486
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.399355053
Short name T364
Test name
Test status
Simulation time 5609252719 ps
CPU time 6.99 seconds
Started Jul 20 05:58:35 PM PDT 24
Finished Jul 20 05:58:43 PM PDT 24
Peak memory 201580 kb
Host smart-cf6ed362-94ae-4990-b93a-d1268d307119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399355053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.399355053
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.198096565
Short name T128
Test name
Test status
Simulation time 334370555323 ps
CPU time 600.87 seconds
Started Jul 20 05:58:54 PM PDT 24
Finished Jul 20 06:08:55 PM PDT 24
Peak memory 201708 kb
Host smart-3e6d7b56-e1a3-45dc-a8ce-e9c0cda9d524
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198096565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
198096565
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2170265392
Short name T786
Test name
Test status
Simulation time 87437495259 ps
CPU time 155.19 seconds
Started Jul 20 05:58:52 PM PDT 24
Finished Jul 20 06:01:28 PM PDT 24
Peak memory 210060 kb
Host smart-30cb0b7d-9a92-4ccb-9778-81dcacfffc82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170265392 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.2170265392
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.418166397
Short name T597
Test name
Test status
Simulation time 429469665 ps
CPU time 1.6 seconds
Started Jul 20 05:59:07 PM PDT 24
Finished Jul 20 05:59:09 PM PDT 24
Peak memory 201540 kb
Host smart-36db4cb8-be07-4267-8e94-3874d6f5e14a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418166397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.418166397
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1620785859
Short name T168
Test name
Test status
Simulation time 329176433133 ps
CPU time 104.86 seconds
Started Jul 20 05:58:54 PM PDT 24
Finished Jul 20 06:00:39 PM PDT 24
Peak memory 201732 kb
Host smart-185022eb-5639-41ff-97d0-6798402761af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620785859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1620785859
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1877253897
Short name T127
Test name
Test status
Simulation time 331655197617 ps
CPU time 203.72 seconds
Started Jul 20 05:58:59 PM PDT 24
Finished Jul 20 06:02:23 PM PDT 24
Peak memory 201684 kb
Host smart-3b1437e1-30df-4ef7-84ab-c19823205019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877253897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1877253897
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.3280340921
Short name T185
Test name
Test status
Simulation time 492092194496 ps
CPU time 1101.07 seconds
Started Jul 20 05:58:59 PM PDT 24
Finished Jul 20 06:17:21 PM PDT 24
Peak memory 201688 kb
Host smart-534958f0-1d6c-4d86-bc04-6d1ae4d26f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280340921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3280340921
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2765933884
Short name T407
Test name
Test status
Simulation time 172932683749 ps
CPU time 112.8 seconds
Started Jul 20 05:58:54 PM PDT 24
Finished Jul 20 06:00:48 PM PDT 24
Peak memory 201716 kb
Host smart-e2a4ddf0-7118-44e3-8092-21f9d55da69e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765933884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2765933884
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1895643349
Short name T151
Test name
Test status
Simulation time 485321550801 ps
CPU time 1097.11 seconds
Started Jul 20 05:58:52 PM PDT 24
Finished Jul 20 06:17:09 PM PDT 24
Peak memory 201708 kb
Host smart-de110939-9b34-45bd-a78c-81b45acece6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895643349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1895643349
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.979619841
Short name T456
Test name
Test status
Simulation time 493310252918 ps
CPU time 1114.19 seconds
Started Jul 20 05:58:54 PM PDT 24
Finished Jul 20 06:17:29 PM PDT 24
Peak memory 201732 kb
Host smart-d790de46-fe81-4149-bc47-368275b087b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=979619841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.979619841
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.985098096
Short name T366
Test name
Test status
Simulation time 397541699544 ps
CPU time 440.11 seconds
Started Jul 20 05:58:52 PM PDT 24
Finished Jul 20 06:06:13 PM PDT 24
Peak memory 201712 kb
Host smart-df1fb34a-b3e9-40e6-a514-054386ff4fd8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985098096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.985098096
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3298028834
Short name T350
Test name
Test status
Simulation time 74971534009 ps
CPU time 276.76 seconds
Started Jul 20 05:58:58 PM PDT 24
Finished Jul 20 06:03:35 PM PDT 24
Peak memory 202128 kb
Host smart-acc3e95e-7234-48c9-b113-499a87d13c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298028834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3298028834
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2316630409
Short name T433
Test name
Test status
Simulation time 29277668101 ps
CPU time 62.92 seconds
Started Jul 20 05:58:58 PM PDT 24
Finished Jul 20 06:00:01 PM PDT 24
Peak memory 201592 kb
Host smart-cdb1aa96-9faf-4c1d-b21e-3bb3910ebb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316630409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2316630409
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3284185967
Short name T586
Test name
Test status
Simulation time 2748549485 ps
CPU time 3.71 seconds
Started Jul 20 05:58:53 PM PDT 24
Finished Jul 20 05:58:58 PM PDT 24
Peak memory 201596 kb
Host smart-d99ab96d-01db-41ea-aade-ce74d4c43a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284185967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3284185967
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.386556541
Short name T404
Test name
Test status
Simulation time 5933114982 ps
CPU time 14.21 seconds
Started Jul 20 05:58:54 PM PDT 24
Finished Jul 20 05:59:09 PM PDT 24
Peak memory 201600 kb
Host smart-5fce47b7-3ac7-4c1d-a824-67f6b10d381a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386556541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.386556541
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1301963243
Short name T35
Test name
Test status
Simulation time 202596867897 ps
CPU time 113.55 seconds
Started Jul 20 05:59:05 PM PDT 24
Finished Jul 20 06:00:59 PM PDT 24
Peak memory 201796 kb
Host smart-a950c8f0-de1e-4fa6-90be-c7d32096a5ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301963243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1301963243
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.4197979629
Short name T18
Test name
Test status
Simulation time 49898444503 ps
CPU time 211.09 seconds
Started Jul 20 05:58:59 PM PDT 24
Finished Jul 20 06:02:31 PM PDT 24
Peak memory 210364 kb
Host smart-cd5daade-3c4f-41db-b113-ce93a4a887e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197979629 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.4197979629
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1372407304
Short name T358
Test name
Test status
Simulation time 468239109 ps
CPU time 0.73 seconds
Started Jul 20 05:59:15 PM PDT 24
Finished Jul 20 05:59:16 PM PDT 24
Peak memory 201540 kb
Host smart-a4f78388-f372-4aaa-bc25-510c693edb74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372407304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1372407304
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1692547347
Short name T278
Test name
Test status
Simulation time 165417179527 ps
CPU time 191.55 seconds
Started Jul 20 05:59:07 PM PDT 24
Finished Jul 20 06:02:19 PM PDT 24
Peak memory 201664 kb
Host smart-8762855b-b8b5-441a-90cc-7535d40a40a1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692547347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1692547347
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1868177545
Short name T496
Test name
Test status
Simulation time 335091183677 ps
CPU time 818.06 seconds
Started Jul 20 05:59:04 PM PDT 24
Finished Jul 20 06:12:43 PM PDT 24
Peak memory 201740 kb
Host smart-6535924a-32ed-4e37-adfa-852743a5925a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868177545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1868177545
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.823740102
Short name T243
Test name
Test status
Simulation time 326138026404 ps
CPU time 385.61 seconds
Started Jul 20 05:59:07 PM PDT 24
Finished Jul 20 06:05:34 PM PDT 24
Peak memory 201740 kb
Host smart-a5c0e6ec-0188-41ed-af45-d1895493eb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823740102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.823740102
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1070142422
Short name T442
Test name
Test status
Simulation time 325811335541 ps
CPU time 388.2 seconds
Started Jul 20 05:59:08 PM PDT 24
Finished Jul 20 06:05:37 PM PDT 24
Peak memory 201720 kb
Host smart-36287ace-f829-4735-9626-ad186c3fb28e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070142422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1070142422
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2851636269
Short name T154
Test name
Test status
Simulation time 327462779831 ps
CPU time 729.74 seconds
Started Jul 20 05:59:07 PM PDT 24
Finished Jul 20 06:11:18 PM PDT 24
Peak memory 201640 kb
Host smart-44e80d2d-edb2-4ed4-89ba-71dfdcf0d9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851636269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2851636269
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.972074939
Short name T345
Test name
Test status
Simulation time 501966156745 ps
CPU time 1121.39 seconds
Started Jul 20 05:59:07 PM PDT 24
Finished Jul 20 06:17:48 PM PDT 24
Peak memory 201748 kb
Host smart-10b63daf-c744-4b97-a9fc-f7363e0c18a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=972074939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.972074939
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.368940138
Short name T237
Test name
Test status
Simulation time 569214305973 ps
CPU time 686.48 seconds
Started Jul 20 05:59:04 PM PDT 24
Finished Jul 20 06:10:31 PM PDT 24
Peak memory 201880 kb
Host smart-62a10d5c-2313-42e1-9e5e-3a3e9c5d25b3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368940138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.368940138
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1601270007
Short name T605
Test name
Test status
Simulation time 383623574154 ps
CPU time 837.06 seconds
Started Jul 20 05:59:05 PM PDT 24
Finished Jul 20 06:13:03 PM PDT 24
Peak memory 201732 kb
Host smart-05b6f7b4-abf1-4216-9374-3115e167cd7f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601270007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1601270007
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.410227575
Short name T417
Test name
Test status
Simulation time 130425357061 ps
CPU time 574.91 seconds
Started Jul 20 05:59:16 PM PDT 24
Finished Jul 20 06:08:51 PM PDT 24
Peak memory 202052 kb
Host smart-106ce934-a9f7-4529-97f1-414de0152229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410227575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.410227575
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1448490715
Short name T771
Test name
Test status
Simulation time 44402693642 ps
CPU time 49.28 seconds
Started Jul 20 05:59:06 PM PDT 24
Finished Jul 20 05:59:56 PM PDT 24
Peak memory 201604 kb
Host smart-217c8b84-f8cf-4027-ab26-89b6e7cff74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448490715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1448490715
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2965347775
Short name T387
Test name
Test status
Simulation time 5629754973 ps
CPU time 12.89 seconds
Started Jul 20 05:59:07 PM PDT 24
Finished Jul 20 05:59:21 PM PDT 24
Peak memory 201576 kb
Host smart-ddcf82e0-6d29-4fa6-a870-2767f1e4305a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965347775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2965347775
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.4232084615
Short name T181
Test name
Test status
Simulation time 5831978537 ps
CPU time 4.84 seconds
Started Jul 20 05:59:05 PM PDT 24
Finished Jul 20 05:59:10 PM PDT 24
Peak memory 201620 kb
Host smart-da711206-1c52-4d2e-adb3-7925c5bb0a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232084615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.4232084615
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2177627646
Short name T233
Test name
Test status
Simulation time 566748064052 ps
CPU time 511.88 seconds
Started Jul 20 05:59:16 PM PDT 24
Finished Jul 20 06:07:48 PM PDT 24
Peak memory 212744 kb
Host smart-62ce1dd9-6190-4ea6-8e2c-f9b1ecfccafa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177627646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2177627646
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2608335429
Short name T604
Test name
Test status
Simulation time 17660153838 ps
CPU time 43.01 seconds
Started Jul 20 05:59:11 PM PDT 24
Finished Jul 20 05:59:55 PM PDT 24
Peak memory 210296 kb
Host smart-f75e81ea-977d-4f60-be85-180c9fde3adb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608335429 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2608335429
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.4135449515
Short name T651
Test name
Test status
Simulation time 461939048 ps
CPU time 1.64 seconds
Started Jul 20 05:59:12 PM PDT 24
Finished Jul 20 05:59:14 PM PDT 24
Peak memory 201540 kb
Host smart-a19c046d-4ed7-48c1-96a3-42226fe0f855
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135449515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.4135449515
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3847736151
Short name T51
Test name
Test status
Simulation time 357706846215 ps
CPU time 222.8 seconds
Started Jul 20 05:59:22 PM PDT 24
Finished Jul 20 06:03:05 PM PDT 24
Peak memory 201792 kb
Host smart-9fe9a4a9-cd50-4369-a448-e068d869e473
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847736151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3847736151
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2038839568
Short name T619
Test name
Test status
Simulation time 326369514089 ps
CPU time 216.12 seconds
Started Jul 20 05:59:16 PM PDT 24
Finished Jul 20 06:02:52 PM PDT 24
Peak memory 201680 kb
Host smart-770457af-949c-43d2-ad78-1d0fd090677e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038839568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2038839568
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1958159554
Short name T489
Test name
Test status
Simulation time 165022309563 ps
CPU time 387.23 seconds
Started Jul 20 05:59:14 PM PDT 24
Finished Jul 20 06:05:42 PM PDT 24
Peak memory 201740 kb
Host smart-c333fb9e-1e38-44c3-9d5c-f185a405398b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958159554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.1958159554
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.638289383
Short name T628
Test name
Test status
Simulation time 167082752092 ps
CPU time 191.86 seconds
Started Jul 20 05:59:16 PM PDT 24
Finished Jul 20 06:02:28 PM PDT 24
Peak memory 201748 kb
Host smart-19a11e3f-95f4-4919-a36a-342b79144a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638289383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.638289383
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2116708908
Short name T661
Test name
Test status
Simulation time 496209206930 ps
CPU time 687 seconds
Started Jul 20 05:59:15 PM PDT 24
Finished Jul 20 06:10:42 PM PDT 24
Peak memory 201680 kb
Host smart-d19a5e43-a6b5-4663-b63d-a77ecb63e1e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116708908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2116708908
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3781538872
Short name T178
Test name
Test status
Simulation time 650639520648 ps
CPU time 253.73 seconds
Started Jul 20 05:59:22 PM PDT 24
Finished Jul 20 06:03:36 PM PDT 24
Peak memory 201808 kb
Host smart-9fd246cd-421e-42fb-9278-3b97d53ca703
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781538872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3781538872
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2185466548
Short name T647
Test name
Test status
Simulation time 610075837590 ps
CPU time 960.17 seconds
Started Jul 20 05:59:14 PM PDT 24
Finished Jul 20 06:15:15 PM PDT 24
Peak memory 201732 kb
Host smart-f0c252fc-6299-4057-b451-f3c3b87f8840
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185466548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2185466548
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.107914013
Short name T564
Test name
Test status
Simulation time 45990635984 ps
CPU time 112.73 seconds
Started Jul 20 05:59:15 PM PDT 24
Finished Jul 20 06:01:08 PM PDT 24
Peak memory 201596 kb
Host smart-55eaca11-e9eb-45c2-a220-f24924e640f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107914013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.107914013
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2125619382
Short name T453
Test name
Test status
Simulation time 5230782954 ps
CPU time 12.9 seconds
Started Jul 20 05:59:22 PM PDT 24
Finished Jul 20 05:59:35 PM PDT 24
Peak memory 201588 kb
Host smart-7efdeac6-dbc0-4c7c-995f-a3ebb49716bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125619382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2125619382
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.814743333
Short name T544
Test name
Test status
Simulation time 5839255099 ps
CPU time 14.24 seconds
Started Jul 20 05:59:14 PM PDT 24
Finished Jul 20 05:59:28 PM PDT 24
Peak memory 201596 kb
Host smart-287fd1e5-95e6-4a36-8980-29edfe2eb906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814743333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.814743333
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2122522628
Short name T231
Test name
Test status
Simulation time 355988168512 ps
CPU time 577.52 seconds
Started Jul 20 05:59:14 PM PDT 24
Finished Jul 20 06:08:52 PM PDT 24
Peak memory 201760 kb
Host smart-14f88bd7-549e-4a85-af2d-9ec63f559487
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122522628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2122522628
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.147196586
Short name T685
Test name
Test status
Simulation time 354104962 ps
CPU time 0.78 seconds
Started Jul 20 05:59:31 PM PDT 24
Finished Jul 20 05:59:32 PM PDT 24
Peak memory 201540 kb
Host smart-15d83342-2a94-4ae8-84f9-98c6a760026d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147196586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.147196586
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3426734067
Short name T613
Test name
Test status
Simulation time 354794106614 ps
CPU time 877.11 seconds
Started Jul 20 05:59:19 PM PDT 24
Finished Jul 20 06:13:57 PM PDT 24
Peak memory 201804 kb
Host smart-1aae2ae4-b118-4ec9-82a7-2fecc7c43903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426734067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3426734067
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.785398286
Short name T460
Test name
Test status
Simulation time 161536117912 ps
CPU time 47.34 seconds
Started Jul 20 05:59:21 PM PDT 24
Finished Jul 20 06:00:08 PM PDT 24
Peak memory 201884 kb
Host smart-8497c056-f4b5-4d75-b86c-273ad550305b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785398286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.785398286
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2545505010
Short name T728
Test name
Test status
Simulation time 498719464412 ps
CPU time 286.67 seconds
Started Jul 20 05:59:21 PM PDT 24
Finished Jul 20 06:04:08 PM PDT 24
Peak memory 201688 kb
Host smart-bd9e044e-794a-490e-a2d1-d030f5fab2e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545505010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2545505010
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3429627549
Short name T227
Test name
Test status
Simulation time 497018094295 ps
CPU time 236.8 seconds
Started Jul 20 05:59:23 PM PDT 24
Finished Jul 20 06:03:20 PM PDT 24
Peak memory 201728 kb
Host smart-0dc891ca-df5a-4bb1-9fa3-b3d266cc49cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429627549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3429627549
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1475524013
Short name T408
Test name
Test status
Simulation time 484498303190 ps
CPU time 1184.86 seconds
Started Jul 20 05:59:13 PM PDT 24
Finished Jul 20 06:18:58 PM PDT 24
Peak memory 201776 kb
Host smart-ce4c5dba-8854-4a14-a648-d926fd0b9ca4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475524013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1475524013
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3453112580
Short name T594
Test name
Test status
Simulation time 197370674694 ps
CPU time 464.29 seconds
Started Jul 20 05:59:22 PM PDT 24
Finished Jul 20 06:07:07 PM PDT 24
Peak memory 201684 kb
Host smart-fc8c1b98-f9d7-4eb4-b2a4-d2bbec5bc2eb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453112580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3453112580
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2092858461
Short name T194
Test name
Test status
Simulation time 109960187681 ps
CPU time 542.39 seconds
Started Jul 20 05:59:22 PM PDT 24
Finished Jul 20 06:08:25 PM PDT 24
Peak memory 202096 kb
Host smart-7587c160-b018-425c-8b61-db6fa96c748a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092858461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2092858461
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.635378341
Short name T621
Test name
Test status
Simulation time 31872924785 ps
CPU time 65.45 seconds
Started Jul 20 05:59:23 PM PDT 24
Finished Jul 20 06:00:29 PM PDT 24
Peak memory 201604 kb
Host smart-bc7bd36f-04da-415c-b812-4561da7ab031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635378341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.635378341
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1087279643
Short name T76
Test name
Test status
Simulation time 5457744888 ps
CPU time 12.93 seconds
Started Jul 20 05:59:19 PM PDT 24
Finished Jul 20 05:59:33 PM PDT 24
Peak memory 201600 kb
Host smart-9606c66e-1068-42c4-8dc2-d2e988d2dcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087279643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1087279643
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.340166095
Short name T745
Test name
Test status
Simulation time 5822921535 ps
CPU time 4.28 seconds
Started Jul 20 05:59:12 PM PDT 24
Finished Jul 20 05:59:17 PM PDT 24
Peak memory 201600 kb
Host smart-b8a5b746-1fc7-4868-b9e1-ae1b339133af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340166095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.340166095
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2307771387
Short name T538
Test name
Test status
Simulation time 62967953531 ps
CPU time 26.95 seconds
Started Jul 20 05:59:24 PM PDT 24
Finished Jul 20 05:59:51 PM PDT 24
Peak memory 210104 kb
Host smart-b1a9cf69-c52a-4c7e-ae91-cb76ce0f7163
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307771387 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2307771387
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3071915217
Short name T584
Test name
Test status
Simulation time 448297073 ps
CPU time 0.89 seconds
Started Jul 20 05:59:40 PM PDT 24
Finished Jul 20 05:59:41 PM PDT 24
Peak memory 201532 kb
Host smart-3764c0f6-687a-4c8e-bb80-b67c87e89b28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071915217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3071915217
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.958101097
Short name T264
Test name
Test status
Simulation time 170519981614 ps
CPU time 114.55 seconds
Started Jul 20 05:59:41 PM PDT 24
Finished Jul 20 06:01:36 PM PDT 24
Peak memory 201744 kb
Host smart-c463922a-ae9a-4890-b189-6024a4364505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958101097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.958101097
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3271364724
Short name T229
Test name
Test status
Simulation time 488333236418 ps
CPU time 1231.52 seconds
Started Jul 20 05:59:37 PM PDT 24
Finished Jul 20 06:20:09 PM PDT 24
Peak memory 201800 kb
Host smart-f9d8c7b1-5e71-421b-a087-12d8fd9f108c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271364724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3271364724
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1843726351
Short name T419
Test name
Test status
Simulation time 327800861957 ps
CPU time 65.1 seconds
Started Jul 20 05:59:40 PM PDT 24
Finished Jul 20 06:00:46 PM PDT 24
Peak memory 201724 kb
Host smart-9511aed6-1aea-4f56-bae3-5c1d6b153e29
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843726351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1843726351
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.2209138235
Short name T170
Test name
Test status
Simulation time 494947532401 ps
CPU time 1114.32 seconds
Started Jul 20 05:59:31 PM PDT 24
Finished Jul 20 06:18:05 PM PDT 24
Peak memory 201744 kb
Host smart-5a48b977-f3bb-41c7-b828-c8b8a9a9d80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209138235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2209138235
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1842751532
Short name T757
Test name
Test status
Simulation time 164361292807 ps
CPU time 415.46 seconds
Started Jul 20 05:59:31 PM PDT 24
Finished Jul 20 06:06:27 PM PDT 24
Peak memory 201716 kb
Host smart-26661247-3ac7-4517-a899-6fecce7adf88
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842751532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1842751532
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2456490059
Short name T221
Test name
Test status
Simulation time 354662604332 ps
CPU time 866.8 seconds
Started Jul 20 05:59:38 PM PDT 24
Finished Jul 20 06:14:06 PM PDT 24
Peak memory 201784 kb
Host smart-349711c2-20c4-4314-a1c4-51a22b9e0385
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456490059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.2456490059
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2779363729
Short name T696
Test name
Test status
Simulation time 398001131066 ps
CPU time 246.62 seconds
Started Jul 20 05:59:40 PM PDT 24
Finished Jul 20 06:03:48 PM PDT 24
Peak memory 201664 kb
Host smart-053aa9d6-bfcf-4b5a-ba3d-993d77766c62
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779363729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2779363729
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.692405635
Short name T711
Test name
Test status
Simulation time 76070308029 ps
CPU time 328.96 seconds
Started Jul 20 05:59:40 PM PDT 24
Finished Jul 20 06:05:10 PM PDT 24
Peak memory 202124 kb
Host smart-c92a9582-7b56-4a0e-8f9c-90db3c06380b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692405635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.692405635
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.224324751
Short name T508
Test name
Test status
Simulation time 30846726245 ps
CPU time 69.02 seconds
Started Jul 20 05:59:37 PM PDT 24
Finished Jul 20 06:00:47 PM PDT 24
Peak memory 201596 kb
Host smart-1a52a284-e281-4403-bba3-9d6f295194e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224324751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.224324751
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.493958506
Short name T427
Test name
Test status
Simulation time 5127598763 ps
CPU time 11.42 seconds
Started Jul 20 05:59:40 PM PDT 24
Finished Jul 20 05:59:53 PM PDT 24
Peak memory 201604 kb
Host smart-b5dd1c11-c80f-4514-adb9-0326ccecb6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493958506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.493958506
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1852252551
Short name T727
Test name
Test status
Simulation time 5994492167 ps
CPU time 3.79 seconds
Started Jul 20 05:59:31 PM PDT 24
Finished Jul 20 05:59:36 PM PDT 24
Peak memory 201596 kb
Host smart-bbaef23e-47b5-4658-aa68-dcc55226bf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852252551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1852252551
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.562796690
Short name T556
Test name
Test status
Simulation time 32468917998 ps
CPU time 48.65 seconds
Started Jul 20 05:59:40 PM PDT 24
Finished Jul 20 06:00:29 PM PDT 24
Peak memory 210488 kb
Host smart-09ffc290-8da8-419f-89d7-315814b29aa7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562796690 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.562796690
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3004605670
Short name T497
Test name
Test status
Simulation time 351885831 ps
CPU time 0.84 seconds
Started Jul 20 05:59:53 PM PDT 24
Finished Jul 20 05:59:54 PM PDT 24
Peak memory 201452 kb
Host smart-30aec13d-2b2c-41e4-9da1-57cc92048661
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004605670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3004605670
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2176101315
Short name T186
Test name
Test status
Simulation time 601917849843 ps
CPU time 324.41 seconds
Started Jul 20 05:59:55 PM PDT 24
Finished Jul 20 06:05:21 PM PDT 24
Peak memory 201752 kb
Host smart-7d55f641-0385-494f-8ef0-c920b4593d39
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176101315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2176101315
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.4146408842
Short name T470
Test name
Test status
Simulation time 329227361178 ps
CPU time 208.29 seconds
Started Jul 20 05:59:56 PM PDT 24
Finished Jul 20 06:03:25 PM PDT 24
Peak memory 201696 kb
Host smart-01a2c957-6521-40e9-9f82-6d1e94e63ecb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146408842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.4146408842
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2056547893
Short name T599
Test name
Test status
Simulation time 169156838137 ps
CPU time 399.46 seconds
Started Jul 20 05:59:56 PM PDT 24
Finished Jul 20 06:06:36 PM PDT 24
Peak memory 201808 kb
Host smart-04732858-85a2-4c0e-babc-006a5c9dc1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056547893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2056547893
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.3265847427
Short name T480
Test name
Test status
Simulation time 494870357547 ps
CPU time 316.74 seconds
Started Jul 20 05:59:56 PM PDT 24
Finished Jul 20 06:05:13 PM PDT 24
Peak memory 201712 kb
Host smart-cb3e5d58-1ba7-4f93-b227-25c8309374c6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265847427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.3265847427
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3390138971
Short name T449
Test name
Test status
Simulation time 386311009297 ps
CPU time 806.94 seconds
Started Jul 20 05:59:55 PM PDT 24
Finished Jul 20 06:13:23 PM PDT 24
Peak memory 201716 kb
Host smart-49afb3d1-02ff-4aa9-9dd6-f08e5923710d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390138971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3390138971
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.614037981
Short name T583
Test name
Test status
Simulation time 124082834465 ps
CPU time 380.78 seconds
Started Jul 20 05:59:55 PM PDT 24
Finished Jul 20 06:06:17 PM PDT 24
Peak memory 202176 kb
Host smart-f9b15dac-02b5-4d6c-910d-d2086b35ab55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614037981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.614037981
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1113877578
Short name T498
Test name
Test status
Simulation time 33654097847 ps
CPU time 41.09 seconds
Started Jul 20 05:59:54 PM PDT 24
Finished Jul 20 06:00:35 PM PDT 24
Peak memory 201592 kb
Host smart-167c3a8a-d968-4262-b5f6-4f2a1980d6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113877578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1113877578
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2054449712
Short name T452
Test name
Test status
Simulation time 4693344274 ps
CPU time 5.64 seconds
Started Jul 20 05:59:55 PM PDT 24
Finished Jul 20 06:00:02 PM PDT 24
Peak memory 201612 kb
Host smart-921b7d5b-506b-45ec-9263-e7823162aac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054449712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2054449712
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2492320759
Short name T630
Test name
Test status
Simulation time 6071041684 ps
CPU time 4.13 seconds
Started Jul 20 05:59:55 PM PDT 24
Finished Jul 20 06:00:00 PM PDT 24
Peak memory 201552 kb
Host smart-f6b06e60-e1e7-4456-8397-beb1011b8973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492320759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2492320759
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.859647910
Short name T707
Test name
Test status
Simulation time 165000876455 ps
CPU time 96.25 seconds
Started Jul 20 05:59:54 PM PDT 24
Finished Jul 20 06:01:31 PM PDT 24
Peak memory 201800 kb
Host smart-5e02b4ad-c014-4215-a419-0a8235174b5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859647910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
859647910
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1131338939
Short name T472
Test name
Test status
Simulation time 81000992327 ps
CPU time 144.04 seconds
Started Jul 20 05:59:55 PM PDT 24
Finished Jul 20 06:02:20 PM PDT 24
Peak memory 210412 kb
Host smart-5698bdde-20dc-4cf8-87ea-366667352de4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131338939 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1131338939
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1721308780
Short name T515
Test name
Test status
Simulation time 389203531 ps
CPU time 1.49 seconds
Started Jul 20 05:56:35 PM PDT 24
Finished Jul 20 05:56:40 PM PDT 24
Peak memory 201572 kb
Host smart-a1411073-7710-4632-ac8f-a5b30d404a81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721308780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1721308780
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1837497065
Short name T328
Test name
Test status
Simulation time 521659758197 ps
CPU time 1201.73 seconds
Started Jul 20 05:56:30 PM PDT 24
Finished Jul 20 06:16:35 PM PDT 24
Peak memory 201792 kb
Host smart-28ec42b5-b20a-4ce3-a718-1d941dad87e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837497065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1837497065
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.2469537990
Short name T172
Test name
Test status
Simulation time 163039596225 ps
CPU time 376.2 seconds
Started Jul 20 05:56:37 PM PDT 24
Finished Jul 20 06:02:55 PM PDT 24
Peak memory 201696 kb
Host smart-4cdfe7d7-05ae-4138-b245-c0845ac04464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469537990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2469537990
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2431962657
Short name T74
Test name
Test status
Simulation time 495592666353 ps
CPU time 1042.36 seconds
Started Jul 20 05:56:31 PM PDT 24
Finished Jul 20 06:13:56 PM PDT 24
Peak memory 201776 kb
Host smart-0619d9f5-d269-4cc2-a6b0-11739badad01
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431962657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2431962657
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.805076445
Short name T629
Test name
Test status
Simulation time 166203835688 ps
CPU time 202.08 seconds
Started Jul 20 05:56:40 PM PDT 24
Finished Jul 20 06:00:03 PM PDT 24
Peak memory 201816 kb
Host smart-bf7aabb7-6453-49d6-ab0c-7119638a3b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805076445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.805076445
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1509743763
Short name T734
Test name
Test status
Simulation time 324954365017 ps
CPU time 180.26 seconds
Started Jul 20 05:56:43 PM PDT 24
Finished Jul 20 05:59:44 PM PDT 24
Peak memory 201732 kb
Host smart-7d064a79-984e-4354-8908-76b29d7f0cd3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509743763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1509743763
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3471945438
Short name T469
Test name
Test status
Simulation time 192869493332 ps
CPU time 403.89 seconds
Started Jul 20 05:56:40 PM PDT 24
Finished Jul 20 06:03:25 PM PDT 24
Peak memory 201804 kb
Host smart-b9c41c6f-0062-4d33-a1f7-d3069b88b95c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471945438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3471945438
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2608138422
Short name T659
Test name
Test status
Simulation time 194248508831 ps
CPU time 204.64 seconds
Started Jul 20 05:56:40 PM PDT 24
Finished Jul 20 06:00:06 PM PDT 24
Peak memory 201800 kb
Host smart-e3f8f993-cc30-4738-88b6-fe1eb5f9bf19
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608138422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2608138422
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.124443684
Short name T519
Test name
Test status
Simulation time 94324490445 ps
CPU time 359.11 seconds
Started Jul 20 05:56:32 PM PDT 24
Finished Jul 20 06:02:34 PM PDT 24
Peak memory 202004 kb
Host smart-1add7cd2-6a33-4cf1-accb-e7b027f1803b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124443684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.124443684
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1176965628
Short name T774
Test name
Test status
Simulation time 32862068829 ps
CPU time 11.91 seconds
Started Jul 20 05:56:33 PM PDT 24
Finished Jul 20 05:56:48 PM PDT 24
Peak memory 201604 kb
Host smart-138c3d98-7d6c-41fa-82ac-dfcdff14a92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176965628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1176965628
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.2327747735
Short name T384
Test name
Test status
Simulation time 4603429387 ps
CPU time 2.11 seconds
Started Jul 20 05:56:35 PM PDT 24
Finished Jul 20 05:56:40 PM PDT 24
Peak memory 201508 kb
Host smart-52f49558-0e92-45f6-ad43-0dedc5320fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327747735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2327747735
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2962777087
Short name T61
Test name
Test status
Simulation time 4238326445 ps
CPU time 10.21 seconds
Started Jul 20 05:56:32 PM PDT 24
Finished Jul 20 05:56:45 PM PDT 24
Peak memory 217156 kb
Host smart-009bcd33-177a-4f6a-823d-a49741ee54bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962777087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2962777087
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3684633897
Short name T373
Test name
Test status
Simulation time 5628205476 ps
CPU time 12.65 seconds
Started Jul 20 05:56:33 PM PDT 24
Finished Jul 20 05:56:49 PM PDT 24
Peak memory 201616 kb
Host smart-27aeea9d-3eeb-4153-932b-a5645f15312e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684633897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3684633897
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3022841164
Short name T287
Test name
Test status
Simulation time 533936293200 ps
CPU time 137.24 seconds
Started Jul 20 05:56:39 PM PDT 24
Finished Jul 20 05:58:57 PM PDT 24
Peak memory 201716 kb
Host smart-54f30b62-46fc-4a04-8fb8-0e7a4fa1f284
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022841164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3022841164
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1986359872
Short name T263
Test name
Test status
Simulation time 75630984349 ps
CPU time 250.94 seconds
Started Jul 20 05:56:30 PM PDT 24
Finished Jul 20 06:00:43 PM PDT 24
Peak memory 217844 kb
Host smart-a1323f78-0faa-46cc-9a18-1327ede54308
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986359872 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1986359872
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.309099762
Short name T795
Test name
Test status
Simulation time 360633442 ps
CPU time 1.44 seconds
Started Jul 20 06:00:05 PM PDT 24
Finished Jul 20 06:00:07 PM PDT 24
Peak memory 201540 kb
Host smart-ee51e586-1515-44e4-9c6d-da9acd69a2ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309099762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.309099762
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.382734212
Short name T790
Test name
Test status
Simulation time 324287828848 ps
CPU time 692.93 seconds
Started Jul 20 05:59:55 PM PDT 24
Finished Jul 20 06:11:29 PM PDT 24
Peak memory 201772 kb
Host smart-9626502c-6caf-419a-b910-d1e6cddc25f4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382734212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.382734212
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3974521520
Short name T302
Test name
Test status
Simulation time 495707062752 ps
CPU time 506.7 seconds
Started Jul 20 05:59:54 PM PDT 24
Finished Jul 20 06:08:21 PM PDT 24
Peak memory 201740 kb
Host smart-751de819-e153-4035-95aa-6e93f1c43511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974521520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3974521520
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3900721772
Short name T681
Test name
Test status
Simulation time 165160357752 ps
CPU time 105.4 seconds
Started Jul 20 05:59:58 PM PDT 24
Finished Jul 20 06:01:44 PM PDT 24
Peak memory 201720 kb
Host smart-b6137a5d-47a9-43fc-84df-fa6eac4c7100
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900721772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3900721772
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.4117460348
Short name T739
Test name
Test status
Simulation time 483028948012 ps
CPU time 269.1 seconds
Started Jul 20 05:59:59 PM PDT 24
Finished Jul 20 06:04:29 PM PDT 24
Peak memory 201752 kb
Host smart-1eced6d8-8ae4-4482-abb7-cf4809903faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117460348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.4117460348
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2517977920
Short name T369
Test name
Test status
Simulation time 489805995123 ps
CPU time 562.38 seconds
Started Jul 20 06:00:00 PM PDT 24
Finished Jul 20 06:09:23 PM PDT 24
Peak memory 201712 kb
Host smart-7cbd31dc-a601-4e4c-b709-f863afc97ea4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517977920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2517977920
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3941062586
Short name T754
Test name
Test status
Simulation time 205018443329 ps
CPU time 400.86 seconds
Started Jul 20 05:59:55 PM PDT 24
Finished Jul 20 06:06:37 PM PDT 24
Peak memory 201784 kb
Host smart-20138b96-5ee6-42b9-ba10-93432918ba54
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941062586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3941062586
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2704124207
Short name T477
Test name
Test status
Simulation time 121223376756 ps
CPU time 572.53 seconds
Started Jul 20 05:59:57 PM PDT 24
Finished Jul 20 06:09:30 PM PDT 24
Peak memory 202116 kb
Host smart-468928ed-d704-4210-a53e-99596fbe8fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704124207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2704124207
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.4080251841
Short name T542
Test name
Test status
Simulation time 32355565601 ps
CPU time 78.8 seconds
Started Jul 20 05:59:55 PM PDT 24
Finished Jul 20 06:01:15 PM PDT 24
Peak memory 201608 kb
Host smart-8101054d-f4ba-4dc5-9eb2-5314613f43e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080251841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.4080251841
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3455872161
Short name T371
Test name
Test status
Simulation time 3630814425 ps
CPU time 5.24 seconds
Started Jul 20 05:59:58 PM PDT 24
Finished Jul 20 06:00:04 PM PDT 24
Peak memory 201600 kb
Host smart-bb50cc1f-98f2-4485-a2cd-318b3329df4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455872161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3455872161
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.929717635
Short name T179
Test name
Test status
Simulation time 6028717334 ps
CPU time 3.39 seconds
Started Jul 20 05:59:55 PM PDT 24
Finished Jul 20 06:00:00 PM PDT 24
Peak memory 201608 kb
Host smart-7cd0f121-69c8-49a2-8d83-1d64e43fb05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929717635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.929717635
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1064544107
Short name T190
Test name
Test status
Simulation time 211477371834 ps
CPU time 114.14 seconds
Started Jul 20 06:00:06 PM PDT 24
Finished Jul 20 06:02:00 PM PDT 24
Peak memory 201736 kb
Host smart-b3ce2187-4b37-47aa-951d-5b870dc04ed4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064544107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1064544107
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3111479816
Short name T432
Test name
Test status
Simulation time 45722830199 ps
CPU time 83.39 seconds
Started Jul 20 05:59:59 PM PDT 24
Finished Jul 20 06:01:23 PM PDT 24
Peak memory 210448 kb
Host smart-dc0352ed-8dc6-4734-918f-76aadaccd4d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111479816 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3111479816
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1278556738
Short name T457
Test name
Test status
Simulation time 422302464 ps
CPU time 1.1 seconds
Started Jul 20 06:00:14 PM PDT 24
Finished Jul 20 06:00:15 PM PDT 24
Peak memory 201548 kb
Host smart-7b21e151-1893-48a6-96bb-51cd20a23a4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278556738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1278556738
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1336338315
Short name T618
Test name
Test status
Simulation time 545353319368 ps
CPU time 646.59 seconds
Started Jul 20 06:00:14 PM PDT 24
Finished Jul 20 06:11:01 PM PDT 24
Peak memory 201688 kb
Host smart-33f936a7-cb55-4d5a-8108-5b1da411becd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336338315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1336338315
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.132859153
Short name T309
Test name
Test status
Simulation time 489543349902 ps
CPU time 1067.77 seconds
Started Jul 20 06:00:06 PM PDT 24
Finished Jul 20 06:17:54 PM PDT 24
Peak memory 201804 kb
Host smart-78a724d4-92e1-4284-bee5-023dcf296859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132859153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.132859153
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.341252217
Short name T573
Test name
Test status
Simulation time 320729232679 ps
CPU time 182.14 seconds
Started Jul 20 06:00:06 PM PDT 24
Finished Jul 20 06:03:09 PM PDT 24
Peak memory 201856 kb
Host smart-60675531-8ebc-4e88-91d0-d560cc28639b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=341252217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrup
t_fixed.341252217
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2899032444
Short name T175
Test name
Test status
Simulation time 491357523589 ps
CPU time 526.79 seconds
Started Jul 20 06:00:03 PM PDT 24
Finished Jul 20 06:08:50 PM PDT 24
Peak memory 201804 kb
Host smart-1559e6a1-ec95-42b4-8708-73043c7184fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899032444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2899032444
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.657508239
Short name T636
Test name
Test status
Simulation time 489743264425 ps
CPU time 1160.95 seconds
Started Jul 20 06:00:05 PM PDT 24
Finished Jul 20 06:19:26 PM PDT 24
Peak memory 201744 kb
Host smart-833196b2-ec34-40d4-b131-70c4db6656a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=657508239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixe
d.657508239
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2820376793
Short name T525
Test name
Test status
Simulation time 210815631537 ps
CPU time 131.85 seconds
Started Jul 20 06:00:12 PM PDT 24
Finished Jul 20 06:02:24 PM PDT 24
Peak memory 201740 kb
Host smart-7c011462-4d2c-433c-bfc6-2de264d7a584
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820376793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2820376793
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.516801739
Short name T753
Test name
Test status
Simulation time 394083480950 ps
CPU time 227.4 seconds
Started Jul 20 06:00:14 PM PDT 24
Finished Jul 20 06:04:01 PM PDT 24
Peak memory 201700 kb
Host smart-c4d0f727-a88f-41b1-97cf-da695dd62a16
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516801739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.516801739
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1485180472
Short name T41
Test name
Test status
Simulation time 108201527229 ps
CPU time 446.4 seconds
Started Jul 20 06:00:10 PM PDT 24
Finished Jul 20 06:07:37 PM PDT 24
Peak memory 202160 kb
Host smart-821d4367-b7e9-40da-8ac9-1afa79553997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485180472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1485180472
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2559996231
Short name T789
Test name
Test status
Simulation time 26764007963 ps
CPU time 55.73 seconds
Started Jul 20 06:00:14 PM PDT 24
Finished Jul 20 06:01:10 PM PDT 24
Peak memory 201556 kb
Host smart-807427c9-434e-4f74-a69f-b27a49e5df9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559996231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2559996231
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1510119800
Short name T688
Test name
Test status
Simulation time 3034856102 ps
CPU time 8.09 seconds
Started Jul 20 06:00:13 PM PDT 24
Finished Jul 20 06:00:22 PM PDT 24
Peak memory 201596 kb
Host smart-2c107408-29de-4e80-99ce-05909563339a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510119800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1510119800
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1683206436
Short name T351
Test name
Test status
Simulation time 5775761207 ps
CPU time 4.49 seconds
Started Jul 20 06:00:05 PM PDT 24
Finished Jul 20 06:00:10 PM PDT 24
Peak memory 201576 kb
Host smart-88847f54-7a82-4b4c-aefa-d58c8a449f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683206436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1683206436
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2126226247
Short name T684
Test name
Test status
Simulation time 28757405558 ps
CPU time 64.13 seconds
Started Jul 20 06:00:12 PM PDT 24
Finished Jul 20 06:01:16 PM PDT 24
Peak memory 201588 kb
Host smart-7a13eba8-1329-4e72-adfb-5408208f9740
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126226247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2126226247
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3060868992
Short name T782
Test name
Test status
Simulation time 45961025262 ps
CPU time 73.43 seconds
Started Jul 20 06:00:13 PM PDT 24
Finished Jul 20 06:01:27 PM PDT 24
Peak memory 210504 kb
Host smart-a395b4e3-334e-40dc-a829-1d8018464954
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060868992 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3060868992
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.101957987
Short name T512
Test name
Test status
Simulation time 414291668 ps
CPU time 1.42 seconds
Started Jul 20 06:00:33 PM PDT 24
Finished Jul 20 06:00:35 PM PDT 24
Peak memory 201560 kb
Host smart-23a3a566-8ada-4a97-8eb2-235df146da79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101957987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.101957987
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1109267984
Short name T756
Test name
Test status
Simulation time 160241615016 ps
CPU time 192.57 seconds
Started Jul 20 06:00:23 PM PDT 24
Finished Jul 20 06:03:35 PM PDT 24
Peak memory 201936 kb
Host smart-24205438-cd2c-4a8e-b3a0-4d49c29b955d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109267984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1109267984
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1372373144
Short name T80
Test name
Test status
Simulation time 318947605972 ps
CPU time 177.85 seconds
Started Jul 20 06:00:19 PM PDT 24
Finished Jul 20 06:03:18 PM PDT 24
Peak memory 201724 kb
Host smart-6e5d75e2-314c-495f-a4f6-66b5eb49315b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372373144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1372373144
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3197557097
Short name T213
Test name
Test status
Simulation time 163082584297 ps
CPU time 351.82 seconds
Started Jul 20 06:00:19 PM PDT 24
Finished Jul 20 06:06:11 PM PDT 24
Peak memory 201912 kb
Host smart-1e892775-75bc-4a5e-a49b-8b6277e272c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197557097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3197557097
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3663944787
Short name T694
Test name
Test status
Simulation time 328304156234 ps
CPU time 711.47 seconds
Started Jul 20 06:00:21 PM PDT 24
Finished Jul 20 06:12:13 PM PDT 24
Peak memory 201728 kb
Host smart-553ae567-8c13-4aca-85bc-873dc70061d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663944787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3663944787
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.2538030078
Short name T273
Test name
Test status
Simulation time 452036055894 ps
CPU time 518.97 seconds
Started Jul 20 06:00:23 PM PDT 24
Finished Jul 20 06:09:02 PM PDT 24
Peak memory 201860 kb
Host smart-39d01dd3-1fe1-4b89-8f52-d6ae63d73c1a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538030078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.2538030078
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3247894891
Short name T683
Test name
Test status
Simulation time 392771711216 ps
CPU time 940.17 seconds
Started Jul 20 06:00:34 PM PDT 24
Finished Jul 20 06:16:15 PM PDT 24
Peak memory 201724 kb
Host smart-cc4d5f52-d1ac-4131-80d0-072d27f68c4d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247894891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3247894891
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1109298331
Short name T582
Test name
Test status
Simulation time 45265982706 ps
CPU time 23.93 seconds
Started Jul 20 06:00:34 PM PDT 24
Finished Jul 20 06:00:59 PM PDT 24
Peak memory 201616 kb
Host smart-7e74a40d-e94b-4ecb-8961-19bed16e4835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109298331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1109298331
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3795132155
Short name T576
Test name
Test status
Simulation time 4649302940 ps
CPU time 6.43 seconds
Started Jul 20 06:00:34 PM PDT 24
Finished Jul 20 06:00:41 PM PDT 24
Peak memory 201576 kb
Host smart-89bef510-66be-4909-9641-55f432d679e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795132155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3795132155
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1964192359
Short name T615
Test name
Test status
Simulation time 5782023563 ps
CPU time 4.49 seconds
Started Jul 20 06:00:13 PM PDT 24
Finished Jul 20 06:00:18 PM PDT 24
Peak memory 201600 kb
Host smart-f48a6adf-856d-4bc9-a313-21e40f395901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964192359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1964192359
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2605744288
Short name T723
Test name
Test status
Simulation time 482291498 ps
CPU time 0.98 seconds
Started Jul 20 06:00:49 PM PDT 24
Finished Jul 20 06:00:51 PM PDT 24
Peak memory 201540 kb
Host smart-fdce17d2-1942-45eb-8ce4-9adc10e7abf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605744288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2605744288
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2467271598
Short name T797
Test name
Test status
Simulation time 163027745672 ps
CPU time 413.16 seconds
Started Jul 20 06:00:41 PM PDT 24
Finished Jul 20 06:07:35 PM PDT 24
Peak memory 201804 kb
Host smart-84c1e9be-8a97-43ed-a305-d0400080abdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467271598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2467271598
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2824635451
Short name T667
Test name
Test status
Simulation time 161773726598 ps
CPU time 107.37 seconds
Started Jul 20 06:00:41 PM PDT 24
Finished Jul 20 06:02:29 PM PDT 24
Peak memory 201648 kb
Host smart-625be874-a67a-4051-97d8-0bd024e7a33b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824635451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2824635451
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1056095844
Short name T134
Test name
Test status
Simulation time 160989442884 ps
CPU time 98.58 seconds
Started Jul 20 06:00:41 PM PDT 24
Finished Jul 20 06:02:21 PM PDT 24
Peak memory 201724 kb
Host smart-1dfad0c0-190c-4d84-87ab-4b14bde09eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056095844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1056095844
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2094719539
Short name T176
Test name
Test status
Simulation time 330939554298 ps
CPU time 409.86 seconds
Started Jul 20 06:00:42 PM PDT 24
Finished Jul 20 06:07:32 PM PDT 24
Peak memory 201716 kb
Host smart-90e17829-463f-48a9-b97c-f0d1622105aa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094719539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2094719539
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1654203837
Short name T715
Test name
Test status
Simulation time 569248661663 ps
CPU time 340.44 seconds
Started Jul 20 06:00:41 PM PDT 24
Finished Jul 20 06:06:23 PM PDT 24
Peak memory 201668 kb
Host smart-39f38601-7d51-45b5-b4fb-49652d4e416f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654203837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1654203837
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2001595218
Short name T724
Test name
Test status
Simulation time 418655450686 ps
CPU time 467.32 seconds
Started Jul 20 06:00:39 PM PDT 24
Finished Jul 20 06:08:27 PM PDT 24
Peak memory 201664 kb
Host smart-dd5995cf-7e8f-450a-9d0b-c4ce856ec514
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001595218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2001595218
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.2470487411
Short name T733
Test name
Test status
Simulation time 47255677636 ps
CPU time 108.38 seconds
Started Jul 20 06:00:40 PM PDT 24
Finished Jul 20 06:02:30 PM PDT 24
Peak memory 201592 kb
Host smart-949a9ab2-651d-490f-b7f1-5871d0455aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470487411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2470487411
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.521436658
Short name T397
Test name
Test status
Simulation time 3606651019 ps
CPU time 3.43 seconds
Started Jul 20 06:00:41 PM PDT 24
Finished Jul 20 06:00:45 PM PDT 24
Peak memory 201612 kb
Host smart-6bb9ca7d-720e-4fea-ae5f-375c796c020e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521436658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.521436658
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2911508929
Short name T422
Test name
Test status
Simulation time 6252497744 ps
CPU time 8.08 seconds
Started Jul 20 06:00:33 PM PDT 24
Finished Jul 20 06:00:41 PM PDT 24
Peak memory 201596 kb
Host smart-5b566cca-d081-46bc-af56-50a00d854fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911508929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2911508929
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3352029578
Short name T326
Test name
Test status
Simulation time 573703477776 ps
CPU time 181.56 seconds
Started Jul 20 06:00:40 PM PDT 24
Finished Jul 20 06:03:42 PM PDT 24
Peak memory 201736 kb
Host smart-fecb3580-8a56-4b1f-a1ee-3b318e750788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352029578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3352029578
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2735085389
Short name T389
Test name
Test status
Simulation time 368951945 ps
CPU time 1.39 seconds
Started Jul 20 06:00:48 PM PDT 24
Finished Jul 20 06:00:50 PM PDT 24
Peak memory 201556 kb
Host smart-e5ed3f7a-b15d-4ee6-8463-297165075036
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735085389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2735085389
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.932881510
Short name T215
Test name
Test status
Simulation time 330485555706 ps
CPU time 209.4 seconds
Started Jul 20 06:00:52 PM PDT 24
Finished Jul 20 06:04:22 PM PDT 24
Peak memory 201696 kb
Host smart-5fbce6f6-b812-4ead-b6fd-142755c8e276
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932881510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.932881510
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1747750893
Short name T258
Test name
Test status
Simulation time 320779292246 ps
CPU time 715.57 seconds
Started Jul 20 06:00:50 PM PDT 24
Finished Jul 20 06:12:46 PM PDT 24
Peak memory 201720 kb
Host smart-076773e1-3c9c-4889-a069-ef29a902eb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747750893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1747750893
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2260013439
Short name T131
Test name
Test status
Simulation time 499531642430 ps
CPU time 601.98 seconds
Started Jul 20 06:00:49 PM PDT 24
Finished Jul 20 06:10:52 PM PDT 24
Peak memory 201736 kb
Host smart-6574ba78-9703-4f2d-ac67-b33833ede1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260013439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2260013439
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.275008158
Short name T682
Test name
Test status
Simulation time 327665573498 ps
CPU time 705.12 seconds
Started Jul 20 06:00:50 PM PDT 24
Finished Jul 20 06:12:35 PM PDT 24
Peak memory 201616 kb
Host smart-64c62718-f7e8-4ea1-8afa-b55a57fc853e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=275008158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.275008158
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.822139094
Short name T298
Test name
Test status
Simulation time 164576766182 ps
CPU time 44.21 seconds
Started Jul 20 06:00:50 PM PDT 24
Finished Jul 20 06:01:35 PM PDT 24
Peak memory 201812 kb
Host smart-ce72493b-4e49-4eb0-8e0d-ea4141b260c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822139094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.822139094
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3593836886
Short name T162
Test name
Test status
Simulation time 489616661245 ps
CPU time 230.22 seconds
Started Jul 20 06:00:50 PM PDT 24
Finished Jul 20 06:04:41 PM PDT 24
Peak memory 201752 kb
Host smart-d1a4cccb-ae4e-4e4b-8e0c-148f7a37d710
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593836886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3593836886
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1387274118
Short name T763
Test name
Test status
Simulation time 534101606582 ps
CPU time 630.04 seconds
Started Jul 20 06:00:48 PM PDT 24
Finished Jul 20 06:11:18 PM PDT 24
Peak memory 201844 kb
Host smart-c3049e08-d3c2-4a89-a672-547be0315d4e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387274118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1387274118
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2738625680
Short name T793
Test name
Test status
Simulation time 182880666529 ps
CPU time 41.5 seconds
Started Jul 20 06:00:53 PM PDT 24
Finished Jul 20 06:01:35 PM PDT 24
Peak memory 201776 kb
Host smart-63b70875-9e6e-47a7-9b16-94933cb7eb84
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738625680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2738625680
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2559957889
Short name T738
Test name
Test status
Simulation time 97205095911 ps
CPU time 312.38 seconds
Started Jul 20 06:00:48 PM PDT 24
Finished Jul 20 06:06:01 PM PDT 24
Peak memory 202172 kb
Host smart-be8c68ff-ba5f-44e8-9d61-5a4caa98c345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559957889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2559957889
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.4125129154
Short name T649
Test name
Test status
Simulation time 22851052553 ps
CPU time 5.99 seconds
Started Jul 20 06:00:51 PM PDT 24
Finished Jul 20 06:00:57 PM PDT 24
Peak memory 201604 kb
Host smart-dbd32814-5b5e-422d-ab55-a291bf72ba35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125129154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.4125129154
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.777146663
Short name T368
Test name
Test status
Simulation time 3213031317 ps
CPU time 8.61 seconds
Started Jul 20 06:00:50 PM PDT 24
Finished Jul 20 06:00:59 PM PDT 24
Peak memory 201604 kb
Host smart-4d04cce2-69ae-45f9-9bc0-d4f0931d2142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777146663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.777146663
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.40228290
Short name T443
Test name
Test status
Simulation time 5849875982 ps
CPU time 13.17 seconds
Started Jul 20 06:00:53 PM PDT 24
Finished Jul 20 06:01:07 PM PDT 24
Peak memory 201596 kb
Host smart-02257c69-9648-4e8d-822d-58c0abfcc345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40228290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.40228290
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.4013874366
Short name T282
Test name
Test status
Simulation time 546437124980 ps
CPU time 227.73 seconds
Started Jul 20 06:00:51 PM PDT 24
Finished Jul 20 06:04:39 PM PDT 24
Peak memory 201760 kb
Host smart-0da6de56-f6ce-4051-a660-243d412f5626
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013874366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.4013874366
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3137256919
Short name T291
Test name
Test status
Simulation time 73550886265 ps
CPU time 175.91 seconds
Started Jul 20 06:00:49 PM PDT 24
Finished Jul 20 06:03:46 PM PDT 24
Peak memory 218464 kb
Host smart-357a5ad6-3950-472f-bc7a-bdf37d8cfd59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137256919 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3137256919
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.860570423
Short name T557
Test name
Test status
Simulation time 302760198 ps
CPU time 0.92 seconds
Started Jul 20 06:01:10 PM PDT 24
Finished Jul 20 06:01:11 PM PDT 24
Peak memory 201544 kb
Host smart-f7f34a24-202a-40f1-bce6-0566230e374f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860570423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.860570423
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.3645406096
Short name T474
Test name
Test status
Simulation time 324381886527 ps
CPU time 756.83 seconds
Started Jul 20 06:00:57 PM PDT 24
Finished Jul 20 06:13:35 PM PDT 24
Peak memory 201752 kb
Host smart-b1787835-c8f2-4016-adaf-98bf1f3d5568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645406096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3645406096
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2036682591
Short name T616
Test name
Test status
Simulation time 498724238535 ps
CPU time 1126.96 seconds
Started Jul 20 06:01:06 PM PDT 24
Finished Jul 20 06:19:53 PM PDT 24
Peak memory 201800 kb
Host smart-7d1a4ebc-5f62-4f6f-8dc6-6964c768070f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036682591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2036682591
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.332729815
Short name T716
Test name
Test status
Simulation time 494992037219 ps
CPU time 285.09 seconds
Started Jul 20 06:01:00 PM PDT 24
Finished Jul 20 06:05:45 PM PDT 24
Peak memory 201716 kb
Host smart-da8cc2bf-8c19-44d9-aa72-164f100e0142
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=332729815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrup
t_fixed.332729815
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1093007846
Short name T423
Test name
Test status
Simulation time 169721031323 ps
CPU time 379.57 seconds
Started Jul 20 06:01:05 PM PDT 24
Finished Jul 20 06:07:25 PM PDT 24
Peak memory 201808 kb
Host smart-b827a419-d0b4-43ea-a351-0e308e8ad37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093007846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1093007846
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.3643232737
Short name T785
Test name
Test status
Simulation time 493695351423 ps
CPU time 156.39 seconds
Started Jul 20 06:00:57 PM PDT 24
Finished Jul 20 06:03:34 PM PDT 24
Peak memory 201716 kb
Host smart-cce10aeb-40bf-4c95-852e-4948522eee69
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643232737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.3643232737
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.3415901042
Short name T30
Test name
Test status
Simulation time 181910092690 ps
CPU time 429.83 seconds
Started Jul 20 06:00:59 PM PDT 24
Finished Jul 20 06:08:09 PM PDT 24
Peak memory 201748 kb
Host smart-04ed8175-acac-4f52-a327-b255afae1d31
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415901042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.3415901042
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2822148416
Short name T730
Test name
Test status
Simulation time 409357289428 ps
CPU time 250.46 seconds
Started Jul 20 06:00:59 PM PDT 24
Finished Jul 20 06:05:09 PM PDT 24
Peak memory 201792 kb
Host smart-97c3d966-6d9a-4b80-a562-9f1aa9a5829f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822148416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2822148416
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2250073904
Short name T340
Test name
Test status
Simulation time 133835731812 ps
CPU time 522.84 seconds
Started Jul 20 06:01:06 PM PDT 24
Finished Jul 20 06:09:49 PM PDT 24
Peak memory 202180 kb
Host smart-d0b6b7b2-bc58-40d8-848b-0323044319c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250073904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2250073904
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.148543026
Short name T781
Test name
Test status
Simulation time 41265150338 ps
CPU time 25.09 seconds
Started Jul 20 06:00:58 PM PDT 24
Finished Jul 20 06:01:23 PM PDT 24
Peak memory 201548 kb
Host smart-fc0877ac-7ba0-4dbd-b091-f66050d2aa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148543026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.148543026
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.199172478
Short name T664
Test name
Test status
Simulation time 3705556518 ps
CPU time 2.62 seconds
Started Jul 20 06:01:09 PM PDT 24
Finished Jul 20 06:01:12 PM PDT 24
Peak memory 201600 kb
Host smart-43be5d58-27e5-441c-b873-b1bebee7917b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199172478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.199172478
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.248168752
Short name T490
Test name
Test status
Simulation time 5712752356 ps
CPU time 15.08 seconds
Started Jul 20 06:00:59 PM PDT 24
Finished Jul 20 06:01:14 PM PDT 24
Peak memory 201600 kb
Host smart-0523eaa6-9972-4643-912f-8dc0362dcb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248168752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.248168752
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3031398811
Short name T521
Test name
Test status
Simulation time 446363142087 ps
CPU time 1443.26 seconds
Started Jul 20 06:01:11 PM PDT 24
Finished Jul 20 06:25:15 PM PDT 24
Peak memory 210196 kb
Host smart-ef412383-5656-4340-93ad-f4b05c9ce6f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031398811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3031398811
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3856332888
Short name T415
Test name
Test status
Simulation time 343353475 ps
CPU time 1.02 seconds
Started Jul 20 06:01:22 PM PDT 24
Finished Jul 20 06:01:24 PM PDT 24
Peak memory 201528 kb
Host smart-dfed9f97-7b70-40c0-9302-3a530b068d0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856332888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3856332888
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1718412004
Short name T184
Test name
Test status
Simulation time 328191626111 ps
CPU time 386.81 seconds
Started Jul 20 06:01:22 PM PDT 24
Finished Jul 20 06:07:50 PM PDT 24
Peak memory 201696 kb
Host smart-667f69e0-9c2f-4d62-ab59-1858d736734c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718412004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1718412004
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2546002002
Short name T523
Test name
Test status
Simulation time 319222289048 ps
CPU time 150.39 seconds
Started Jul 20 06:01:21 PM PDT 24
Finished Jul 20 06:03:52 PM PDT 24
Peak memory 201732 kb
Host smart-03fcd18e-18c6-40c0-b144-3ea8dccdb60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546002002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2546002002
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2758028144
Short name T259
Test name
Test status
Simulation time 481309386121 ps
CPU time 282.59 seconds
Started Jul 20 06:01:14 PM PDT 24
Finished Jul 20 06:05:57 PM PDT 24
Peak memory 201728 kb
Host smart-049f340c-1740-42fa-9d07-3b63a8c4b24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758028144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2758028144
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1104571201
Short name T445
Test name
Test status
Simulation time 330460045259 ps
CPU time 721.01 seconds
Started Jul 20 06:01:12 PM PDT 24
Finished Jul 20 06:13:14 PM PDT 24
Peak memory 201716 kb
Host smart-b5283ae4-9e46-415e-84ea-892c004c02d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104571201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.1104571201
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.1356954495
Short name T772
Test name
Test status
Simulation time 163803589103 ps
CPU time 47.81 seconds
Started Jul 20 06:01:13 PM PDT 24
Finished Jul 20 06:02:01 PM PDT 24
Peak memory 201824 kb
Host smart-21fc643e-ba8f-42b1-a5b5-603c143ccc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356954495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.1356954495
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1358435804
Short name T520
Test name
Test status
Simulation time 163765599858 ps
CPU time 50.07 seconds
Started Jul 20 06:01:12 PM PDT 24
Finished Jul 20 06:02:02 PM PDT 24
Peak memory 201668 kb
Host smart-621e6270-564a-4373-9226-f4a5a01fa73a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358435804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1358435804
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3790033905
Short name T153
Test name
Test status
Simulation time 340103989553 ps
CPU time 185.39 seconds
Started Jul 20 06:01:11 PM PDT 24
Finished Jul 20 06:04:17 PM PDT 24
Peak memory 201744 kb
Host smart-975fb0ef-541d-4250-98ce-c6db68b08ddc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790033905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3790033905
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1012307785
Short name T718
Test name
Test status
Simulation time 590315046754 ps
CPU time 201.69 seconds
Started Jul 20 06:01:12 PM PDT 24
Finished Jul 20 06:04:34 PM PDT 24
Peak memory 201732 kb
Host smart-6ab67432-d5c8-49de-a465-b36edad6efc2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012307785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1012307785
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3902971025
Short name T205
Test name
Test status
Simulation time 119570542753 ps
CPU time 476.33 seconds
Started Jul 20 06:01:22 PM PDT 24
Finished Jul 20 06:09:19 PM PDT 24
Peak memory 202200 kb
Host smart-c67ae9e2-d9cb-4cd4-a6fd-0cb3cfd83c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902971025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3902971025
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.742147085
Short name T391
Test name
Test status
Simulation time 35672271496 ps
CPU time 13.72 seconds
Started Jul 20 06:01:22 PM PDT 24
Finished Jul 20 06:01:36 PM PDT 24
Peak memory 201596 kb
Host smart-f7b59f7a-ecf2-43c4-827d-4c3e281abef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742147085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.742147085
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.4024771254
Short name T418
Test name
Test status
Simulation time 5283029889 ps
CPU time 3.53 seconds
Started Jul 20 06:01:24 PM PDT 24
Finished Jul 20 06:01:28 PM PDT 24
Peak memory 201612 kb
Host smart-3f1d92a0-a323-4ec1-9a27-1685b5f0ba4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024771254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.4024771254
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3694114192
Short name T652
Test name
Test status
Simulation time 5700136901 ps
CPU time 1.99 seconds
Started Jul 20 06:01:13 PM PDT 24
Finished Jul 20 06:01:15 PM PDT 24
Peak memory 201604 kb
Host smart-3cd5136b-fdc4-42d6-84f6-d29780e7da6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694114192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3694114192
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2404203948
Short name T625
Test name
Test status
Simulation time 461115848283 ps
CPU time 443.03 seconds
Started Jul 20 06:01:20 PM PDT 24
Finished Jul 20 06:08:43 PM PDT 24
Peak memory 201728 kb
Host smart-2e1815f0-faff-43ff-958d-29d3439e8d40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404203948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2404203948
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.386357240
Short name T271
Test name
Test status
Simulation time 210896655694 ps
CPU time 166.15 seconds
Started Jul 20 06:01:23 PM PDT 24
Finished Jul 20 06:04:09 PM PDT 24
Peak memory 210476 kb
Host smart-aba80086-d16e-4a95-8706-e3fc91c57bfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386357240 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.386357240
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.1802827801
Short name T598
Test name
Test status
Simulation time 486087078 ps
CPU time 1.64 seconds
Started Jul 20 06:01:28 PM PDT 24
Finished Jul 20 06:01:30 PM PDT 24
Peak memory 201600 kb
Host smart-6bde4cf6-a36a-4830-95f3-2fe8aed39a78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802827801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.1802827801
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2612656469
Short name T484
Test name
Test status
Simulation time 161524347460 ps
CPU time 200.15 seconds
Started Jul 20 06:01:21 PM PDT 24
Finished Jul 20 06:04:42 PM PDT 24
Peak memory 201760 kb
Host smart-19d9482b-a030-4002-8216-b66293c3c47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612656469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2612656469
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.3105186550
Short name T666
Test name
Test status
Simulation time 165412986315 ps
CPU time 190.97 seconds
Started Jul 20 06:01:22 PM PDT 24
Finished Jul 20 06:04:33 PM PDT 24
Peak memory 201808 kb
Host smart-f4f2dc21-672e-463c-91e7-34f98c8e697a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105186550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3105186550
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.49048748
Short name T209
Test name
Test status
Simulation time 326842394231 ps
CPU time 780.98 seconds
Started Jul 20 06:01:20 PM PDT 24
Finished Jul 20 06:14:21 PM PDT 24
Peak memory 201728 kb
Host smart-f3442472-1173-4a66-afc9-52f42fb77828
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=49048748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt
_fixed.49048748
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1295346442
Short name T487
Test name
Test status
Simulation time 324146557928 ps
CPU time 143.96 seconds
Started Jul 20 06:01:23 PM PDT 24
Finished Jul 20 06:03:48 PM PDT 24
Peak memory 201744 kb
Host smart-0c9380b0-b695-4da0-9d9d-eeb7f6d00b7e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295346442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1295346442
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3111910304
Short name T315
Test name
Test status
Simulation time 164006031488 ps
CPU time 172.04 seconds
Started Jul 20 06:01:19 PM PDT 24
Finished Jul 20 06:04:12 PM PDT 24
Peak memory 201776 kb
Host smart-7d654095-b8ad-4c99-8503-44073e22bccd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111910304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3111910304
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1616388388
Short name T1
Test name
Test status
Simulation time 398127276127 ps
CPU time 99.83 seconds
Started Jul 20 06:01:19 PM PDT 24
Finished Jul 20 06:02:59 PM PDT 24
Peak memory 201628 kb
Host smart-4a32409e-39f2-419f-82f7-b9d4ffeb0a94
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616388388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1616388388
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2451078929
Short name T585
Test name
Test status
Simulation time 109377577182 ps
CPU time 657.11 seconds
Started Jul 20 06:01:30 PM PDT 24
Finished Jul 20 06:12:27 PM PDT 24
Peak memory 202124 kb
Host smart-e585431d-22dc-447d-b2a1-16e7cf8e3081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451078929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2451078929
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2185649424
Short name T376
Test name
Test status
Simulation time 40247753738 ps
CPU time 24.63 seconds
Started Jul 20 06:01:32 PM PDT 24
Finished Jul 20 06:01:57 PM PDT 24
Peak memory 201600 kb
Host smart-12a5722a-81e2-46ff-a48b-a1bc39f227f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185649424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2185649424
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1394706763
Short name T568
Test name
Test status
Simulation time 5781804640 ps
CPU time 4.85 seconds
Started Jul 20 06:01:32 PM PDT 24
Finished Jul 20 06:01:38 PM PDT 24
Peak memory 201612 kb
Host smart-a8259bc6-f92f-428d-a520-c2a25fb44b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394706763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1394706763
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.4222601979
Short name T755
Test name
Test status
Simulation time 5982588335 ps
CPU time 7.75 seconds
Started Jul 20 06:01:22 PM PDT 24
Finished Jul 20 06:01:30 PM PDT 24
Peak memory 201596 kb
Host smart-ccf0158b-b786-4126-be22-de6b6af3e8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222601979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.4222601979
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.3789601653
Short name T720
Test name
Test status
Simulation time 322401353027 ps
CPU time 190.74 seconds
Started Jul 20 06:01:32 PM PDT 24
Finished Jul 20 06:04:43 PM PDT 24
Peak memory 201804 kb
Host smart-3e974005-4c4c-42e0-9879-180ab8ec7e0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789601653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.3789601653
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2968395821
Short name T589
Test name
Test status
Simulation time 51279328222 ps
CPU time 190.06 seconds
Started Jul 20 06:01:32 PM PDT 24
Finished Jul 20 06:04:42 PM PDT 24
Peak memory 210400 kb
Host smart-05e1d423-0d78-4337-aa93-efd639437e7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968395821 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2968395821
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3944682406
Short name T548
Test name
Test status
Simulation time 285309455 ps
CPU time 0.98 seconds
Started Jul 20 06:01:41 PM PDT 24
Finished Jul 20 06:01:43 PM PDT 24
Peak memory 201556 kb
Host smart-5a131d04-c97b-4ff6-b1c3-93824dc966d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944682406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3944682406
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1047240744
Short name T48
Test name
Test status
Simulation time 164325549302 ps
CPU time 45.6 seconds
Started Jul 20 06:01:30 PM PDT 24
Finished Jul 20 06:02:16 PM PDT 24
Peak memory 201816 kb
Host smart-d9595c74-191e-480b-b260-286b4d266122
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047240744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1047240744
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2390533900
Short name T210
Test name
Test status
Simulation time 325764176714 ps
CPU time 206.7 seconds
Started Jul 20 06:01:28 PM PDT 24
Finished Jul 20 06:04:55 PM PDT 24
Peak memory 201796 kb
Host smart-0a448029-7d7f-4057-a73d-8ef9ba50a6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390533900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2390533900
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1742501148
Short name T620
Test name
Test status
Simulation time 492440129656 ps
CPU time 274.58 seconds
Started Jul 20 06:01:28 PM PDT 24
Finished Jul 20 06:06:03 PM PDT 24
Peak memory 201680 kb
Host smart-83218851-7b45-426c-a68f-bc203bd232be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742501148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1742501148
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.4049598223
Short name T146
Test name
Test status
Simulation time 163874702533 ps
CPU time 176.26 seconds
Started Jul 20 06:01:31 PM PDT 24
Finished Jul 20 06:04:28 PM PDT 24
Peak memory 201744 kb
Host smart-8ac7f771-a76a-4e4c-a39c-f274bc30e9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049598223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.4049598223
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.4289150970
Short name T653
Test name
Test status
Simulation time 496644756134 ps
CPU time 1078.42 seconds
Started Jul 20 06:01:32 PM PDT 24
Finished Jul 20 06:19:31 PM PDT 24
Peak memory 201736 kb
Host smart-b3fac99c-94f5-4ca4-bb21-44d7635fcdae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289150970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.4289150970
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.31097698
Short name T777
Test name
Test status
Simulation time 540388024315 ps
CPU time 98.74 seconds
Started Jul 20 06:01:31 PM PDT 24
Finished Jul 20 06:03:10 PM PDT 24
Peak memory 201812 kb
Host smart-56d8f938-6a42-4a10-a4db-5633028bed71
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31097698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_w
akeup.31097698
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.20742979
Short name T732
Test name
Test status
Simulation time 401191845076 ps
CPU time 259.67 seconds
Started Jul 20 06:01:32 PM PDT 24
Finished Jul 20 06:05:52 PM PDT 24
Peak memory 201736 kb
Host smart-99fc863f-5360-4a13-bf1d-9f156f4a447d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20742979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.a
dc_ctrl_filters_wakeup_fixed.20742979
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1944061027
Short name T493
Test name
Test status
Simulation time 101445339980 ps
CPU time 411.41 seconds
Started Jul 20 06:01:38 PM PDT 24
Finished Jul 20 06:08:30 PM PDT 24
Peak memory 202116 kb
Host smart-c9f99deb-fff5-4b8f-b53d-fed4bbc7e2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944061027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1944061027
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3427028769
Short name T424
Test name
Test status
Simulation time 36274193335 ps
CPU time 20.55 seconds
Started Jul 20 06:01:40 PM PDT 24
Finished Jul 20 06:02:01 PM PDT 24
Peak memory 201612 kb
Host smart-6d86991d-64d8-4412-ad9c-bd8922af3986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427028769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3427028769
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3408567179
Short name T459
Test name
Test status
Simulation time 4477934454 ps
CPU time 2.72 seconds
Started Jul 20 06:01:39 PM PDT 24
Finished Jul 20 06:01:42 PM PDT 24
Peak memory 201592 kb
Host smart-1a4ebb4a-f02f-4f5e-9ab4-cfd1bc437c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408567179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3408567179
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.2018936271
Short name T342
Test name
Test status
Simulation time 5718254272 ps
CPU time 12.98 seconds
Started Jul 20 06:01:28 PM PDT 24
Finished Jul 20 06:01:41 PM PDT 24
Peak memory 201620 kb
Host smart-b033c777-7d5c-4ccb-b47a-715b080e43b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018936271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2018936271
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3300600040
Short name T303
Test name
Test status
Simulation time 454204608507 ps
CPU time 1318.14 seconds
Started Jul 20 06:01:39 PM PDT 24
Finished Jul 20 06:23:37 PM PDT 24
Peak memory 210308 kb
Host smart-684397ba-33ef-444d-8ab3-34b425f058ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300600040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3300600040
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.654261114
Short name T454
Test name
Test status
Simulation time 73140000415 ps
CPU time 296.44 seconds
Started Jul 20 06:01:38 PM PDT 24
Finished Jul 20 06:06:35 PM PDT 24
Peak memory 218128 kb
Host smart-0426f299-b60f-4dcc-8507-c552f0399cad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654261114 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.654261114
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3460128362
Short name T361
Test name
Test status
Simulation time 332654443 ps
CPU time 0.72 seconds
Started Jul 20 06:01:57 PM PDT 24
Finished Jul 20 06:01:58 PM PDT 24
Peak memory 201528 kb
Host smart-2903d8c5-919a-4f7e-a1d7-86b5108df8d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460128362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3460128362
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2607602632
Short name T135
Test name
Test status
Simulation time 368674555776 ps
CPU time 431.27 seconds
Started Jul 20 06:01:51 PM PDT 24
Finished Jul 20 06:09:03 PM PDT 24
Peak memory 201752 kb
Host smart-7ff40502-5c47-46c6-8d5e-2b05d58723b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607602632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2607602632
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3084493661
Short name T737
Test name
Test status
Simulation time 322040076240 ps
CPU time 666.9 seconds
Started Jul 20 06:01:47 PM PDT 24
Finished Jul 20 06:12:54 PM PDT 24
Peak memory 201804 kb
Host smart-15a85c2f-d98a-4206-8322-20806ab74dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084493661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3084493661
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2244495363
Short name T791
Test name
Test status
Simulation time 328642252216 ps
CPU time 71.33 seconds
Started Jul 20 06:01:48 PM PDT 24
Finished Jul 20 06:03:00 PM PDT 24
Peak memory 201728 kb
Host smart-6ee7b2b8-e3b4-4b84-9cfb-6e6b86a89a1a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244495363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2244495363
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1058802198
Short name T304
Test name
Test status
Simulation time 338467676721 ps
CPU time 742.02 seconds
Started Jul 20 06:01:46 PM PDT 24
Finished Jul 20 06:14:08 PM PDT 24
Peak memory 201704 kb
Host smart-c066fe42-1195-42c9-8794-5f6bafe9a116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058802198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1058802198
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.3979161884
Short name T466
Test name
Test status
Simulation time 163443993005 ps
CPU time 195.92 seconds
Started Jul 20 06:01:51 PM PDT 24
Finished Jul 20 06:05:08 PM PDT 24
Peak memory 201716 kb
Host smart-a946421d-f640-4ea6-b8c5-8efc1ce057a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979161884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.3979161884
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3830267848
Short name T660
Test name
Test status
Simulation time 375740155799 ps
CPU time 456.37 seconds
Started Jul 20 06:01:47 PM PDT 24
Finished Jul 20 06:09:24 PM PDT 24
Peak memory 201820 kb
Host smart-4a61aefb-070f-46de-a58e-c5f34dfb4c26
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830267848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3830267848
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1261965821
Short name T400
Test name
Test status
Simulation time 401803354765 ps
CPU time 870.39 seconds
Started Jul 20 06:01:47 PM PDT 24
Finished Jul 20 06:16:18 PM PDT 24
Peak memory 201716 kb
Host smart-1dea5a5d-0890-40e0-b252-dd46cb59bea9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261965821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1261965821
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2976289321
Short name T461
Test name
Test status
Simulation time 68047929961 ps
CPU time 305.93 seconds
Started Jul 20 06:01:49 PM PDT 24
Finished Jul 20 06:06:55 PM PDT 24
Peak memory 202076 kb
Host smart-76a2f12b-f9ff-4292-8b6d-9d11ec7dba96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976289321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2976289321
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1457331746
Short name T410
Test name
Test status
Simulation time 43071093437 ps
CPU time 28.15 seconds
Started Jul 20 06:01:52 PM PDT 24
Finished Jul 20 06:02:21 PM PDT 24
Peak memory 201588 kb
Host smart-b2a6c2fb-a8fe-407b-9c17-ccbd1d8fe6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457331746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1457331746
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.764536506
Short name T677
Test name
Test status
Simulation time 3970835111 ps
CPU time 8.76 seconds
Started Jul 20 06:01:48 PM PDT 24
Finished Jul 20 06:01:57 PM PDT 24
Peak memory 201600 kb
Host smart-1f86ab43-0db2-4358-aadb-9f3ae293feac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764536506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.764536506
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3368017149
Short name T719
Test name
Test status
Simulation time 6046478840 ps
CPU time 4.43 seconds
Started Jul 20 06:01:39 PM PDT 24
Finished Jul 20 06:01:44 PM PDT 24
Peak memory 201612 kb
Host smart-a951d24f-dc2c-41da-a1b9-8a3732f5acb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368017149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3368017149
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3075139763
Short name T39
Test name
Test status
Simulation time 19338368001 ps
CPU time 67.35 seconds
Started Jul 20 06:01:46 PM PDT 24
Finished Jul 20 06:02:54 PM PDT 24
Peak memory 210344 kb
Host smart-c32bca46-0681-425f-940a-5749b1c594f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075139763 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3075139763
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3442904857
Short name T367
Test name
Test status
Simulation time 568063265 ps
CPU time 0.76 seconds
Started Jul 20 05:56:34 PM PDT 24
Finished Jul 20 05:56:38 PM PDT 24
Peak memory 201504 kb
Host smart-0ade5ae6-3770-4bf0-9b53-6e7580741262
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442904857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3442904857
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1692454027
Short name T292
Test name
Test status
Simulation time 328291766830 ps
CPU time 392.27 seconds
Started Jul 20 05:56:33 PM PDT 24
Finished Jul 20 06:03:09 PM PDT 24
Peak memory 201756 kb
Host smart-8605fdc7-9f39-49e8-b7cd-e2fc7ca802bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692454027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1692454027
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3128361270
Short name T744
Test name
Test status
Simulation time 323326710814 ps
CPU time 671.71 seconds
Started Jul 20 05:56:33 PM PDT 24
Finished Jul 20 06:07:48 PM PDT 24
Peak memory 201692 kb
Host smart-3809fc0a-fbc4-49b4-99ce-e4639e6bb1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128361270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3128361270
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1824584083
Short name T475
Test name
Test status
Simulation time 334692508972 ps
CPU time 801.84 seconds
Started Jul 20 05:56:31 PM PDT 24
Finished Jul 20 06:09:56 PM PDT 24
Peak memory 201636 kb
Host smart-803ef9f6-4168-450f-888b-a0571e395027
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824584083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1824584083
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1816320531
Short name T124
Test name
Test status
Simulation time 497342258025 ps
CPU time 1172.53 seconds
Started Jul 20 05:56:34 PM PDT 24
Finished Jul 20 06:16:10 PM PDT 24
Peak memory 201756 kb
Host smart-e1b58a13-796e-4f57-b146-2dcd9156ad0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816320531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1816320531
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3979378909
Short name T494
Test name
Test status
Simulation time 496174066585 ps
CPU time 1226.24 seconds
Started Jul 20 05:56:35 PM PDT 24
Finished Jul 20 06:17:04 PM PDT 24
Peak memory 201728 kb
Host smart-78808f17-61e8-4cb1-a93d-086f545416d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979378909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3979378909
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1943337511
Short name T332
Test name
Test status
Simulation time 545707659785 ps
CPU time 1304.46 seconds
Started Jul 20 05:56:39 PM PDT 24
Finished Jul 20 06:18:24 PM PDT 24
Peak memory 201812 kb
Host smart-46fb2425-e337-41e9-ab7a-64da966e8a86
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943337511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1943337511
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.3741214198
Short name T601
Test name
Test status
Simulation time 609147136452 ps
CPU time 352.7 seconds
Started Jul 20 05:56:37 PM PDT 24
Finished Jul 20 06:02:32 PM PDT 24
Peak memory 201732 kb
Host smart-68de8a18-c8b1-45e9-8bc0-0d6b3df9d2e7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741214198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.3741214198
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.999091416
Short name T87
Test name
Test status
Simulation time 122362930544 ps
CPU time 449.52 seconds
Started Jul 20 05:56:37 PM PDT 24
Finished Jul 20 06:04:09 PM PDT 24
Peak memory 202088 kb
Host smart-d5405951-041c-4840-8ef9-f35d14ccf115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999091416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.999091416
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.4063862162
Short name T550
Test name
Test status
Simulation time 39113198010 ps
CPU time 22.48 seconds
Started Jul 20 05:56:41 PM PDT 24
Finished Jul 20 05:57:05 PM PDT 24
Peak memory 201596 kb
Host smart-b66db8ab-3721-45eb-a450-4f35fefc2cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063862162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.4063862162
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3211859916
Short name T532
Test name
Test status
Simulation time 4645577316 ps
CPU time 11.01 seconds
Started Jul 20 05:56:40 PM PDT 24
Finished Jul 20 05:56:52 PM PDT 24
Peak memory 201612 kb
Host smart-777ec528-8358-4178-b139-87264ecd17e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211859916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3211859916
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.4053035944
Short name T562
Test name
Test status
Simulation time 5814855833 ps
CPU time 13.73 seconds
Started Jul 20 05:56:38 PM PDT 24
Finished Jul 20 05:56:53 PM PDT 24
Peak memory 201604 kb
Host smart-7d2a5ce4-f307-4412-b950-e5a6f1509d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053035944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.4053035944
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1046801983
Short name T276
Test name
Test status
Simulation time 553194924979 ps
CPU time 232.23 seconds
Started Jul 20 05:56:37 PM PDT 24
Finished Jul 20 06:00:31 PM PDT 24
Peak memory 201712 kb
Host smart-bee98596-390d-44f4-ae6a-a39ab1b45598
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046801983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1046801983
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1199951078
Short name T38
Test name
Test status
Simulation time 84381931255 ps
CPU time 187.3 seconds
Started Jul 20 05:56:29 PM PDT 24
Finished Jul 20 05:59:37 PM PDT 24
Peak memory 210060 kb
Host smart-1dc325bd-5218-47fe-ad0f-1a15f12b89ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199951078 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1199951078
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1139392299
Short name T357
Test name
Test status
Simulation time 423354277 ps
CPU time 0.85 seconds
Started Jul 20 05:56:46 PM PDT 24
Finished Jul 20 05:56:48 PM PDT 24
Peak memory 201560 kb
Host smart-2fc4d309-2c59-4fbc-bd15-ecfd228595e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139392299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1139392299
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2907773205
Short name T609
Test name
Test status
Simulation time 186976190880 ps
CPU time 151.59 seconds
Started Jul 20 05:56:47 PM PDT 24
Finished Jul 20 05:59:21 PM PDT 24
Peak memory 201732 kb
Host smart-47aa5a5e-14db-4537-9764-ad6f46179012
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907773205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2907773205
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.533955578
Short name T136
Test name
Test status
Simulation time 363167578924 ps
CPU time 454.89 seconds
Started Jul 20 05:56:39 PM PDT 24
Finished Jul 20 06:04:15 PM PDT 24
Peak memory 201800 kb
Host smart-17de1a0e-df0c-4da1-a08a-026516374c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533955578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.533955578
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3409442463
Short name T307
Test name
Test status
Simulation time 493201731217 ps
CPU time 1138.18 seconds
Started Jul 20 05:56:46 PM PDT 24
Finished Jul 20 06:15:47 PM PDT 24
Peak memory 201404 kb
Host smart-bd0cdbdb-3a37-4b78-96df-57e7474cc870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409442463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3409442463
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3592708282
Short name T462
Test name
Test status
Simulation time 324685368279 ps
CPU time 404.8 seconds
Started Jul 20 05:56:43 PM PDT 24
Finished Jul 20 06:03:29 PM PDT 24
Peak memory 201708 kb
Host smart-2e51f700-7cd9-4dd7-b34b-107e27e5bb03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592708282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3592708282
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3726619497
Short name T448
Test name
Test status
Simulation time 166453513185 ps
CPU time 118.86 seconds
Started Jul 20 05:56:33 PM PDT 24
Finished Jul 20 05:58:35 PM PDT 24
Peak memory 201812 kb
Host smart-0dbe68f2-eeea-46c4-9953-f72cda224b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726619497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3726619497
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2269053794
Short name T495
Test name
Test status
Simulation time 498459847004 ps
CPU time 1175.5 seconds
Started Jul 20 05:56:44 PM PDT 24
Finished Jul 20 06:16:21 PM PDT 24
Peak memory 201772 kb
Host smart-3005ead6-dcbd-4bd3-b3b8-e5d378d7de48
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269053794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2269053794
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3358347442
Short name T238
Test name
Test status
Simulation time 387313541200 ps
CPU time 461.88 seconds
Started Jul 20 05:56:40 PM PDT 24
Finished Jul 20 06:04:23 PM PDT 24
Peak memory 201700 kb
Host smart-d470117e-8149-4eda-9105-7459a1fe7ec0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358347442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3358347442
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1008223448
Short name T555
Test name
Test status
Simulation time 409201569586 ps
CPU time 264.19 seconds
Started Jul 20 05:56:45 PM PDT 24
Finished Jul 20 06:01:10 PM PDT 24
Peak memory 201800 kb
Host smart-b5f651ba-8041-4da5-a92f-8591ab01826e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008223448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1008223448
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2759694355
Short name T336
Test name
Test status
Simulation time 106063112897 ps
CPU time 506.21 seconds
Started Jul 20 05:56:41 PM PDT 24
Finished Jul 20 06:05:08 PM PDT 24
Peak memory 202096 kb
Host smart-57195bfe-b549-4806-9fa3-f3d76b85bc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759694355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2759694355
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3399615740
Short name T571
Test name
Test status
Simulation time 37586217948 ps
CPU time 52.92 seconds
Started Jul 20 05:56:47 PM PDT 24
Finished Jul 20 05:57:42 PM PDT 24
Peak memory 201596 kb
Host smart-293df16f-1ac8-4b03-9bf5-5d2323f7ab06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399615740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3399615740
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.698195274
Short name T341
Test name
Test status
Simulation time 4520757640 ps
CPU time 3.09 seconds
Started Jul 20 05:56:42 PM PDT 24
Finished Jul 20 05:56:46 PM PDT 24
Peak memory 201612 kb
Host smart-89591a5b-4a96-433c-925a-0a6a449d9414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698195274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.698195274
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.4191030165
Short name T704
Test name
Test status
Simulation time 5839242338 ps
CPU time 13.94 seconds
Started Jul 20 05:56:32 PM PDT 24
Finished Jul 20 05:56:48 PM PDT 24
Peak memory 201588 kb
Host smart-faea37c2-5444-444d-9b19-3f0bbeda9b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191030165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.4191030165
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1413093482
Short name T764
Test name
Test status
Simulation time 168419398573 ps
CPU time 385.96 seconds
Started Jul 20 05:56:46 PM PDT 24
Finished Jul 20 06:03:14 PM PDT 24
Peak memory 201616 kb
Host smart-3f41d5e7-b2a9-42b9-ac64-73c415f84398
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413093482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1413093482
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.4243453708
Short name T546
Test name
Test status
Simulation time 60152748871 ps
CPU time 127.45 seconds
Started Jul 20 05:56:46 PM PDT 24
Finished Jul 20 05:58:56 PM PDT 24
Peak memory 210132 kb
Host smart-0b0660e6-d357-4c41-8a6f-7da2dbaefb27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243453708 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.4243453708
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.2187269994
Short name T439
Test name
Test status
Simulation time 502474178 ps
CPU time 0.91 seconds
Started Jul 20 05:56:46 PM PDT 24
Finished Jul 20 05:56:48 PM PDT 24
Peak memory 201536 kb
Host smart-72d21cc1-ab63-420d-bb4d-8292cc92e289
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187269994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2187269994
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3593322348
Short name T265
Test name
Test status
Simulation time 177960642654 ps
CPU time 211.84 seconds
Started Jul 20 05:56:46 PM PDT 24
Finished Jul 20 06:00:20 PM PDT 24
Peak memory 201732 kb
Host smart-dd1e9e04-d0d8-4607-9023-022c11819c1d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593322348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3593322348
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.1762543275
Short name T311
Test name
Test status
Simulation time 345022737950 ps
CPU time 773.45 seconds
Started Jul 20 05:56:46 PM PDT 24
Finished Jul 20 06:09:41 PM PDT 24
Peak memory 201748 kb
Host smart-4b37e0b5-544e-45da-8f1f-1da04aa96c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762543275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1762543275
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1412448014
Short name T318
Test name
Test status
Simulation time 166077897299 ps
CPU time 198.06 seconds
Started Jul 20 05:56:44 PM PDT 24
Finished Jul 20 06:00:03 PM PDT 24
Peak memory 201736 kb
Host smart-e695bbff-e104-417f-be2f-8680b65290d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412448014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1412448014
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1547517724
Short name T726
Test name
Test status
Simulation time 336524062651 ps
CPU time 157.16 seconds
Started Jul 20 05:56:44 PM PDT 24
Finished Jul 20 05:59:22 PM PDT 24
Peak memory 201716 kb
Host smart-4c29d0c3-7dde-4b4e-8865-fcbdaee19ada
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547517724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1547517724
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.2477232968
Short name T242
Test name
Test status
Simulation time 501927305886 ps
CPU time 108.61 seconds
Started Jul 20 05:56:40 PM PDT 24
Finished Jul 20 05:58:30 PM PDT 24
Peak memory 201756 kb
Host smart-465f04cb-be55-4377-99a2-64aa48952e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477232968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2477232968
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.968337538
Short name T346
Test name
Test status
Simulation time 324101034499 ps
CPU time 724.83 seconds
Started Jul 20 05:56:47 PM PDT 24
Finished Jul 20 06:08:55 PM PDT 24
Peak memory 201712 kb
Host smart-b15e3e86-c703-4079-a9a8-008e212b0089
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=968337538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.968337538
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.307564832
Short name T530
Test name
Test status
Simulation time 273997990980 ps
CPU time 659.73 seconds
Started Jul 20 05:56:48 PM PDT 24
Finished Jul 20 06:07:50 PM PDT 24
Peak memory 201744 kb
Host smart-981946cd-af6e-4f1b-b6a8-f5ffebd592cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307564832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.307564832
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.389490167
Short name T780
Test name
Test status
Simulation time 591329991954 ps
CPU time 1388.45 seconds
Started Jul 20 05:56:44 PM PDT 24
Finished Jul 20 06:19:54 PM PDT 24
Peak memory 201796 kb
Host smart-e2fe434a-92c6-46ee-8118-5f0c64eda24c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389490167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.a
dc_ctrl_filters_wakeup_fixed.389490167
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.465287230
Short name T198
Test name
Test status
Simulation time 111706632114 ps
CPU time 406.14 seconds
Started Jul 20 05:56:47 PM PDT 24
Finished Jul 20 06:03:35 PM PDT 24
Peak memory 202100 kb
Host smart-64316849-39b9-49fe-b152-142c180339c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465287230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.465287230
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2626351027
Short name T483
Test name
Test status
Simulation time 41670093990 ps
CPU time 55.95 seconds
Started Jul 20 05:56:39 PM PDT 24
Finished Jul 20 05:57:36 PM PDT 24
Peak memory 201608 kb
Host smart-d2c07181-ba7a-4017-a00b-5d0fe953a5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626351027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2626351027
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.631314027
Short name T450
Test name
Test status
Simulation time 2819045627 ps
CPU time 3.65 seconds
Started Jul 20 05:56:48 PM PDT 24
Finished Jul 20 05:56:53 PM PDT 24
Peak memory 201612 kb
Host smart-ac5dbf4a-4ce8-446e-9441-5569f37e0c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631314027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.631314027
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3184565143
Short name T743
Test name
Test status
Simulation time 6000911387 ps
CPU time 4.51 seconds
Started Jul 20 05:56:43 PM PDT 24
Finished Jul 20 05:56:49 PM PDT 24
Peak memory 201604 kb
Host smart-9e15c034-8ce9-4f07-8d22-a48be0786e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184565143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3184565143
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1872190736
Short name T768
Test name
Test status
Simulation time 2853998145770 ps
CPU time 5701.91 seconds
Started Jul 20 05:56:43 PM PDT 24
Finished Jul 20 07:31:46 PM PDT 24
Peak memory 213384 kb
Host smart-5c169e91-8c6d-4023-b568-54b3c7a625d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872190736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1872190736
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.563298625
Short name T192
Test name
Test status
Simulation time 183348342636 ps
CPU time 367.75 seconds
Started Jul 20 05:56:45 PM PDT 24
Finished Jul 20 06:02:54 PM PDT 24
Peak memory 210428 kb
Host smart-63e47411-79e8-4414-8de5-5d175fb233d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563298625 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.563298625
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1152375508
Short name T386
Test name
Test status
Simulation time 510145535 ps
CPU time 1.78 seconds
Started Jul 20 05:56:47 PM PDT 24
Finished Jul 20 05:56:51 PM PDT 24
Peak memory 201536 kb
Host smart-96c7f77b-c615-4bcb-ae67-bb262310098e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152375508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1152375508
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1319529108
Short name T256
Test name
Test status
Simulation time 334090368845 ps
CPU time 92.55 seconds
Started Jul 20 05:56:41 PM PDT 24
Finished Jul 20 05:58:14 PM PDT 24
Peak memory 201756 kb
Host smart-1ba6d15c-4530-4e81-bf4a-9f61fba5ba33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319529108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1319529108
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2161875703
Short name T673
Test name
Test status
Simulation time 166790027004 ps
CPU time 86.61 seconds
Started Jul 20 05:56:48 PM PDT 24
Finished Jul 20 05:58:17 PM PDT 24
Peak memory 201736 kb
Host smart-f5198765-5917-4517-8d46-2e349c29ca16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161875703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2161875703
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.997238460
Short name T370
Test name
Test status
Simulation time 318859049169 ps
CPU time 180.47 seconds
Started Jul 20 05:56:46 PM PDT 24
Finished Jul 20 05:59:49 PM PDT 24
Peak memory 201356 kb
Host smart-36ebe5c3-4252-4f59-bb7e-31da536ac6eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=997238460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.997238460
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2781930373
Short name T536
Test name
Test status
Simulation time 167242110298 ps
CPU time 94.04 seconds
Started Jul 20 05:56:35 PM PDT 24
Finished Jul 20 05:58:12 PM PDT 24
Peak memory 201816 kb
Host smart-801e6dd1-a0e4-4f35-a7e4-10c37147d25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781930373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2781930373
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1080992779
Short name T388
Test name
Test status
Simulation time 160857967856 ps
CPU time 98.87 seconds
Started Jul 20 05:56:47 PM PDT 24
Finished Jul 20 05:58:28 PM PDT 24
Peak memory 201740 kb
Host smart-0744de4b-3f2c-4885-ae63-c2d9c6b018a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080992779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1080992779
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3571567466
Short name T283
Test name
Test status
Simulation time 399508296800 ps
CPU time 885.56 seconds
Started Jul 20 05:56:39 PM PDT 24
Finished Jul 20 06:11:26 PM PDT 24
Peak memory 201868 kb
Host smart-c1f16a2b-d703-419b-aafd-f04b4c191e66
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571567466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.3571567466
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1653015682
Short name T769
Test name
Test status
Simulation time 392138020700 ps
CPU time 902.96 seconds
Started Jul 20 05:56:47 PM PDT 24
Finished Jul 20 06:11:52 PM PDT 24
Peak memory 201724 kb
Host smart-ec8d4e0f-a06f-42e9-a024-189c91fdba22
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653015682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1653015682
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.704881001
Short name T689
Test name
Test status
Simulation time 108539419814 ps
CPU time 461.62 seconds
Started Jul 20 05:56:40 PM PDT 24
Finished Jul 20 06:04:23 PM PDT 24
Peak memory 202092 kb
Host smart-0f2e6338-677e-40eb-a2d9-c743d0e79cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704881001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.704881001
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1724875685
Short name T182
Test name
Test status
Simulation time 36244468530 ps
CPU time 84.43 seconds
Started Jul 20 05:56:48 PM PDT 24
Finished Jul 20 05:58:14 PM PDT 24
Peak memory 201600 kb
Host smart-564e5db1-8f91-44bc-8242-65efcfca8e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724875685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1724875685
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.523235611
Short name T559
Test name
Test status
Simulation time 4384636816 ps
CPU time 5.44 seconds
Started Jul 20 05:56:39 PM PDT 24
Finished Jul 20 05:56:46 PM PDT 24
Peak memory 201612 kb
Host smart-83aa73cb-4c5a-4533-adbf-433bba116899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523235611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.523235611
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3464421182
Short name T468
Test name
Test status
Simulation time 5924826603 ps
CPU time 9.15 seconds
Started Jul 20 05:56:46 PM PDT 24
Finished Jul 20 05:56:57 PM PDT 24
Peak memory 201616 kb
Host smart-d1591107-2b7f-44af-985d-2a282bebccad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464421182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3464421182
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2731042948
Short name T289
Test name
Test status
Simulation time 1005118676675 ps
CPU time 2855.03 seconds
Started Jul 20 05:56:49 PM PDT 24
Finished Jul 20 06:44:26 PM PDT 24
Peak memory 202092 kb
Host smart-c89dd1a8-a4ee-4c8d-b6a7-b5707c85a9a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731042948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2731042948
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.383650513
Short name T712
Test name
Test status
Simulation time 55194333230 ps
CPU time 44.71 seconds
Started Jul 20 05:56:43 PM PDT 24
Finished Jul 20 05:57:29 PM PDT 24
Peak memory 209960 kb
Host smart-ac68dbe7-2da6-4406-8657-3cc0af33cad3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383650513 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.383650513
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1100893439
Short name T750
Test name
Test status
Simulation time 423002875 ps
CPU time 1.63 seconds
Started Jul 20 05:56:49 PM PDT 24
Finished Jul 20 05:56:52 PM PDT 24
Peak memory 201556 kb
Host smart-6a3a96ef-e98d-4a74-b173-69b773dba961
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100893439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1100893439
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3687213064
Short name T189
Test name
Test status
Simulation time 511922677141 ps
CPU time 207.25 seconds
Started Jul 20 05:56:44 PM PDT 24
Finished Jul 20 06:00:12 PM PDT 24
Peak memory 201792 kb
Host smart-1eeb0756-5b81-4a82-a258-e98ba5e5b9a8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687213064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3687213064
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2089455510
Short name T89
Test name
Test status
Simulation time 323342648310 ps
CPU time 345.34 seconds
Started Jul 20 05:56:49 PM PDT 24
Finished Jul 20 06:02:36 PM PDT 24
Peak memory 201736 kb
Host smart-d0ff08e8-cc31-44f4-91cf-55f97b512d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089455510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2089455510
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1501237886
Short name T414
Test name
Test status
Simulation time 326195162899 ps
CPU time 196.69 seconds
Started Jul 20 05:56:43 PM PDT 24
Finished Jul 20 06:00:00 PM PDT 24
Peak memory 201720 kb
Host smart-ce2fc6bb-237e-412f-a2f3-05a9fddaa34f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501237886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1501237886
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2445840677
Short name T241
Test name
Test status
Simulation time 325728919316 ps
CPU time 775.92 seconds
Started Jul 20 05:56:40 PM PDT 24
Finished Jul 20 06:09:37 PM PDT 24
Peak memory 201804 kb
Host smart-210f6d68-9dac-4e05-9fb5-385ed5db9321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445840677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2445840677
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.1019390708
Short name T173
Test name
Test status
Simulation time 163903972518 ps
CPU time 91.69 seconds
Started Jul 20 05:56:49 PM PDT 24
Finished Jul 20 05:58:22 PM PDT 24
Peak memory 201800 kb
Host smart-065600cc-047b-4a8b-8830-8091b56493a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019390708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.1019390708
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2044074811
Short name T252
Test name
Test status
Simulation time 365357505227 ps
CPU time 805 seconds
Started Jul 20 05:56:46 PM PDT 24
Finished Jul 20 06:10:13 PM PDT 24
Peak memory 201792 kb
Host smart-927750cf-1aea-46bf-a749-724e7af2a74f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044074811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2044074811
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1014745603
Short name T749
Test name
Test status
Simulation time 194655049090 ps
CPU time 413.75 seconds
Started Jul 20 05:56:46 PM PDT 24
Finished Jul 20 06:03:41 PM PDT 24
Peak memory 201736 kb
Host smart-430d04d5-afa1-4990-9ae5-45f9bb509b57
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014745603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1014745603
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2867339509
Short name T335
Test name
Test status
Simulation time 79527696308 ps
CPU time 202.04 seconds
Started Jul 20 05:56:42 PM PDT 24
Finished Jul 20 06:00:05 PM PDT 24
Peak memory 202036 kb
Host smart-fccc0740-9c98-4ab4-82b5-3f5fe7a14a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867339509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2867339509
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3150626561
Short name T500
Test name
Test status
Simulation time 29637720890 ps
CPU time 70.41 seconds
Started Jul 20 05:56:47 PM PDT 24
Finished Jul 20 05:58:00 PM PDT 24
Peak memory 201592 kb
Host smart-86aab3e5-7cdd-4bc1-a74a-a70bf7bec0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150626561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3150626561
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.447865142
Short name T518
Test name
Test status
Simulation time 4543781725 ps
CPU time 3.38 seconds
Started Jul 20 05:56:37 PM PDT 24
Finished Jul 20 05:56:43 PM PDT 24
Peak memory 201556 kb
Host smart-18320661-d1c4-4bd8-9d74-4b528fa0d61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447865142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.447865142
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.4085826548
Short name T655
Test name
Test status
Simulation time 5642572934 ps
CPU time 14.75 seconds
Started Jul 20 05:56:45 PM PDT 24
Finished Jul 20 05:57:01 PM PDT 24
Peak memory 201600 kb
Host smart-c01dacd7-164b-4875-9714-cf71c84fb824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085826548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.4085826548
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1872276567
Short name T81
Test name
Test status
Simulation time 167912687986 ps
CPU time 185.9 seconds
Started Jul 20 05:56:44 PM PDT 24
Finished Jul 20 05:59:51 PM PDT 24
Peak memory 201732 kb
Host smart-26acd4b1-1022-491f-aa29-f570f0dc9f35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872276567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1872276567
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1599933378
Short name T280
Test name
Test status
Simulation time 23577119659 ps
CPU time 56.33 seconds
Started Jul 20 05:56:41 PM PDT 24
Finished Jul 20 05:57:38 PM PDT 24
Peak memory 201856 kb
Host smart-606ee24f-36de-410c-8bb5-f4efe1231721
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599933378 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1599933378
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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