Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1228648	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1200244

1

T1

373

T2

2099

T3

1896

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2127565	1			T1	19		T2	4019		T3	2900
values[0x0]	150489	1			T1	473		T2	127		T3	458
values[0x1]	150838	1			T1	383		T2	138		T3	445

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	983969	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1444923

1

T1

440

T2

2518

T3

2265

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24261	1			T1	3		T3	11		T4	7
valid_sources[0x01]	8804	1			T1	4		T3	2		T4	7
valid_sources[0x02]	12234	1			T1	4		T4	8		T6	5
valid_sources[0x03]	6853	1			T1	3		T3	3		T4	3
valid_sources[0x04]	6678	1			T1	5		T4	6		T5	9
valid_sources[0x05]	6651	1			T1	1		T3	14		T4	7
valid_sources[0x06]	11122	1			T1	5		T3	11		T4	10
valid_sources[0x07]	13950	1			T1	3		T3	2		T4	8
valid_sources[0x08]	15569	1			T1	6		T3	3		T4	17
valid_sources[0x09]	6723	1			T1	2		T3	31		T4	6
valid_sources[0x0a]	11521	1			T1	3		T3	9		T4	3
valid_sources[0x0b]	15207	1			T1	2		T3	37		T4	11
valid_sources[0x0c]	11920	1			T1	2		T3	29		T4	8
valid_sources[0x0d]	10059	1			T3	4		T4	11		T5	3
valid_sources[0x0e]	12429	1			T1	4		T3	4		T4	13
valid_sources[0x0f]	12085	1			T1	1		T3	3		T4	17
valid_sources[0x10]	6875	1			T1	7		T3	2		T4	5
valid_sources[0x11]	6958	1			T1	5		T3	1		T4	4
valid_sources[0x12]	6486	1			T1	4		T4	6		T5	7
valid_sources[0x13]	6709	1			T1	5		T4	2		T6	6
valid_sources[0x14]	14129	1			T1	15		T3	10		T4	7
valid_sources[0x15]	6912	1			T1	3		T3	9		T4	5
valid_sources[0x16]	7789	1			T4	5		T6	1		T7	52
valid_sources[0x17]	12254	1			T1	5		T3	4		T4	6
valid_sources[0x18]	8231	1			T1	2		T4	7		T5	4
valid_sources[0x19]	6859	1			T1	2		T3	5		T4	5
valid_sources[0x1a]	6875	1			T1	3		T3	24		T4	6
valid_sources[0x1b]	11522	1			T1	3		T3	14		T4	10
valid_sources[0x1c]	9800	1			T1	2		T3	5		T4	5
valid_sources[0x1d]	7836	1			T1	5		T3	6		T4	9
valid_sources[0x1e]	7003	1			T1	3		T3	41		T4	2
valid_sources[0x1f]	13225	1			T1	1		T4	6		T5	14
valid_sources[0x20]	6793	1			T1	1		T3	7		T4	7
valid_sources[0x21]	7094	1			T1	2		T3	4		T4	4
valid_sources[0x22]	12341	1			T1	3		T3	4		T4	5
valid_sources[0x23]	7752	1			T1	5		T3	9		T4	9
valid_sources[0x24]	6965	1			T1	4		T3	3		T4	5
valid_sources[0x25]	7046	1			T1	1		T3	6		T4	7
valid_sources[0x26]	6622	1			T1	5		T3	8		T4	6
valid_sources[0x27]	6558	1			T1	4		T3	4		T4	1
valid_sources[0x28]	8696	1			T1	5		T3	6		T4	8
valid_sources[0x29]	6749	1			T1	1		T3	2		T4	11
valid_sources[0x2a]	7304	1			T1	1		T3	9		T4	9
valid_sources[0x2b]	7861	1			T1	2		T3	19		T4	4
valid_sources[0x2c]	8428	1			T1	1		T3	527		T4	8
valid_sources[0x2d]	6948	1			T1	4		T3	68		T4	9
valid_sources[0x2e]	8469	1			T1	1		T3	20		T4	5
valid_sources[0x2f]	8927	1			T1	4		T3	7		T4	8
valid_sources[0x30]	6853	1			T1	4		T3	2		T4	5
valid_sources[0x31]	11187	1			T1	1		T3	34		T4	7
valid_sources[0x32]	7045	1			T1	4		T3	28		T4	4
valid_sources[0x33]	11386	1			T1	1		T3	6		T4	9
valid_sources[0x34]	10884	1			T1	2		T3	4		T4	4
valid_sources[0x35]	7405	1			T1	3		T3	8		T4	8
valid_sources[0x36]	6936	1			T1	6		T3	11		T4	8
valid_sources[0x37]	6875	1			T1	5		T3	5		T4	9
valid_sources[0x38]	8291	1			T3	48		T4	4		T5	8
valid_sources[0x39]	6900	1			T1	2		T3	7		T4	6
valid_sources[0x3a]	18006	1			T1	2		T3	4		T4	9
valid_sources[0x3b]	7822	1			T1	6		T3	1		T4	7
valid_sources[0x3c]	7370	1			T1	3		T3	30		T4	9
valid_sources[0x3d]	20062	1			T1	5		T3	11		T4	8
valid_sources[0x3e]	8756	1			T1	4		T3	7		T4	7
valid_sources[0x3f]	7013	1			T1	5		T4	10		T5	2
valid_sources[0x40]	6984	1			T1	2		T3	2		T4	7
valid_sources[0x41]	11324	1			T1	2		T3	2		T4	6
valid_sources[0x42]	6518	1			T1	2		T3	9		T4	11
valid_sources[0x43]	6600	1			T1	1		T3	3		T4	6
valid_sources[0x44]	7093	1			T1	6		T4	9		T5	3
valid_sources[0x45]	6642	1			T1	5		T3	5		T4	15
valid_sources[0x46]	13812	1			T1	4		T3	10		T4	4
valid_sources[0x47]	8352	1			T1	3		T3	462		T4	9
valid_sources[0x48]	7003	1			T1	3		T3	21		T4	6
valid_sources[0x49]	18800	1			T1	4		T3	18		T4	10
valid_sources[0x4a]	7848	1			T1	3		T3	14		T4	7
valid_sources[0x4b]	8870	1			T1	12		T3	2		T4	4
valid_sources[0x4c]	11307	1			T1	6		T3	17		T4	7
valid_sources[0x4d]	6550	1			T1	2		T3	6		T4	7
valid_sources[0x4e]	6579	1			T1	4		T3	5		T4	13
valid_sources[0x4f]	10797	1			T1	4		T3	1		T4	3
valid_sources[0x50]	7015	1			T1	4		T3	16		T4	6
valid_sources[0x51]	7017	1			T1	3		T3	13		T4	9
valid_sources[0x52]	9385	1			T1	1		T3	11		T4	5
valid_sources[0x53]	14800	1			T1	2		T3	15		T4	7
valid_sources[0x54]	16781	1			T1	3		T3	33		T4	6
valid_sources[0x55]	11134	1			T1	1		T3	4		T4	7
valid_sources[0x56]	6878	1			T1	5		T3	3		T4	10
valid_sources[0x57]	7562	1			T1	3		T3	13		T4	9
valid_sources[0x58]	7202	1			T1	2		T3	13		T4	10
valid_sources[0x59]	13832	1			T1	3		T3	5		T4	9
valid_sources[0x5a]	8091	1			T1	2		T3	3		T4	5
valid_sources[0x5b]	14246	1			T1	4		T4	8		T5	5
valid_sources[0x5c]	8749	1			T1	3		T4	6		T5	8
valid_sources[0x5d]	9755	1			T1	1		T3	3		T4	12
valid_sources[0x5e]	7143	1			T1	2		T3	4		T4	6
valid_sources[0x5f]	6866	1			T1	7		T3	12		T4	12
valid_sources[0x60]	7773	1			T1	4		T4	8		T6	5
valid_sources[0x61]	6899	1			T1	5		T3	30		T4	9
valid_sources[0x62]	10853	1			T1	5		T3	11		T4	9
valid_sources[0x63]	7048	1			T1	2		T3	1		T4	7
valid_sources[0x64]	11183	1			T1	6		T3	22		T4	7
valid_sources[0x65]	6615	1			T1	6		T3	3		T4	7
valid_sources[0x66]	8874	1			T1	1		T3	1		T4	7
valid_sources[0x67]	17599	1			T1	8		T3	19		T4	15
valid_sources[0x68]	15258	1			T1	4		T3	5		T4	11
valid_sources[0x69]	6725	1			T1	8		T3	1		T4	10
valid_sources[0x6a]	11477	1			T1	3		T4	8		T6	1
valid_sources[0x6b]	12075	1			T1	5		T3	5		T4	7
valid_sources[0x6c]	10508	1			T1	3		T3	3		T4	9
valid_sources[0x6d]	7103	1			T1	4		T3	5		T4	5
valid_sources[0x6e]	6858	1			T1	3		T3	23		T4	5
valid_sources[0x6f]	11289	1			T1	1		T3	6		T4	5
valid_sources[0x70]	7918	1			T1	6		T3	87		T4	12
valid_sources[0x71]	6871	1			T1	4		T3	54		T4	7
valid_sources[0x72]	7486	1			T1	3		T3	16		T4	10
valid_sources[0x73]	7119	1			T1	8		T3	5		T4	4
valid_sources[0x74]	6656	1			T1	5		T3	2		T4	8
valid_sources[0x75]	12608	1			T1	2		T3	31		T4	6
valid_sources[0x76]	7824	1			T1	6		T3	23		T4	11
valid_sources[0x77]	7979	1			T3	2		T4	10		T6	6
valid_sources[0x78]	11344	1			T3	9		T4	2		T5	7
valid_sources[0x79]	7002	1			T1	2		T3	17		T4	10
valid_sources[0x7a]	18426	1			T1	3		T3	24		T4	9
valid_sources[0x7b]	8066	1			T1	3		T3	2		T4	9
valid_sources[0x7c]	11604	1			T1	4		T3	1		T4	2
valid_sources[0x7d]	10910	1			T3	19		T4	7		T6	8
valid_sources[0x7e]	7256	1			T1	2		T3	40		T4	7
valid_sources[0x7f]	12296	1			T1	2		T3	17		T4	10
valid_sources[0x80]	7169	1			T1	2		T3	3		T4	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1058783

1

T1

12

T2

1997

T3

1435

values[0x0]

all_enables

biggest_size

82244

1

T1

226

T2

53

T3

249

values[0x1]

all_enables

biggest_size

59217

1

T1

135

T2

49

T3

212